1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * T104x RDB board configuration file 11 */ 12 #include <asm/config_mpc85xx.h> 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 16 #ifndef CONFIG_SECURE_BOOT 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #else 19 #define CONFIG_SYS_FSL_PBL_PBI \ 20 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 21 #endif 22 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 26 #define CONFIG_SPL_PAD_TO 0x40000 27 #define CONFIG_SPL_MAX_SIZE 0x28000 28 #ifdef CONFIG_SPL_BUILD 29 #define CONFIG_SPL_SKIP_RELOCATE 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 32 #endif 33 #define RESET_VECTOR_OFFSET 0x27FFC 34 #define BOOT_PAGE_OFFSET 0x27000 35 36 #ifdef CONFIG_NAND 37 #ifdef CONFIG_SECURE_BOOT 38 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 39 /* 40 * HDR would be appended at end of image and copied to DDR along 41 * with U-Boot image. 42 */ 43 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 44 CONFIG_U_BOOT_HDR_SIZE) 45 #else 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 47 #endif 48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 52 #ifdef CONFIG_TARGET_T1040RDB 53 #define CONFIG_SYS_FSL_PBL_RCW \ 54 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 55 #endif 56 #ifdef CONFIG_TARGET_T1042RDB_PI 57 #define CONFIG_SYS_FSL_PBL_RCW \ 58 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 59 #endif 60 #ifdef CONFIG_TARGET_T1042RDB 61 #define CONFIG_SYS_FSL_PBL_RCW \ 62 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 63 #endif 64 #ifdef CONFIG_TARGET_T1040D4RDB 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 67 #endif 68 #ifdef CONFIG_TARGET_T1042D4RDB 69 #define CONFIG_SYS_FSL_PBL_RCW \ 70 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 71 #endif 72 #define CONFIG_SPL_NAND_BOOT 73 #endif 74 75 #ifdef CONFIG_SPIFLASH 76 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 77 #define CONFIG_SPL_SPI_FLASH_MINIMAL 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #ifdef CONFIG_TARGET_T1040RDB 87 #define CONFIG_SYS_FSL_PBL_RCW \ 88 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 89 #endif 90 #ifdef CONFIG_TARGET_T1042RDB_PI 91 #define CONFIG_SYS_FSL_PBL_RCW \ 92 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 93 #endif 94 #ifdef CONFIG_TARGET_T1042RDB 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 97 #endif 98 #ifdef CONFIG_TARGET_T1040D4RDB 99 #define CONFIG_SYS_FSL_PBL_RCW \ 100 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 101 #endif 102 #ifdef CONFIG_TARGET_T1042D4RDB 103 #define CONFIG_SYS_FSL_PBL_RCW \ 104 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 105 #endif 106 #define CONFIG_SPL_SPI_BOOT 107 #endif 108 109 #ifdef CONFIG_SDCARD 110 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 111 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 112 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 113 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 114 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 115 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 116 #ifndef CONFIG_SPL_BUILD 117 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 118 #endif 119 #ifdef CONFIG_TARGET_T1040RDB 120 #define CONFIG_SYS_FSL_PBL_RCW \ 121 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 122 #endif 123 #ifdef CONFIG_TARGET_T1042RDB_PI 124 #define CONFIG_SYS_FSL_PBL_RCW \ 125 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 126 #endif 127 #ifdef CONFIG_TARGET_T1042RDB 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_TARGET_T1040D4RDB 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_TARGET_T1042D4RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 138 #endif 139 #define CONFIG_SPL_MMC_BOOT 140 #endif 141 142 #endif 143 144 /* High Level Configuration Options */ 145 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 146 147 /* support deep sleep */ 148 #define CONFIG_DEEP_SLEEP 149 150 #ifndef CONFIG_RESET_VECTOR_ADDRESS 151 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 152 #endif 153 154 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 155 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 156 #define CONFIG_PCI_INDIRECT_BRIDGE 157 #define CONFIG_PCIE1 /* PCIE controller 1 */ 158 #define CONFIG_PCIE2 /* PCIE controller 2 */ 159 #define CONFIG_PCIE3 /* PCIE controller 3 */ 160 #define CONFIG_PCIE4 /* PCIE controller 4 */ 161 162 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 163 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 164 165 #define CONFIG_ENV_OVERWRITE 166 167 #ifdef CONFIG_MTD_NOR_FLASH 168 #define CONFIG_FLASH_CFI_DRIVER 169 #define CONFIG_SYS_FLASH_CFI 170 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 171 #endif 172 173 #if defined(CONFIG_SPIFLASH) 174 #define CONFIG_SYS_EXTRA_ENV_RELOC 175 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 176 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 177 #define CONFIG_ENV_SECT_SIZE 0x10000 178 #elif defined(CONFIG_SDCARD) 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_SYS_MMC_ENV_DEV 0 181 #define CONFIG_ENV_SIZE 0x2000 182 #define CONFIG_ENV_OFFSET (512 * 0x800) 183 #elif defined(CONFIG_NAND) 184 #ifdef CONFIG_SECURE_BOOT 185 #define CONFIG_RAMBOOT_NAND 186 #define CONFIG_BOOTSCRIPT_COPY_RAM 187 #endif 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_ENV_SIZE 0x2000 190 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 191 #else 192 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 193 #define CONFIG_ENV_SIZE 0x2000 194 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 195 #endif 196 197 #define CONFIG_SYS_CLK_FREQ 100000000 198 #define CONFIG_DDR_CLK_FREQ 66666666 199 200 /* 201 * These can be toggled for performance analysis, otherwise use default. 202 */ 203 #define CONFIG_SYS_CACHE_STASHING 204 #define CONFIG_BACKSIDE_L2_CACHE 205 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 206 #define CONFIG_BTB /* toggle branch predition */ 207 #define CONFIG_DDR_ECC 208 #ifdef CONFIG_DDR_ECC 209 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 210 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 211 #endif 212 213 #define CONFIG_ENABLE_36BIT_PHYS 214 215 #define CONFIG_ADDR_MAP 216 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 217 218 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 219 #define CONFIG_SYS_MEMTEST_END 0x00400000 220 221 /* 222 * Config the L3 Cache as L3 SRAM 223 */ 224 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 225 /* 226 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 227 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 228 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 229 */ 230 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 231 #define CONFIG_SYS_L3_SIZE 256 << 10 232 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 233 #ifdef CONFIG_RAMBOOT_PBL 234 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 235 #endif 236 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 237 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 238 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 239 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 240 241 #define CONFIG_SYS_DCSRBAR 0xf0000000 242 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 243 244 /* 245 * DDR Setup 246 */ 247 #define CONFIG_VERY_BIG_RAM 248 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 249 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 250 251 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 252 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 253 254 #define CONFIG_DDR_SPD 255 256 #define CONFIG_SYS_SPD_BUS_NUM 0 257 #define SPD_EEPROM_ADDRESS 0x51 258 259 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 260 261 /* 262 * IFC Definitions 263 */ 264 #define CONFIG_SYS_FLASH_BASE 0xe8000000 265 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 266 267 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 268 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 269 CSPR_PORT_SIZE_16 | \ 270 CSPR_MSEL_NOR | \ 271 CSPR_V) 272 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 273 274 /* 275 * TDM Definition 276 */ 277 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 278 279 /* NOR Flash Timing Params */ 280 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 281 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 282 FTIM0_NOR_TEADC(0x5) | \ 283 FTIM0_NOR_TEAHC(0x5)) 284 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 285 FTIM1_NOR_TRAD_NOR(0x1A) |\ 286 FTIM1_NOR_TSEQRAD_NOR(0x13)) 287 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 288 FTIM2_NOR_TCH(0x4) | \ 289 FTIM2_NOR_TWPH(0x0E) | \ 290 FTIM2_NOR_TWP(0x1c)) 291 #define CONFIG_SYS_NOR_FTIM3 0x0 292 293 #define CONFIG_SYS_FLASH_QUIET_TEST 294 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 295 296 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 297 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 298 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 299 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 300 301 #define CONFIG_SYS_FLASH_EMPTY_INFO 302 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 303 304 /* CPLD on IFC */ 305 #define CPLD_LBMAP_MASK 0x3F 306 #define CPLD_BANK_SEL_MASK 0x07 307 #define CPLD_BANK_OVERRIDE 0x40 308 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 309 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 310 #define CPLD_LBMAP_RESET 0xFF 311 #define CPLD_LBMAP_SHIFT 0x03 312 313 #if defined(CONFIG_TARGET_T1042RDB_PI) 314 #define CPLD_DIU_SEL_DFP 0x80 315 #elif defined(CONFIG_TARGET_T1042D4RDB) 316 #define CPLD_DIU_SEL_DFP 0xc0 317 #endif 318 319 #if defined(CONFIG_TARGET_T1040D4RDB) 320 #define CPLD_INT_MASK_ALL 0xFF 321 #define CPLD_INT_MASK_THERM 0x80 322 #define CPLD_INT_MASK_DVI_DFP 0x40 323 #define CPLD_INT_MASK_QSGMII1 0x20 324 #define CPLD_INT_MASK_QSGMII2 0x10 325 #define CPLD_INT_MASK_SGMI1 0x08 326 #define CPLD_INT_MASK_SGMI2 0x04 327 #define CPLD_INT_MASK_TDMR1 0x02 328 #define CPLD_INT_MASK_TDMR2 0x01 329 #endif 330 331 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 332 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 333 #define CONFIG_SYS_CSPR2_EXT (0xf) 334 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 335 | CSPR_PORT_SIZE_8 \ 336 | CSPR_MSEL_GPCM \ 337 | CSPR_V) 338 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 339 #define CONFIG_SYS_CSOR2 0x0 340 /* CPLD Timing parameters for IFC CS2 */ 341 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 342 FTIM0_GPCM_TEADC(0x0e) | \ 343 FTIM0_GPCM_TEAHC(0x0e)) 344 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 345 FTIM1_GPCM_TRAD(0x1f)) 346 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 347 FTIM2_GPCM_TCH(0x8) | \ 348 FTIM2_GPCM_TWP(0x1f)) 349 #define CONFIG_SYS_CS2_FTIM3 0x0 350 351 /* NAND Flash on IFC */ 352 #define CONFIG_NAND_FSL_IFC 353 #define CONFIG_SYS_NAND_BASE 0xff800000 354 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 355 356 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 357 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 358 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 359 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 360 | CSPR_V) 361 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 362 363 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 364 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 365 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 366 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 367 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 368 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 369 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 370 371 #define CONFIG_SYS_NAND_ONFI_DETECTION 372 373 /* ONFI NAND Flash mode0 Timing Params */ 374 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 375 FTIM0_NAND_TWP(0x18) | \ 376 FTIM0_NAND_TWCHT(0x07) | \ 377 FTIM0_NAND_TWH(0x0a)) 378 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 379 FTIM1_NAND_TWBE(0x39) | \ 380 FTIM1_NAND_TRR(0x0e) | \ 381 FTIM1_NAND_TRP(0x18)) 382 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 383 FTIM2_NAND_TREH(0x0a) | \ 384 FTIM2_NAND_TWHRE(0x1e)) 385 #define CONFIG_SYS_NAND_FTIM3 0x0 386 387 #define CONFIG_SYS_NAND_DDR_LAW 11 388 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 389 #define CONFIG_SYS_MAX_NAND_DEVICE 1 390 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 392 393 #if defined(CONFIG_NAND) 394 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 395 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 396 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 397 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 398 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 399 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 400 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 401 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 402 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 403 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 404 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 405 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 406 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 407 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 408 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 409 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 410 #else 411 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 412 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 413 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 420 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 421 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 422 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 423 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 424 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 425 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 426 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 427 #endif 428 429 #ifdef CONFIG_SPL_BUILD 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 431 #else 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 433 #endif 434 435 #if defined(CONFIG_RAMBOOT_PBL) 436 #define CONFIG_SYS_RAMBOOT 437 #endif 438 439 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 440 #if defined(CONFIG_NAND) 441 #define CONFIG_A008044_WORKAROUND 442 #endif 443 #endif 444 445 #define CONFIG_MISC_INIT_R 446 447 #define CONFIG_HWCONFIG 448 449 /* define to use L1 as initial stack */ 450 #define CONFIG_L1_INIT_RAM 451 #define CONFIG_SYS_INIT_RAM_LOCK 452 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 455 /* The assembler doesn't like typecast */ 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 457 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 458 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 459 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 460 461 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 462 GENERATED_GBL_DATA_SIZE) 463 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 464 465 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 466 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 467 468 /* Serial Port - controlled on board with jumper J8 469 * open - index 2 470 * shorted - index 1 471 */ 472 #define CONFIG_SYS_NS16550_SERIAL 473 #define CONFIG_SYS_NS16550_REG_SIZE 1 474 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 475 476 #define CONFIG_SYS_BAUDRATE_TABLE \ 477 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 478 479 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 480 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 481 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 482 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 483 484 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 485 /* Video */ 486 #define CONFIG_FSL_DIU_FB 487 488 #ifdef CONFIG_FSL_DIU_FB 489 #define CONFIG_FSL_DIU_CH7301 490 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 491 #define CONFIG_VIDEO_LOGO 492 #define CONFIG_VIDEO_BMP_LOGO 493 #endif 494 #endif 495 496 /* I2C */ 497 #define CONFIG_SYS_I2C 498 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 499 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 500 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 501 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 502 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 503 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 504 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 505 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 506 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 507 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 508 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 509 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 510 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 511 512 /* I2C bus multiplexer */ 513 #define I2C_MUX_PCA_ADDR 0x70 514 #define I2C_MUX_CH_DEFAULT 0x8 515 516 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 517 defined(CONFIG_TARGET_T1040D4RDB) || \ 518 defined(CONFIG_TARGET_T1042D4RDB) 519 /* LDI/DVI Encoder for display */ 520 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 521 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 522 523 /* 524 * RTC configuration 525 */ 526 #define RTC 527 #define CONFIG_RTC_DS1337 1 528 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 529 530 /*DVI encoder*/ 531 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 532 #endif 533 534 /* 535 * eSPI - Enhanced SPI 536 */ 537 #define CONFIG_SPI_FLASH_BAR 538 #define CONFIG_SF_DEFAULT_SPEED 10000000 539 #define CONFIG_SF_DEFAULT_MODE 0 540 #define CONFIG_ENV_SPI_BUS 0 541 #define CONFIG_ENV_SPI_CS 0 542 #define CONFIG_ENV_SPI_MAX_HZ 10000000 543 #define CONFIG_ENV_SPI_MODE 0 544 545 /* 546 * General PCI 547 * Memory space is mapped 1-1, but I/O space must start from 0. 548 */ 549 550 #ifdef CONFIG_PCI 551 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 552 #ifdef CONFIG_PCIE1 553 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 554 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 555 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 556 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 557 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 558 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 559 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 560 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 561 #endif 562 563 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 564 #ifdef CONFIG_PCIE2 565 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 566 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 568 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 569 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 570 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 571 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 572 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 573 #endif 574 575 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 576 #ifdef CONFIG_PCIE3 577 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 578 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 580 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 582 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 583 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 584 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 585 #endif 586 587 /* controller 4, Base address 203000 */ 588 #ifdef CONFIG_PCIE4 589 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 590 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 592 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 593 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 594 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 595 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 596 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 597 #endif 598 599 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 600 #endif /* CONFIG_PCI */ 601 602 /* SATA */ 603 #define CONFIG_FSL_SATA_V2 604 #ifdef CONFIG_FSL_SATA_V2 605 #define CONFIG_SYS_SATA_MAX_DEVICE 1 606 #define CONFIG_SATA1 607 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 608 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 609 610 #define CONFIG_LBA48 611 #endif 612 613 /* 614 * USB 615 */ 616 #define CONFIG_HAS_FSL_DR_USB 617 618 #ifdef CONFIG_HAS_FSL_DR_USB 619 #ifdef CONFIG_USB_EHCI_HCD 620 #define CONFIG_USB_EHCI_FSL 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 622 #define CONFIG_EHCI_DESC_BIG_ENDIAN 623 #endif 624 #endif 625 626 #ifdef CONFIG_MMC 627 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 628 #endif 629 630 /* Qman/Bman */ 631 #ifndef CONFIG_NOBQFMAN 632 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 633 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 634 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 635 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 636 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 637 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 638 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 639 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 640 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 641 CONFIG_SYS_BMAN_CENA_SIZE) 642 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 643 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 644 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 645 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 646 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 647 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 648 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 649 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 650 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 651 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 653 CONFIG_SYS_QMAN_CENA_SIZE) 654 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 655 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 656 657 #define CONFIG_SYS_DPAA_FMAN 658 #define CONFIG_SYS_DPAA_PME 659 660 #define CONFIG_QE 661 #define CONFIG_U_QE 662 663 /* Default address of microcode for the Linux Fman driver */ 664 #if defined(CONFIG_SPIFLASH) 665 /* 666 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 667 * env, so we got 0x110000. 668 */ 669 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 670 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 671 #elif defined(CONFIG_SDCARD) 672 /* 673 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 674 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 675 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 676 */ 677 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 678 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 679 #elif defined(CONFIG_NAND) 680 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 681 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 682 #else 683 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 684 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 685 #endif 686 687 #if defined(CONFIG_SPIFLASH) 688 #define CONFIG_SYS_QE_FW_ADDR 0x130000 689 #elif defined(CONFIG_SDCARD) 690 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 691 #elif defined(CONFIG_NAND) 692 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 693 #else 694 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 695 #endif 696 697 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 698 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 699 #endif /* CONFIG_NOBQFMAN */ 700 701 #ifdef CONFIG_SYS_DPAA_FMAN 702 #define CONFIG_FMAN_ENET 703 #define CONFIG_PHY_VITESSE 704 #define CONFIG_PHY_REALTEK 705 #endif 706 707 #ifdef CONFIG_FMAN_ENET 708 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 709 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 710 #elif defined(CONFIG_TARGET_T1040D4RDB) 711 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 712 #elif defined(CONFIG_TARGET_T1042D4RDB) 713 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 714 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 715 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 716 #endif 717 718 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 719 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 720 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 721 #else 722 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 723 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 724 #endif 725 726 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 727 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 728 #define CONFIG_VSC9953 729 #ifdef CONFIG_TARGET_T1040RDB 730 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 731 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 732 #else 733 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 734 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 735 #endif 736 #endif 737 738 #define CONFIG_MII /* MII PHY management */ 739 #define CONFIG_ETHPRIME "FM1@DTSEC4" 740 #endif 741 742 /* 743 * Environment 744 */ 745 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 746 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 747 748 /* 749 * Miscellaneous configurable options 750 */ 751 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 752 753 /* 754 * For booting Linux, the board info and command line data 755 * have to be in the first 64 MB of memory, since this is 756 * the maximum mapped by the Linux kernel during initialization. 757 */ 758 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 759 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 760 761 #ifdef CONFIG_CMD_KGDB 762 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 763 #endif 764 765 /* 766 * Dynamic MTD Partition support with mtdparts 767 */ 768 #ifdef CONFIG_MTD_NOR_FLASH 769 #define CONFIG_FLASH_CFI_MTD 770 #endif 771 772 /* 773 * Environment Configuration 774 */ 775 #define CONFIG_ROOTPATH "/opt/nfsroot" 776 #define CONFIG_BOOTFILE "uImage" 777 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 778 779 /* default location for tftp and bootm */ 780 #define CONFIG_LOADADDR 1000000 781 782 #define __USB_PHY_TYPE utmi 783 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 784 785 #ifdef CONFIG_TARGET_T1040RDB 786 #define FDTFILE "t1040rdb/t1040rdb.dtb" 787 #elif defined(CONFIG_TARGET_T1042RDB_PI) 788 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 789 #elif defined(CONFIG_TARGET_T1042RDB) 790 #define FDTFILE "t1042rdb/t1042rdb.dtb" 791 #elif defined(CONFIG_TARGET_T1040D4RDB) 792 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 793 #elif defined(CONFIG_TARGET_T1042D4RDB) 794 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 795 #endif 796 797 #ifdef CONFIG_FSL_DIU_FB 798 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 799 #else 800 #define DIU_ENVIRONMENT 801 #endif 802 803 #define CONFIG_EXTRA_ENV_SETTINGS \ 804 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 805 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 806 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 807 "netdev=eth0\0" \ 808 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 809 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 810 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 811 "tftpflash=tftpboot $loadaddr $uboot && " \ 812 "protect off $ubootaddr +$filesize && " \ 813 "erase $ubootaddr +$filesize && " \ 814 "cp.b $loadaddr $ubootaddr $filesize && " \ 815 "protect on $ubootaddr +$filesize && " \ 816 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 817 "consoledev=ttyS0\0" \ 818 "ramdiskaddr=2000000\0" \ 819 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 820 "fdtaddr=1e00000\0" \ 821 "fdtfile=" __stringify(FDTFILE) "\0" \ 822 "bdev=sda3\0" 823 824 #define CONFIG_LINUX \ 825 "setenv bootargs root=/dev/ram rw " \ 826 "console=$consoledev,$baudrate $othbootargs;" \ 827 "setenv ramdiskaddr 0x02000000;" \ 828 "setenv fdtaddr 0x00c00000;" \ 829 "setenv loadaddr 0x1000000;" \ 830 "bootm $loadaddr $ramdiskaddr $fdtaddr" 831 832 #define CONFIG_HDBOOT \ 833 "setenv bootargs root=/dev/$bdev rw " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "tftp $loadaddr $bootfile;" \ 836 "tftp $fdtaddr $fdtfile;" \ 837 "bootm $loadaddr - $fdtaddr" 838 839 #define CONFIG_NFSBOOTCOMMAND \ 840 "setenv bootargs root=/dev/nfs rw " \ 841 "nfsroot=$serverip:$rootpath " \ 842 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 843 "console=$consoledev,$baudrate $othbootargs;" \ 844 "tftp $loadaddr $bootfile;" \ 845 "tftp $fdtaddr $fdtfile;" \ 846 "bootm $loadaddr - $fdtaddr" 847 848 #define CONFIG_RAMBOOTCOMMAND \ 849 "setenv bootargs root=/dev/ram rw " \ 850 "console=$consoledev,$baudrate $othbootargs;" \ 851 "tftp $ramdiskaddr $ramdiskfile;" \ 852 "tftp $loadaddr $bootfile;" \ 853 "tftp $fdtaddr $fdtfile;" \ 854 "bootm $loadaddr $ramdiskaddr $fdtaddr" 855 856 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 857 858 #include <asm/fsl_secure_boot.h> 859 860 #endif /* __CONFIG_H */ 861