1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #ifdef CONFIG_T1040RDB 19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 20 #endif 21 #ifdef CONFIG_T1042RDB_PI 22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 23 #endif 24 25 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 26 #define CONFIG_SPL_ENV_SUPPORT 27 #define CONFIG_SPL_SERIAL_SUPPORT 28 #define CONFIG_SPL_FLUSH_IMAGE 29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 30 #define CONFIG_SPL_LIBGENERIC_SUPPORT 31 #define CONFIG_SPL_LIBCOMMON_SUPPORT 32 #define CONFIG_SPL_I2C_SUPPORT 33 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_SYS_TEXT_BASE 0x30001000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #ifdef CONFIG_SPL_BUILD 40 #define CONFIG_SPL_SKIP_RELOCATE 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 43 #define CONFIG_SYS_NO_FLASH 44 #endif 45 #define RESET_VECTOR_OFFSET 0x27FFC 46 #define BOOT_PAGE_OFFSET 0x27000 47 48 #ifdef CONFIG_NAND 49 #define CONFIG_SPL_NAND_SUPPORT 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #define CONFIG_SPL_NAND_BOOT 56 #endif 57 58 #ifdef CONFIG_SPIFLASH 59 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 60 #define CONFIG_SPL_SPI_SUPPORT 61 #define CONFIG_SPL_SPI_FLASH_SUPPORT 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #define CONFIG_SPL_SPI_BOOT 72 #endif 73 74 #ifdef CONFIG_SDCARD 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_MMC_SUPPORT 77 #define CONFIG_SPL_MMC_MINIMAL 78 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 80 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 81 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SPL_MMC_BOOT 87 #endif 88 89 #endif 90 91 /* High Level Configuration Options */ 92 #define CONFIG_BOOKE 93 #define CONFIG_E500 /* BOOKE e500 family */ 94 #define CONFIG_E500MC /* BOOKE e500mc family */ 95 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 96 #define CONFIG_MP /* support multiple processors */ 97 98 /* support deep sleep */ 99 #define CONFIG_DEEP_SLEEP 100 #define CONFIG_SILENT_CONSOLE 101 102 #ifndef CONFIG_SYS_TEXT_BASE 103 #define CONFIG_SYS_TEXT_BASE 0xeff40000 104 #endif 105 106 #ifndef CONFIG_RESET_VECTOR_ADDRESS 107 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 108 #endif 109 110 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 111 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 112 #define CONFIG_FSL_IFC /* Enable IFC Support */ 113 #define CONFIG_PCI /* Enable PCI/PCIE */ 114 #define CONFIG_PCI_INDIRECT_BRIDGE 115 #define CONFIG_PCIE1 /* PCIE controler 1 */ 116 #define CONFIG_PCIE2 /* PCIE controler 2 */ 117 #define CONFIG_PCIE3 /* PCIE controler 3 */ 118 #define CONFIG_PCIE4 /* PCIE controler 4 */ 119 120 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 121 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 122 123 #define CONFIG_FSL_LAW /* Use common FSL init code */ 124 125 #define CONFIG_ENV_OVERWRITE 126 127 #ifndef CONFIG_SYS_NO_FLASH 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 131 #endif 132 133 #if defined(CONFIG_SPIFLASH) 134 #define CONFIG_SYS_EXTRA_ENV_RELOC 135 #define CONFIG_ENV_IS_IN_SPI_FLASH 136 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 137 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 138 #define CONFIG_ENV_SECT_SIZE 0x10000 139 #elif defined(CONFIG_SDCARD) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_IS_IN_MMC 142 #define CONFIG_SYS_MMC_ENV_DEV 0 143 #define CONFIG_ENV_SIZE 0x2000 144 #define CONFIG_ENV_OFFSET (512 * 0x800) 145 #elif defined(CONFIG_NAND) 146 #define CONFIG_SYS_EXTRA_ENV_RELOC 147 #define CONFIG_ENV_IS_IN_NAND 148 #define CONFIG_ENV_SIZE 0x2000 149 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 150 #else 151 #define CONFIG_ENV_IS_IN_FLASH 152 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 153 #define CONFIG_ENV_SIZE 0x2000 154 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 155 #endif 156 157 #define CONFIG_SYS_CLK_FREQ 100000000 158 #define CONFIG_DDR_CLK_FREQ 66666666 159 160 /* 161 * These can be toggled for performance analysis, otherwise use default. 162 */ 163 #define CONFIG_SYS_CACHE_STASHING 164 #define CONFIG_BACKSIDE_L2_CACHE 165 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 166 #define CONFIG_BTB /* toggle branch predition */ 167 #define CONFIG_DDR_ECC 168 #ifdef CONFIG_DDR_ECC 169 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 170 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 171 #endif 172 173 #define CONFIG_ENABLE_36BIT_PHYS 174 175 #define CONFIG_ADDR_MAP 176 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 177 178 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 179 #define CONFIG_SYS_MEMTEST_END 0x00400000 180 #define CONFIG_SYS_ALT_MEMTEST 181 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 182 183 /* 184 * Config the L3 Cache as L3 SRAM 185 */ 186 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 187 #define CONFIG_SYS_L3_SIZE 256 << 10 188 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 189 #ifdef CONFIG_RAMBOOT_PBL 190 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 191 #endif 192 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 193 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 194 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 195 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 196 197 #define CONFIG_SYS_DCSRBAR 0xf0000000 198 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 199 200 /* 201 * DDR Setup 202 */ 203 #define CONFIG_VERY_BIG_RAM 204 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 205 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 206 207 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 208 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 209 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 210 211 #define CONFIG_DDR_SPD 212 #define CONFIG_SYS_DDR_RAW_TIMING 213 #define CONFIG_SYS_FSL_DDR3 214 215 #define CONFIG_SYS_SPD_BUS_NUM 0 216 #define SPD_EEPROM_ADDRESS 0x51 217 218 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 219 220 /* 221 * IFC Definitions 222 */ 223 #define CONFIG_SYS_FLASH_BASE 0xe8000000 224 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 225 226 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 227 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 228 CSPR_PORT_SIZE_16 | \ 229 CSPR_MSEL_NOR | \ 230 CSPR_V) 231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 232 233 /* 234 * TDM Definition 235 */ 236 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 237 238 /* NOR Flash Timing Params */ 239 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 240 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 241 FTIM0_NOR_TEADC(0x5) | \ 242 FTIM0_NOR_TEAHC(0x5)) 243 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 244 FTIM1_NOR_TRAD_NOR(0x1A) |\ 245 FTIM1_NOR_TSEQRAD_NOR(0x13)) 246 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 247 FTIM2_NOR_TCH(0x4) | \ 248 FTIM2_NOR_TWPH(0x0E) | \ 249 FTIM2_NOR_TWP(0x1c)) 250 #define CONFIG_SYS_NOR_FTIM3 0x0 251 252 #define CONFIG_SYS_FLASH_QUIET_TEST 253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 254 255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 256 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 257 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 258 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 259 260 #define CONFIG_SYS_FLASH_EMPTY_INFO 261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 262 263 /* CPLD on IFC */ 264 #define CPLD_LBMAP_MASK 0x3F 265 #define CPLD_BANK_SEL_MASK 0x07 266 #define CPLD_BANK_OVERRIDE 0x40 267 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 268 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 269 #define CPLD_LBMAP_RESET 0xFF 270 #define CPLD_LBMAP_SHIFT 0x03 271 #ifdef CONFIG_T1042RDB_PI 272 #define CPLD_DIU_SEL_DFP 0x80 273 #endif 274 275 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 276 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 277 #define CONFIG_SYS_CSPR2_EXT (0xf) 278 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 279 | CSPR_PORT_SIZE_8 \ 280 | CSPR_MSEL_GPCM \ 281 | CSPR_V) 282 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 283 #define CONFIG_SYS_CSOR2 0x0 284 /* CPLD Timing parameters for IFC CS2 */ 285 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 286 FTIM0_GPCM_TEADC(0x0e) | \ 287 FTIM0_GPCM_TEAHC(0x0e)) 288 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 289 FTIM1_GPCM_TRAD(0x1f)) 290 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 291 FTIM2_GPCM_TCH(0x8) | \ 292 FTIM2_GPCM_TWP(0x1f)) 293 #define CONFIG_SYS_CS2_FTIM3 0x0 294 295 /* NAND Flash on IFC */ 296 #define CONFIG_NAND_FSL_IFC 297 #define CONFIG_SYS_NAND_BASE 0xff800000 298 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 299 300 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 301 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 302 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 303 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 304 | CSPR_V) 305 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 306 307 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 308 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 309 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 310 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 311 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 312 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 313 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 314 315 #define CONFIG_SYS_NAND_ONFI_DETECTION 316 317 /* ONFI NAND Flash mode0 Timing Params */ 318 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 319 FTIM0_NAND_TWP(0x18) | \ 320 FTIM0_NAND_TWCHT(0x07) | \ 321 FTIM0_NAND_TWH(0x0a)) 322 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 323 FTIM1_NAND_TWBE(0x39) | \ 324 FTIM1_NAND_TRR(0x0e) | \ 325 FTIM1_NAND_TRP(0x18)) 326 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 327 FTIM2_NAND_TREH(0x0a) | \ 328 FTIM2_NAND_TWHRE(0x1e)) 329 #define CONFIG_SYS_NAND_FTIM3 0x0 330 331 #define CONFIG_SYS_NAND_DDR_LAW 11 332 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 333 #define CONFIG_SYS_MAX_NAND_DEVICE 1 334 #define CONFIG_MTD_NAND_VERIFY_WRITE 335 #define CONFIG_CMD_NAND 336 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 338 339 #if defined(CONFIG_NAND) 340 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 348 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 349 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 350 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 351 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 352 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 353 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 354 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 355 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 356 #else 357 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 366 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 367 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 368 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 369 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 370 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 371 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 372 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 373 #endif 374 375 #ifdef CONFIG_SPL_BUILD 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 377 #else 378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 379 #endif 380 381 #if defined(CONFIG_RAMBOOT_PBL) 382 #define CONFIG_SYS_RAMBOOT 383 #endif 384 385 #define CONFIG_BOARD_EARLY_INIT_R 386 #define CONFIG_MISC_INIT_R 387 388 #define CONFIG_HWCONFIG 389 390 /* define to use L1 as initial stack */ 391 #define CONFIG_L1_INIT_RAM 392 #define CONFIG_SYS_INIT_RAM_LOCK 393 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 396 /* The assembler doesn't like typecast */ 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 398 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 399 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 400 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 401 402 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 403 GENERATED_GBL_DATA_SIZE) 404 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 405 406 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 407 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 408 409 /* Serial Port - controlled on board with jumper J8 410 * open - index 2 411 * shorted - index 1 412 */ 413 #define CONFIG_CONS_INDEX 1 414 #define CONFIG_SYS_NS16550 415 #define CONFIG_SYS_NS16550_SERIAL 416 #define CONFIG_SYS_NS16550_REG_SIZE 1 417 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 418 419 #define CONFIG_SYS_BAUDRATE_TABLE \ 420 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 421 422 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 423 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 424 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 425 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 426 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 427 #ifndef CONFIG_SPL_BUILD 428 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 429 #endif 430 431 /* Use the HUSH parser */ 432 #define CONFIG_SYS_HUSH_PARSER 433 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 434 435 #ifdef CONFIG_T1042RDB_PI 436 /* Video */ 437 #define CONFIG_FSL_DIU_FB 438 439 #ifdef CONFIG_FSL_DIU_FB 440 #define CONFIG_FSL_DIU_CH7301 441 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 442 #define CONFIG_VIDEO 443 #define CONFIG_CMD_BMP 444 #define CONFIG_CFB_CONSOLE 445 #define CONFIG_CFB_CONSOLE_ANSI 446 #define CONFIG_VIDEO_SW_CURSOR 447 #define CONFIG_VGA_AS_SINGLE_DEVICE 448 #define CONFIG_VIDEO_LOGO 449 #define CONFIG_VIDEO_BMP_LOGO 450 #endif 451 #endif 452 453 /* pass open firmware flat tree */ 454 #define CONFIG_OF_LIBFDT 455 #define CONFIG_OF_BOARD_SETUP 456 #define CONFIG_OF_STDOUT_VIA_ALIAS 457 458 /* new uImage format support */ 459 #define CONFIG_FIT 460 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 461 462 /* I2C */ 463 #define CONFIG_SYS_I2C 464 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 465 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 466 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 467 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 468 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 469 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 470 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 471 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 472 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 473 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 474 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 475 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 476 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 477 478 /* I2C bus multiplexer */ 479 #define I2C_MUX_PCA_ADDR 0x70 480 #ifdef CONFIG_T1040RDB 481 #define I2C_MUX_CH_DEFAULT 0x8 482 #endif 483 484 #ifdef CONFIG_T1042RDB_PI 485 /* LDI/DVI Encoder for display */ 486 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 487 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 488 489 /* 490 * RTC configuration 491 */ 492 #define RTC 493 #define CONFIG_RTC_DS1337 1 494 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 495 496 /*DVI encoder*/ 497 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 498 #endif 499 500 /* 501 * eSPI - Enhanced SPI 502 */ 503 #define CONFIG_FSL_ESPI 504 #define CONFIG_SPI_FLASH 505 #define CONFIG_SPI_FLASH_STMICRO 506 #define CONFIG_SPI_FLASH_BAR 507 #define CONFIG_CMD_SF 508 #define CONFIG_SF_DEFAULT_SPEED 10000000 509 #define CONFIG_SF_DEFAULT_MODE 0 510 #define CONFIG_ENV_SPI_BUS 0 511 #define CONFIG_ENV_SPI_CS 0 512 #define CONFIG_ENV_SPI_MAX_HZ 10000000 513 #define CONFIG_ENV_SPI_MODE 0 514 515 /* 516 * General PCI 517 * Memory space is mapped 1-1, but I/O space must start from 0. 518 */ 519 520 #ifdef CONFIG_PCI 521 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 522 #ifdef CONFIG_PCIE1 523 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 524 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 526 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 527 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 528 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 529 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 530 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 531 #endif 532 533 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 534 #ifdef CONFIG_PCIE2 535 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 536 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 537 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 538 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 539 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 540 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 541 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 542 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 543 #endif 544 545 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 546 #ifdef CONFIG_PCIE3 547 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 548 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 549 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 550 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 551 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 552 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 553 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 554 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 555 #endif 556 557 /* controller 4, Base address 203000 */ 558 #ifdef CONFIG_PCIE4 559 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 560 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 562 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 563 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 564 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 565 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 566 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 567 #endif 568 569 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 570 #define CONFIG_E1000 571 572 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 573 #define CONFIG_DOS_PARTITION 574 #endif /* CONFIG_PCI */ 575 576 /* SATA */ 577 #define CONFIG_FSL_SATA_V2 578 #ifdef CONFIG_FSL_SATA_V2 579 #define CONFIG_LIBATA 580 #define CONFIG_FSL_SATA 581 582 #define CONFIG_SYS_SATA_MAX_DEVICE 1 583 #define CONFIG_SATA1 584 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 585 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 586 587 #define CONFIG_LBA48 588 #define CONFIG_CMD_SATA 589 #define CONFIG_DOS_PARTITION 590 #define CONFIG_CMD_EXT2 591 #endif 592 593 /* 594 * USB 595 */ 596 #define CONFIG_HAS_FSL_DR_USB 597 598 #ifdef CONFIG_HAS_FSL_DR_USB 599 #define CONFIG_USB_EHCI 600 601 #ifdef CONFIG_USB_EHCI 602 #define CONFIG_CMD_USB 603 #define CONFIG_USB_STORAGE 604 #define CONFIG_USB_EHCI_FSL 605 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 606 #define CONFIG_CMD_EXT2 607 #endif 608 #endif 609 610 #define CONFIG_MMC 611 612 #ifdef CONFIG_MMC 613 #define CONFIG_FSL_ESDHC 614 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 615 #define CONFIG_CMD_MMC 616 #define CONFIG_GENERIC_MMC 617 #define CONFIG_CMD_EXT2 618 #define CONFIG_CMD_FAT 619 #define CONFIG_DOS_PARTITION 620 #endif 621 622 /* Qman/Bman */ 623 #ifndef CONFIG_NOBQFMAN 624 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 625 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 626 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 627 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 628 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 629 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 630 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 631 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 632 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 633 634 #define CONFIG_SYS_DPAA_FMAN 635 #define CONFIG_SYS_DPAA_PME 636 637 #ifdef CONFIG_T1040RDB 638 #define CONFIG_QE 639 #define CONFIG_U_QE 640 #endif 641 642 /* Default address of microcode for the Linux Fman driver */ 643 #if defined(CONFIG_SPIFLASH) 644 /* 645 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 646 * env, so we got 0x110000. 647 */ 648 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 649 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 650 #elif defined(CONFIG_SDCARD) 651 /* 652 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 653 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 654 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 655 */ 656 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 657 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 658 #elif defined(CONFIG_NAND) 659 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 660 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 661 #else 662 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 663 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 664 #endif 665 666 #ifdef CONFIG_T1040RDB 667 #if defined(CONFIG_SPIFLASH) 668 #define CONFIG_SYS_QE_FW_ADDR 0x130000 669 #elif defined(CONFIG_SDCARD) 670 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 671 #elif defined(CONFIG_NAND) 672 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 673 #else 674 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 675 #endif 676 #endif 677 678 679 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 680 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 681 #endif /* CONFIG_NOBQFMAN */ 682 683 #ifdef CONFIG_SYS_DPAA_FMAN 684 #define CONFIG_FMAN_ENET 685 #define CONFIG_PHY_VITESSE 686 #define CONFIG_PHY_REALTEK 687 #endif 688 689 #ifdef CONFIG_FMAN_ENET 690 #ifdef CONFIG_T1040RDB 691 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 692 #endif 693 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 694 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 695 696 #define CONFIG_MII /* MII PHY management */ 697 #define CONFIG_ETHPRIME "FM1@DTSEC4" 698 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 699 #endif 700 701 /* 702 * Environment 703 */ 704 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 705 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 706 707 /* 708 * Command line configuration. 709 */ 710 #include <config_cmd_default.h> 711 712 #ifdef CONFIG_T1042RDB_PI 713 #define CONFIG_CMD_DATE 714 #endif 715 #define CONFIG_CMD_DHCP 716 #define CONFIG_CMD_ELF 717 #define CONFIG_CMD_ERRATA 718 #define CONFIG_CMD_GREPENV 719 #define CONFIG_CMD_IRQ 720 #define CONFIG_CMD_I2C 721 #define CONFIG_CMD_MII 722 #define CONFIG_CMD_PING 723 #define CONFIG_CMD_REGINFO 724 #define CONFIG_CMD_SETEXPR 725 726 #ifdef CONFIG_PCI 727 #define CONFIG_CMD_PCI 728 #define CONFIG_CMD_NET 729 #endif 730 731 /* 732 * Miscellaneous configurable options 733 */ 734 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 735 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 736 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 737 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 738 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 739 #ifdef CONFIG_CMD_KGDB 740 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 741 #else 742 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 743 #endif 744 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 745 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 746 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 747 748 /* 749 * For booting Linux, the board info and command line data 750 * have to be in the first 64 MB of memory, since this is 751 * the maximum mapped by the Linux kernel during initialization. 752 */ 753 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 754 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 755 756 #ifdef CONFIG_CMD_KGDB 757 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 758 #endif 759 760 /* 761 * Dynamic MTD Partition support with mtdparts 762 */ 763 #ifndef CONFIG_SYS_NO_FLASH 764 #define CONFIG_MTD_DEVICE 765 #define CONFIG_MTD_PARTITIONS 766 #define CONFIG_CMD_MTDPARTS 767 #define CONFIG_FLASH_CFI_MTD 768 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 769 "spi0=spife110000.0" 770 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 771 "128k(dtb),96m(fs),-(user);"\ 772 "fff800000.flash:2m(uboot),9m(kernel),"\ 773 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 774 "2m(uboot),9m(kernel),128k(dtb),-(user)" 775 #endif 776 777 /* 778 * Environment Configuration 779 */ 780 #define CONFIG_ROOTPATH "/opt/nfsroot" 781 #define CONFIG_BOOTFILE "uImage" 782 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 783 784 /* default location for tftp and bootm */ 785 #define CONFIG_LOADADDR 1000000 786 787 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 788 789 #define CONFIG_BAUDRATE 115200 790 791 #define __USB_PHY_TYPE utmi 792 793 #ifdef CONFIG_T1040RDB 794 #define FDTFILE "t1040rdb/t1040rdb.dtb" 795 #define RAMDISKFILE "t1040rdb/ramdisk.uboot" 796 #elif CONFIG_T1042RDB_PI 797 #define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb" 798 #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" 799 #endif 800 801 #ifdef CONFIG_FSL_DIU_FB 802 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 803 #else 804 #define DIU_ENVIRONMENT 805 #endif 806 807 #define CONFIG_EXTRA_ENV_SETTINGS \ 808 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 809 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 810 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 811 "netdev=eth0\0" \ 812 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 813 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 814 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 815 "tftpflash=tftpboot $loadaddr $uboot && " \ 816 "protect off $ubootaddr +$filesize && " \ 817 "erase $ubootaddr +$filesize && " \ 818 "cp.b $loadaddr $ubootaddr $filesize && " \ 819 "protect on $ubootaddr +$filesize && " \ 820 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 821 "consoledev=ttyS0\0" \ 822 "ramdiskaddr=2000000\0" \ 823 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 824 "fdtaddr=c00000\0" \ 825 "fdtfile=" __stringify(FDTFILE) "\0" \ 826 "bdev=sda3\0" 827 828 #define CONFIG_LINUX \ 829 "setenv bootargs root=/dev/ram rw " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "setenv ramdiskaddr 0x02000000;" \ 832 "setenv fdtaddr 0x00c00000;" \ 833 "setenv loadaddr 0x1000000;" \ 834 "bootm $loadaddr $ramdiskaddr $fdtaddr" 835 836 #define CONFIG_HDBOOT \ 837 "setenv bootargs root=/dev/$bdev rw " \ 838 "console=$consoledev,$baudrate $othbootargs;" \ 839 "tftp $loadaddr $bootfile;" \ 840 "tftp $fdtaddr $fdtfile;" \ 841 "bootm $loadaddr - $fdtaddr" 842 843 #define CONFIG_NFSBOOTCOMMAND \ 844 "setenv bootargs root=/dev/nfs rw " \ 845 "nfsroot=$serverip:$rootpath " \ 846 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "tftp $loadaddr $bootfile;" \ 849 "tftp $fdtaddr $fdtfile;" \ 850 "bootm $loadaddr - $fdtaddr" 851 852 #define CONFIG_RAMBOOTCOMMAND \ 853 "setenv bootargs root=/dev/ram rw " \ 854 "console=$consoledev,$baudrate $othbootargs;" \ 855 "tftp $ramdiskaddr $ramdiskfile;" \ 856 "tftp $loadaddr $bootfile;" \ 857 "tftp $fdtaddr $fdtfile;" \ 858 "bootm $loadaddr $ramdiskaddr $fdtaddr" 859 860 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 861 862 #ifdef CONFIG_SECURE_BOOT 863 #include <asm/fsl_secure_boot.h> 864 #endif 865 866 #endif /* __CONFIG_H */ 867