1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 20 #ifdef CONFIG_RAMBOOT_PBL 21 22 #ifndef CONFIG_SECURE_BOOT 23 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 24 #else 25 #define CONFIG_SYS_FSL_PBL_PBI \ 26 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 27 #endif 28 29 #ifdef CONFIG_T1040RDB 30 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 31 #endif 32 #ifdef CONFIG_T1042RDB_PI 33 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 34 #endif 35 #ifdef CONFIG_T1042RDB 36 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 37 #endif 38 #ifdef CONFIG_T1040D4RDB 39 #define CONFIG_SYS_FSL_PBL_RCW \ 40 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 41 #endif 42 #ifdef CONFIG_T1042D4RDB 43 #define CONFIG_SYS_FSL_PBL_RCW \ 44 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 45 #endif 46 47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 48 #define CONFIG_SPL_ENV_SUPPORT 49 #define CONFIG_SPL_SERIAL_SUPPORT 50 #define CONFIG_SPL_FLUSH_IMAGE 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 #define CONFIG_SPL_LIBGENERIC_SUPPORT 53 #define CONFIG_SPL_LIBCOMMON_SUPPORT 54 #define CONFIG_SPL_I2C_SUPPORT 55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 56 #define CONFIG_FSL_LAW /* Use common FSL init code */ 57 #define CONFIG_SYS_TEXT_BASE 0x30001000 58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 59 #define CONFIG_SPL_PAD_TO 0x40000 60 #define CONFIG_SPL_MAX_SIZE 0x28000 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 #define RESET_VECTOR_OFFSET 0x27FFC 68 #define BOOT_PAGE_OFFSET 0x27000 69 70 #ifdef CONFIG_NAND 71 #define CONFIG_SPL_NAND_SUPPORT 72 #ifdef CONFIG_SECURE_BOOT 73 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 74 /* 75 * HDR would be appended at end of image and copied to DDR along 76 * with U-Boot image. 77 */ 78 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 79 CONFIG_U_BOOT_HDR_SIZE) 80 #else 81 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 82 #endif 83 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 84 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 85 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 86 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 87 #define CONFIG_SPL_NAND_BOOT 88 #endif 89 90 #ifdef CONFIG_SPIFLASH 91 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 92 #define CONFIG_SPL_SPI_SUPPORT 93 #define CONFIG_SPL_SPI_FLASH_SUPPORT 94 #define CONFIG_SPL_SPI_FLASH_MINIMAL 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 99 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 100 #ifndef CONFIG_SPL_BUILD 101 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 102 #endif 103 #define CONFIG_SPL_SPI_BOOT 104 #endif 105 106 #ifdef CONFIG_SDCARD 107 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 108 #define CONFIG_SPL_MMC_SUPPORT 109 #define CONFIG_SPL_MMC_MINIMAL 110 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 111 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 112 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 113 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 114 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 115 #ifndef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 117 #endif 118 #define CONFIG_SPL_MMC_BOOT 119 #endif 120 121 #endif 122 123 /* High Level Configuration Options */ 124 #define CONFIG_BOOKE 125 #define CONFIG_E500MC /* BOOKE e500mc family */ 126 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 127 #define CONFIG_MP /* support multiple processors */ 128 129 /* support deep sleep */ 130 #define CONFIG_DEEP_SLEEP 131 #if defined(CONFIG_DEEP_SLEEP) 132 #define CONFIG_BOARD_EARLY_INIT_F 133 #define CONFIG_SILENT_CONSOLE 134 #endif 135 136 #ifndef CONFIG_SYS_TEXT_BASE 137 #define CONFIG_SYS_TEXT_BASE 0xeff40000 138 #endif 139 140 #ifndef CONFIG_RESET_VECTOR_ADDRESS 141 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 142 #endif 143 144 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 145 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 146 #define CONFIG_FSL_IFC /* Enable IFC Support */ 147 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 148 #define CONFIG_PCI /* Enable PCI/PCIE */ 149 #define CONFIG_PCI_INDIRECT_BRIDGE 150 #define CONFIG_PCIE1 /* PCIE controller 1 */ 151 #define CONFIG_PCIE2 /* PCIE controller 2 */ 152 #define CONFIG_PCIE3 /* PCIE controller 3 */ 153 #define CONFIG_PCIE4 /* PCIE controller 4 */ 154 155 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 156 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 157 158 #define CONFIG_FSL_LAW /* Use common FSL init code */ 159 160 #define CONFIG_ENV_OVERWRITE 161 162 #ifndef CONFIG_SYS_NO_FLASH 163 #define CONFIG_FLASH_CFI_DRIVER 164 #define CONFIG_SYS_FLASH_CFI 165 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 166 #endif 167 168 #if defined(CONFIG_SPIFLASH) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_ENV_IS_IN_SPI_FLASH 171 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 172 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 173 #define CONFIG_ENV_SECT_SIZE 0x10000 174 #elif defined(CONFIG_SDCARD) 175 #define CONFIG_SYS_EXTRA_ENV_RELOC 176 #define CONFIG_ENV_IS_IN_MMC 177 #define CONFIG_SYS_MMC_ENV_DEV 0 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_OFFSET (512 * 0x800) 180 #elif defined(CONFIG_NAND) 181 #ifdef CONFIG_SECURE_BOOT 182 #define CONFIG_RAMBOOT_NAND 183 #define CONFIG_BOOTSCRIPT_COPY_RAM 184 #endif 185 #define CONFIG_SYS_EXTRA_ENV_RELOC 186 #define CONFIG_ENV_IS_IN_NAND 187 #define CONFIG_ENV_SIZE 0x2000 188 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 189 #else 190 #define CONFIG_ENV_IS_IN_FLASH 191 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 192 #define CONFIG_ENV_SIZE 0x2000 193 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 194 #endif 195 196 #define CONFIG_SYS_CLK_FREQ 100000000 197 #define CONFIG_DDR_CLK_FREQ 66666666 198 199 /* 200 * These can be toggled for performance analysis, otherwise use default. 201 */ 202 #define CONFIG_SYS_CACHE_STASHING 203 #define CONFIG_BACKSIDE_L2_CACHE 204 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 205 #define CONFIG_BTB /* toggle branch predition */ 206 #define CONFIG_DDR_ECC 207 #ifdef CONFIG_DDR_ECC 208 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 209 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 210 #endif 211 212 #define CONFIG_ENABLE_36BIT_PHYS 213 214 #define CONFIG_ADDR_MAP 215 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 216 217 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 218 #define CONFIG_SYS_MEMTEST_END 0x00400000 219 #define CONFIG_SYS_ALT_MEMTEST 220 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 221 222 /* 223 * Config the L3 Cache as L3 SRAM 224 */ 225 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 226 /* 227 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 228 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 229 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 230 */ 231 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 232 #define CONFIG_SYS_L3_SIZE 256 << 10 233 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 234 #ifdef CONFIG_RAMBOOT_PBL 235 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 236 #endif 237 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 238 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 239 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 240 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 241 242 #define CONFIG_SYS_DCSRBAR 0xf0000000 243 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 244 245 /* 246 * DDR Setup 247 */ 248 #define CONFIG_VERY_BIG_RAM 249 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 250 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 251 252 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 253 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 254 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 255 256 #define CONFIG_DDR_SPD 257 #ifndef CONFIG_SYS_FSL_DDR4 258 #define CONFIG_SYS_FSL_DDR3 259 #endif 260 261 #define CONFIG_SYS_SPD_BUS_NUM 0 262 #define SPD_EEPROM_ADDRESS 0x51 263 264 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 265 266 /* 267 * IFC Definitions 268 */ 269 #define CONFIG_SYS_FLASH_BASE 0xe8000000 270 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 271 272 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 273 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 274 CSPR_PORT_SIZE_16 | \ 275 CSPR_MSEL_NOR | \ 276 CSPR_V) 277 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 278 279 /* 280 * TDM Definition 281 */ 282 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 283 284 /* NOR Flash Timing Params */ 285 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 286 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 287 FTIM0_NOR_TEADC(0x5) | \ 288 FTIM0_NOR_TEAHC(0x5)) 289 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 290 FTIM1_NOR_TRAD_NOR(0x1A) |\ 291 FTIM1_NOR_TSEQRAD_NOR(0x13)) 292 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 293 FTIM2_NOR_TCH(0x4) | \ 294 FTIM2_NOR_TWPH(0x0E) | \ 295 FTIM2_NOR_TWP(0x1c)) 296 #define CONFIG_SYS_NOR_FTIM3 0x0 297 298 #define CONFIG_SYS_FLASH_QUIET_TEST 299 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 300 301 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 302 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 303 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 304 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 305 306 #define CONFIG_SYS_FLASH_EMPTY_INFO 307 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 308 309 /* CPLD on IFC */ 310 #define CPLD_LBMAP_MASK 0x3F 311 #define CPLD_BANK_SEL_MASK 0x07 312 #define CPLD_BANK_OVERRIDE 0x40 313 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 314 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 315 #define CPLD_LBMAP_RESET 0xFF 316 #define CPLD_LBMAP_SHIFT 0x03 317 318 #if defined(CONFIG_T1042RDB_PI) 319 #define CPLD_DIU_SEL_DFP 0x80 320 #elif defined(CONFIG_T1042D4RDB) 321 #define CPLD_DIU_SEL_DFP 0xc0 322 #endif 323 324 #if defined(CONFIG_T1040D4RDB) 325 #define CPLD_INT_MASK_ALL 0xFF 326 #define CPLD_INT_MASK_THERM 0x80 327 #define CPLD_INT_MASK_DVI_DFP 0x40 328 #define CPLD_INT_MASK_QSGMII1 0x20 329 #define CPLD_INT_MASK_QSGMII2 0x10 330 #define CPLD_INT_MASK_SGMI1 0x08 331 #define CPLD_INT_MASK_SGMI2 0x04 332 #define CPLD_INT_MASK_TDMR1 0x02 333 #define CPLD_INT_MASK_TDMR2 0x01 334 #endif 335 336 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 337 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 338 #define CONFIG_SYS_CSPR2_EXT (0xf) 339 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 340 | CSPR_PORT_SIZE_8 \ 341 | CSPR_MSEL_GPCM \ 342 | CSPR_V) 343 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 344 #define CONFIG_SYS_CSOR2 0x0 345 /* CPLD Timing parameters for IFC CS2 */ 346 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 347 FTIM0_GPCM_TEADC(0x0e) | \ 348 FTIM0_GPCM_TEAHC(0x0e)) 349 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 350 FTIM1_GPCM_TRAD(0x1f)) 351 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 352 FTIM2_GPCM_TCH(0x8) | \ 353 FTIM2_GPCM_TWP(0x1f)) 354 #define CONFIG_SYS_CS2_FTIM3 0x0 355 356 /* NAND Flash on IFC */ 357 #define CONFIG_NAND_FSL_IFC 358 #define CONFIG_SYS_NAND_BASE 0xff800000 359 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 360 361 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 362 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 363 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 364 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 365 | CSPR_V) 366 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 367 368 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 369 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 370 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 371 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 372 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 373 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 374 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 375 376 #define CONFIG_SYS_NAND_ONFI_DETECTION 377 378 /* ONFI NAND Flash mode0 Timing Params */ 379 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 380 FTIM0_NAND_TWP(0x18) | \ 381 FTIM0_NAND_TWCHT(0x07) | \ 382 FTIM0_NAND_TWH(0x0a)) 383 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 384 FTIM1_NAND_TWBE(0x39) | \ 385 FTIM1_NAND_TRR(0x0e) | \ 386 FTIM1_NAND_TRP(0x18)) 387 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 388 FTIM2_NAND_TREH(0x0a) | \ 389 FTIM2_NAND_TWHRE(0x1e)) 390 #define CONFIG_SYS_NAND_FTIM3 0x0 391 392 #define CONFIG_SYS_NAND_DDR_LAW 11 393 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 394 #define CONFIG_SYS_MAX_NAND_DEVICE 1 395 #define CONFIG_CMD_NAND 396 397 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 398 399 #if defined(CONFIG_NAND) 400 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 401 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 402 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 403 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 404 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 405 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 406 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 407 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 408 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 409 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 410 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 411 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 412 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 413 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 414 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 415 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 416 #else 417 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 418 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 419 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 420 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 421 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 422 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 423 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 424 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 425 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 426 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 427 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 428 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 429 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 430 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 431 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 432 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 433 #endif 434 435 #ifdef CONFIG_SPL_BUILD 436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 437 #else 438 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 439 #endif 440 441 #if defined(CONFIG_RAMBOOT_PBL) 442 #define CONFIG_SYS_RAMBOOT 443 #endif 444 445 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 446 #if defined(CONFIG_NAND) 447 #define CONFIG_A008044_WORKAROUND 448 #endif 449 #endif 450 451 #define CONFIG_BOARD_EARLY_INIT_R 452 #define CONFIG_MISC_INIT_R 453 454 #define CONFIG_HWCONFIG 455 456 /* define to use L1 as initial stack */ 457 #define CONFIG_L1_INIT_RAM 458 #define CONFIG_SYS_INIT_RAM_LOCK 459 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 462 /* The assembler doesn't like typecast */ 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 464 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 465 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 466 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 467 468 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 469 GENERATED_GBL_DATA_SIZE) 470 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 471 472 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 473 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 474 475 /* Serial Port - controlled on board with jumper J8 476 * open - index 2 477 * shorted - index 1 478 */ 479 #define CONFIG_CONS_INDEX 1 480 #define CONFIG_SYS_NS16550_SERIAL 481 #define CONFIG_SYS_NS16550_REG_SIZE 1 482 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 483 484 #define CONFIG_SYS_BAUDRATE_TABLE \ 485 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 486 487 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 488 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 489 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 490 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 491 #ifndef CONFIG_SPL_BUILD 492 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 493 #endif 494 495 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 496 /* Video */ 497 #define CONFIG_FSL_DIU_FB 498 499 #ifdef CONFIG_FSL_DIU_FB 500 #define CONFIG_FSL_DIU_CH7301 501 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 502 #define CONFIG_VIDEO 503 #define CONFIG_CMD_BMP 504 #define CONFIG_CFB_CONSOLE 505 #define CONFIG_CFB_CONSOLE_ANSI 506 #define CONFIG_VIDEO_SW_CURSOR 507 #define CONFIG_VGA_AS_SINGLE_DEVICE 508 #define CONFIG_VIDEO_LOGO 509 #define CONFIG_VIDEO_BMP_LOGO 510 #endif 511 #endif 512 513 /* I2C */ 514 #define CONFIG_SYS_I2C 515 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 516 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 517 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 518 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 519 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 520 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 521 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 523 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 524 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 525 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 526 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 527 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 528 529 /* I2C bus multiplexer */ 530 #define I2C_MUX_PCA_ADDR 0x70 531 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 532 #define I2C_MUX_CH_DEFAULT 0x8 533 #endif 534 535 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 536 /* LDI/DVI Encoder for display */ 537 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 538 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 539 540 /* 541 * RTC configuration 542 */ 543 #define RTC 544 #define CONFIG_RTC_DS1337 1 545 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 546 547 /*DVI encoder*/ 548 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 549 #endif 550 551 /* 552 * eSPI - Enhanced SPI 553 */ 554 #define CONFIG_SPI_FLASH_BAR 555 #define CONFIG_SF_DEFAULT_SPEED 10000000 556 #define CONFIG_SF_DEFAULT_MODE 0 557 #define CONFIG_ENV_SPI_BUS 0 558 #define CONFIG_ENV_SPI_CS 0 559 #define CONFIG_ENV_SPI_MAX_HZ 10000000 560 #define CONFIG_ENV_SPI_MODE 0 561 562 /* 563 * General PCI 564 * Memory space is mapped 1-1, but I/O space must start from 0. 565 */ 566 567 #ifdef CONFIG_PCI 568 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 569 #ifdef CONFIG_PCIE1 570 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 571 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 572 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 573 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 574 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 575 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 576 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 577 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 578 #endif 579 580 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 581 #ifdef CONFIG_PCIE2 582 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 583 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 584 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 585 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 587 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 588 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 589 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 590 #endif 591 592 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 593 #ifdef CONFIG_PCIE3 594 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 595 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 596 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 597 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 598 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 599 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 600 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 601 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 602 #endif 603 604 /* controller 4, Base address 203000 */ 605 #ifdef CONFIG_PCIE4 606 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 607 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 608 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 609 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 610 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 611 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 612 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 613 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 614 #endif 615 616 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 617 618 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 619 #define CONFIG_DOS_PARTITION 620 #endif /* CONFIG_PCI */ 621 622 /* SATA */ 623 #define CONFIG_FSL_SATA_V2 624 #ifdef CONFIG_FSL_SATA_V2 625 #define CONFIG_LIBATA 626 #define CONFIG_FSL_SATA 627 628 #define CONFIG_SYS_SATA_MAX_DEVICE 1 629 #define CONFIG_SATA1 630 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 631 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 632 633 #define CONFIG_LBA48 634 #define CONFIG_CMD_SATA 635 #define CONFIG_DOS_PARTITION 636 #endif 637 638 /* 639 * USB 640 */ 641 #define CONFIG_HAS_FSL_DR_USB 642 643 #ifdef CONFIG_HAS_FSL_DR_USB 644 #define CONFIG_USB_EHCI 645 646 #ifdef CONFIG_USB_EHCI 647 #define CONFIG_USB_STORAGE 648 #define CONFIG_USB_EHCI_FSL 649 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 650 #endif 651 #endif 652 653 #define CONFIG_MMC 654 655 #ifdef CONFIG_MMC 656 #define CONFIG_FSL_ESDHC 657 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 658 #define CONFIG_GENERIC_MMC 659 #define CONFIG_DOS_PARTITION 660 #endif 661 662 /* Qman/Bman */ 663 #ifndef CONFIG_NOBQFMAN 664 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 665 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 666 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 667 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 668 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 669 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 670 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 671 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 672 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 674 CONFIG_SYS_BMAN_CENA_SIZE) 675 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 676 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 677 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 678 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 679 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 680 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 681 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 682 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 683 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 684 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 685 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 686 CONFIG_SYS_QMAN_CENA_SIZE) 687 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 688 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 689 690 #define CONFIG_SYS_DPAA_FMAN 691 #define CONFIG_SYS_DPAA_PME 692 693 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 694 #define CONFIG_QE 695 #define CONFIG_U_QE 696 #endif 697 698 /* Default address of microcode for the Linux Fman driver */ 699 #if defined(CONFIG_SPIFLASH) 700 /* 701 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 702 * env, so we got 0x110000. 703 */ 704 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 705 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 706 #elif defined(CONFIG_SDCARD) 707 /* 708 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 709 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 710 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 711 */ 712 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 713 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 714 #elif defined(CONFIG_NAND) 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 716 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 717 #else 718 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 719 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 720 #endif 721 722 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 723 #if defined(CONFIG_SPIFLASH) 724 #define CONFIG_SYS_QE_FW_ADDR 0x130000 725 #elif defined(CONFIG_SDCARD) 726 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 727 #elif defined(CONFIG_NAND) 728 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 729 #else 730 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 731 #endif 732 #endif 733 734 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 735 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 736 #endif /* CONFIG_NOBQFMAN */ 737 738 #ifdef CONFIG_SYS_DPAA_FMAN 739 #define CONFIG_FMAN_ENET 740 #define CONFIG_PHY_VITESSE 741 #define CONFIG_PHY_REALTEK 742 #endif 743 744 #ifdef CONFIG_FMAN_ENET 745 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 746 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 747 #elif defined(CONFIG_T1040D4RDB) 748 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 749 #elif defined(CONFIG_T1042D4RDB) 750 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 751 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 752 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 753 #endif 754 755 #ifdef CONFIG_T104XD4RDB 756 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 757 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 758 #else 759 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 760 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 761 #endif 762 763 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 764 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 765 #define CONFIG_VSC9953 766 #define CONFIG_CMD_ETHSW 767 #ifdef CONFIG_T1040RDB 768 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 769 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 770 #else 771 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 772 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 773 #endif 774 #endif 775 776 #define CONFIG_MII /* MII PHY management */ 777 #define CONFIG_ETHPRIME "FM1@DTSEC4" 778 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 779 #endif 780 781 /* 782 * Environment 783 */ 784 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 785 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 786 787 /* 788 * Command line configuration. 789 */ 790 #ifdef CONFIG_T1042RDB_PI 791 #define CONFIG_CMD_DATE 792 #endif 793 #define CONFIG_CMD_ERRATA 794 #define CONFIG_CMD_IRQ 795 #define CONFIG_CMD_REGINFO 796 797 #ifdef CONFIG_PCI 798 #define CONFIG_CMD_PCI 799 #endif 800 801 /* Hash command with SHA acceleration supported in hardware */ 802 #ifdef CONFIG_FSL_CAAM 803 #define CONFIG_CMD_HASH 804 #define CONFIG_SHA_HW_ACCEL 805 #endif 806 807 /* 808 * Miscellaneous configurable options 809 */ 810 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 811 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 812 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 813 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 814 #ifdef CONFIG_CMD_KGDB 815 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 816 #else 817 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 818 #endif 819 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 820 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 821 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 822 823 /* 824 * For booting Linux, the board info and command line data 825 * have to be in the first 64 MB of memory, since this is 826 * the maximum mapped by the Linux kernel during initialization. 827 */ 828 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 829 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 830 831 #ifdef CONFIG_CMD_KGDB 832 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 833 #endif 834 835 /* 836 * Dynamic MTD Partition support with mtdparts 837 */ 838 #ifndef CONFIG_SYS_NO_FLASH 839 #define CONFIG_MTD_DEVICE 840 #define CONFIG_MTD_PARTITIONS 841 #define CONFIG_CMD_MTDPARTS 842 #define CONFIG_FLASH_CFI_MTD 843 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 844 "spi0=spife110000.0" 845 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 846 "128k(dtb),96m(fs),-(user);"\ 847 "fff800000.flash:2m(uboot),9m(kernel),"\ 848 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 849 "2m(uboot),9m(kernel),128k(dtb),-(user)" 850 #endif 851 852 /* 853 * Environment Configuration 854 */ 855 #define CONFIG_ROOTPATH "/opt/nfsroot" 856 #define CONFIG_BOOTFILE "uImage" 857 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 858 859 /* default location for tftp and bootm */ 860 #define CONFIG_LOADADDR 1000000 861 862 863 #define CONFIG_BAUDRATE 115200 864 865 #define __USB_PHY_TYPE utmi 866 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 867 868 #ifdef CONFIG_T1040RDB 869 #define FDTFILE "t1040rdb/t1040rdb.dtb" 870 #elif defined(CONFIG_T1042RDB_PI) 871 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 872 #elif defined(CONFIG_T1042RDB) 873 #define FDTFILE "t1042rdb/t1042rdb.dtb" 874 #elif defined(CONFIG_T1040D4RDB) 875 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 876 #elif defined(CONFIG_T1042D4RDB) 877 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 878 #endif 879 880 #ifdef CONFIG_FSL_DIU_FB 881 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 882 #else 883 #define DIU_ENVIRONMENT 884 #endif 885 886 #define CONFIG_EXTRA_ENV_SETTINGS \ 887 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 888 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 889 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 890 "netdev=eth0\0" \ 891 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 892 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 893 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 894 "tftpflash=tftpboot $loadaddr $uboot && " \ 895 "protect off $ubootaddr +$filesize && " \ 896 "erase $ubootaddr +$filesize && " \ 897 "cp.b $loadaddr $ubootaddr $filesize && " \ 898 "protect on $ubootaddr +$filesize && " \ 899 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 900 "consoledev=ttyS0\0" \ 901 "ramdiskaddr=2000000\0" \ 902 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 903 "fdtaddr=1e00000\0" \ 904 "fdtfile=" __stringify(FDTFILE) "\0" \ 905 "bdev=sda3\0" 906 907 #define CONFIG_LINUX \ 908 "setenv bootargs root=/dev/ram rw " \ 909 "console=$consoledev,$baudrate $othbootargs;" \ 910 "setenv ramdiskaddr 0x02000000;" \ 911 "setenv fdtaddr 0x00c00000;" \ 912 "setenv loadaddr 0x1000000;" \ 913 "bootm $loadaddr $ramdiskaddr $fdtaddr" 914 915 #define CONFIG_HDBOOT \ 916 "setenv bootargs root=/dev/$bdev rw " \ 917 "console=$consoledev,$baudrate $othbootargs;" \ 918 "tftp $loadaddr $bootfile;" \ 919 "tftp $fdtaddr $fdtfile;" \ 920 "bootm $loadaddr - $fdtaddr" 921 922 #define CONFIG_NFSBOOTCOMMAND \ 923 "setenv bootargs root=/dev/nfs rw " \ 924 "nfsroot=$serverip:$rootpath " \ 925 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 926 "console=$consoledev,$baudrate $othbootargs;" \ 927 "tftp $loadaddr $bootfile;" \ 928 "tftp $fdtaddr $fdtfile;" \ 929 "bootm $loadaddr - $fdtaddr" 930 931 #define CONFIG_RAMBOOTCOMMAND \ 932 "setenv bootargs root=/dev/ram rw " \ 933 "console=$consoledev,$baudrate $othbootargs;" \ 934 "tftp $ramdiskaddr $ramdiskfile;" \ 935 "tftp $loadaddr $bootfile;" \ 936 "tftp $fdtaddr $fdtfile;" \ 937 "bootm $loadaddr $ramdiskaddr $fdtaddr" 938 939 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 940 941 #include <asm/fsl_secure_boot.h> 942 943 #endif /* __CONFIG_H */ 944