1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #ifdef CONFIG_T1040RDB 19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 20 #endif 21 #ifdef CONFIG_T1042RDB_PI 22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 23 #endif 24 #ifdef CONFIG_T1042RDB 25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 26 #endif 27 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_ENV_SUPPORT 30 #define CONFIG_SPL_SERIAL_SUPPORT 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 33 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 35 #define CONFIG_SPL_I2C_SUPPORT 36 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 37 #define CONFIG_FSL_LAW /* Use common FSL init code */ 38 #define CONFIG_SYS_TEXT_BASE 0x30001000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_SKIP_RELOCATE 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 46 #define CONFIG_SYS_NO_FLASH 47 #endif 48 #define RESET_VECTOR_OFFSET 0x27FFC 49 #define BOOT_PAGE_OFFSET 0x27000 50 51 #ifdef CONFIG_NAND 52 #define CONFIG_SPL_NAND_SUPPORT 53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 54 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 55 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 56 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 58 #define CONFIG_SPL_NAND_BOOT 59 #endif 60 61 #ifdef CONFIG_SPIFLASH 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 63 #define CONFIG_SPL_SPI_SUPPORT 64 #define CONFIG_SPL_SPI_FLASH_SUPPORT 65 #define CONFIG_SPL_SPI_FLASH_MINIMAL 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #ifndef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 73 #endif 74 #define CONFIG_SPL_SPI_BOOT 75 #endif 76 77 #ifdef CONFIG_SDCARD 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_MMC_SUPPORT 80 #define CONFIG_SPL_MMC_MINIMAL 81 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #define CONFIG_SPL_MMC_BOOT 90 #endif 91 92 #endif 93 94 /* High Level Configuration Options */ 95 #define CONFIG_BOOKE 96 #define CONFIG_E500 /* BOOKE e500 family */ 97 #define CONFIG_E500MC /* BOOKE e500mc family */ 98 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 99 #define CONFIG_MP /* support multiple processors */ 100 101 /* support deep sleep */ 102 #define CONFIG_DEEP_SLEEP 103 #define CONFIG_SILENT_CONSOLE 104 105 #ifndef CONFIG_SYS_TEXT_BASE 106 #define CONFIG_SYS_TEXT_BASE 0xeff40000 107 #endif 108 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 111 #endif 112 113 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 114 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 115 #define CONFIG_FSL_IFC /* Enable IFC Support */ 116 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 117 #define CONFIG_PCI /* Enable PCI/PCIE */ 118 #define CONFIG_PCI_INDIRECT_BRIDGE 119 #define CONFIG_PCIE1 /* PCIE controler 1 */ 120 #define CONFIG_PCIE2 /* PCIE controler 2 */ 121 #define CONFIG_PCIE3 /* PCIE controler 3 */ 122 #define CONFIG_PCIE4 /* PCIE controler 4 */ 123 124 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 125 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 126 127 #define CONFIG_FSL_LAW /* Use common FSL init code */ 128 129 #define CONFIG_ENV_OVERWRITE 130 131 #ifndef CONFIG_SYS_NO_FLASH 132 #define CONFIG_FLASH_CFI_DRIVER 133 #define CONFIG_SYS_FLASH_CFI 134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 135 #endif 136 137 #if defined(CONFIG_SPIFLASH) 138 #define CONFIG_SYS_EXTRA_ENV_RELOC 139 #define CONFIG_ENV_IS_IN_SPI_FLASH 140 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 141 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 142 #define CONFIG_ENV_SECT_SIZE 0x10000 143 #elif defined(CONFIG_SDCARD) 144 #define CONFIG_SYS_EXTRA_ENV_RELOC 145 #define CONFIG_ENV_IS_IN_MMC 146 #define CONFIG_SYS_MMC_ENV_DEV 0 147 #define CONFIG_ENV_SIZE 0x2000 148 #define CONFIG_ENV_OFFSET (512 * 0x800) 149 #elif defined(CONFIG_NAND) 150 #define CONFIG_SYS_EXTRA_ENV_RELOC 151 #define CONFIG_ENV_IS_IN_NAND 152 #define CONFIG_ENV_SIZE 0x2000 153 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 154 #else 155 #define CONFIG_ENV_IS_IN_FLASH 156 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 157 #define CONFIG_ENV_SIZE 0x2000 158 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 159 #endif 160 161 #define CONFIG_SYS_CLK_FREQ 100000000 162 #define CONFIG_DDR_CLK_FREQ 66666666 163 164 /* 165 * These can be toggled for performance analysis, otherwise use default. 166 */ 167 #define CONFIG_SYS_CACHE_STASHING 168 #define CONFIG_BACKSIDE_L2_CACHE 169 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 170 #define CONFIG_BTB /* toggle branch predition */ 171 #define CONFIG_DDR_ECC 172 #ifdef CONFIG_DDR_ECC 173 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 174 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 175 #endif 176 177 #define CONFIG_ENABLE_36BIT_PHYS 178 179 #define CONFIG_ADDR_MAP 180 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 181 182 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 183 #define CONFIG_SYS_MEMTEST_END 0x00400000 184 #define CONFIG_SYS_ALT_MEMTEST 185 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 186 187 /* 188 * Config the L3 Cache as L3 SRAM 189 */ 190 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 191 #define CONFIG_SYS_L3_SIZE 256 << 10 192 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 193 #ifdef CONFIG_RAMBOOT_PBL 194 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 195 #endif 196 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 197 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 198 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 199 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 200 201 #define CONFIG_SYS_DCSRBAR 0xf0000000 202 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 203 204 /* 205 * DDR Setup 206 */ 207 #define CONFIG_VERY_BIG_RAM 208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 210 211 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 213 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 214 215 #define CONFIG_DDR_SPD 216 #define CONFIG_SYS_DDR_RAW_TIMING 217 #define CONFIG_SYS_FSL_DDR3 218 219 #define CONFIG_SYS_SPD_BUS_NUM 0 220 #define SPD_EEPROM_ADDRESS 0x51 221 222 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 223 224 /* 225 * IFC Definitions 226 */ 227 #define CONFIG_SYS_FLASH_BASE 0xe8000000 228 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 229 230 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 231 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 232 CSPR_PORT_SIZE_16 | \ 233 CSPR_MSEL_NOR | \ 234 CSPR_V) 235 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 236 237 /* 238 * TDM Definition 239 */ 240 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 241 242 /* NOR Flash Timing Params */ 243 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 244 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 245 FTIM0_NOR_TEADC(0x5) | \ 246 FTIM0_NOR_TEAHC(0x5)) 247 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 248 FTIM1_NOR_TRAD_NOR(0x1A) |\ 249 FTIM1_NOR_TSEQRAD_NOR(0x13)) 250 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 251 FTIM2_NOR_TCH(0x4) | \ 252 FTIM2_NOR_TWPH(0x0E) | \ 253 FTIM2_NOR_TWP(0x1c)) 254 #define CONFIG_SYS_NOR_FTIM3 0x0 255 256 #define CONFIG_SYS_FLASH_QUIET_TEST 257 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 263 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 266 267 /* CPLD on IFC */ 268 #define CPLD_LBMAP_MASK 0x3F 269 #define CPLD_BANK_SEL_MASK 0x07 270 #define CPLD_BANK_OVERRIDE 0x40 271 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 272 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 273 #define CPLD_LBMAP_RESET 0xFF 274 #define CPLD_LBMAP_SHIFT 0x03 275 #ifdef CONFIG_T1042RDB_PI 276 #define CPLD_DIU_SEL_DFP 0x80 277 #endif 278 279 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 280 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 281 #define CONFIG_SYS_CSPR2_EXT (0xf) 282 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 283 | CSPR_PORT_SIZE_8 \ 284 | CSPR_MSEL_GPCM \ 285 | CSPR_V) 286 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 287 #define CONFIG_SYS_CSOR2 0x0 288 /* CPLD Timing parameters for IFC CS2 */ 289 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 290 FTIM0_GPCM_TEADC(0x0e) | \ 291 FTIM0_GPCM_TEAHC(0x0e)) 292 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 293 FTIM1_GPCM_TRAD(0x1f)) 294 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 295 FTIM2_GPCM_TCH(0x8) | \ 296 FTIM2_GPCM_TWP(0x1f)) 297 #define CONFIG_SYS_CS2_FTIM3 0x0 298 299 /* NAND Flash on IFC */ 300 #define CONFIG_NAND_FSL_IFC 301 #define CONFIG_SYS_NAND_BASE 0xff800000 302 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 303 304 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 305 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 306 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 307 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 308 | CSPR_V) 309 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 310 311 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 312 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 313 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 314 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 315 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 316 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 317 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 318 319 #define CONFIG_SYS_NAND_ONFI_DETECTION 320 321 /* ONFI NAND Flash mode0 Timing Params */ 322 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 323 FTIM0_NAND_TWP(0x18) | \ 324 FTIM0_NAND_TWCHT(0x07) | \ 325 FTIM0_NAND_TWH(0x0a)) 326 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 327 FTIM1_NAND_TWBE(0x39) | \ 328 FTIM1_NAND_TRR(0x0e) | \ 329 FTIM1_NAND_TRP(0x18)) 330 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 331 FTIM2_NAND_TREH(0x0a) | \ 332 FTIM2_NAND_TWHRE(0x1e)) 333 #define CONFIG_SYS_NAND_FTIM3 0x0 334 335 #define CONFIG_SYS_NAND_DDR_LAW 11 336 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 337 #define CONFIG_SYS_MAX_NAND_DEVICE 1 338 #define CONFIG_MTD_NAND_VERIFY_WRITE 339 #define CONFIG_CMD_NAND 340 341 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 342 343 #if defined(CONFIG_NAND) 344 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 345 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 346 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 347 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 348 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 349 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 350 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 351 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 352 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 353 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 354 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 355 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 356 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 357 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 358 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 359 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 360 #else 361 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 362 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 363 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 364 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 365 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 366 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 367 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 368 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 369 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 370 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 371 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 372 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 373 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 374 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 375 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 376 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 377 #endif 378 379 #ifdef CONFIG_SPL_BUILD 380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 381 #else 382 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 383 #endif 384 385 #if defined(CONFIG_RAMBOOT_PBL) 386 #define CONFIG_SYS_RAMBOOT 387 #endif 388 389 #define CONFIG_BOARD_EARLY_INIT_R 390 #define CONFIG_MISC_INIT_R 391 392 #define CONFIG_HWCONFIG 393 394 /* define to use L1 as initial stack */ 395 #define CONFIG_L1_INIT_RAM 396 #define CONFIG_SYS_INIT_RAM_LOCK 397 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 400 /* The assembler doesn't like typecast */ 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 402 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 403 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 404 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 405 406 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 407 GENERATED_GBL_DATA_SIZE) 408 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 409 410 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 411 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 412 413 /* Serial Port - controlled on board with jumper J8 414 * open - index 2 415 * shorted - index 1 416 */ 417 #define CONFIG_CONS_INDEX 1 418 #define CONFIG_SYS_NS16550 419 #define CONFIG_SYS_NS16550_SERIAL 420 #define CONFIG_SYS_NS16550_REG_SIZE 1 421 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 422 423 #define CONFIG_SYS_BAUDRATE_TABLE \ 424 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 425 426 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 427 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 428 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 429 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 430 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 431 #ifndef CONFIG_SPL_BUILD 432 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 433 #endif 434 435 /* Use the HUSH parser */ 436 #define CONFIG_SYS_HUSH_PARSER 437 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 438 439 #ifdef CONFIG_T1042RDB_PI 440 /* Video */ 441 #define CONFIG_FSL_DIU_FB 442 443 #ifdef CONFIG_FSL_DIU_FB 444 #define CONFIG_FSL_DIU_CH7301 445 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 446 #define CONFIG_VIDEO 447 #define CONFIG_CMD_BMP 448 #define CONFIG_CFB_CONSOLE 449 #define CONFIG_CFB_CONSOLE_ANSI 450 #define CONFIG_VIDEO_SW_CURSOR 451 #define CONFIG_VGA_AS_SINGLE_DEVICE 452 #define CONFIG_VIDEO_LOGO 453 #define CONFIG_VIDEO_BMP_LOGO 454 #endif 455 #endif 456 457 /* pass open firmware flat tree */ 458 #define CONFIG_OF_LIBFDT 459 #define CONFIG_OF_BOARD_SETUP 460 #define CONFIG_OF_STDOUT_VIA_ALIAS 461 462 /* new uImage format support */ 463 #define CONFIG_FIT 464 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 465 466 /* I2C */ 467 #define CONFIG_SYS_I2C 468 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 469 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 470 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 471 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 472 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 473 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 474 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 475 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 476 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 477 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 478 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 479 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 480 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 481 482 /* I2C bus multiplexer */ 483 #define I2C_MUX_PCA_ADDR 0x70 484 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 485 #define I2C_MUX_CH_DEFAULT 0x8 486 #endif 487 488 #ifdef CONFIG_T1042RDB_PI 489 /* LDI/DVI Encoder for display */ 490 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 491 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 492 493 /* 494 * RTC configuration 495 */ 496 #define RTC 497 #define CONFIG_RTC_DS1337 1 498 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 499 500 /*DVI encoder*/ 501 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 502 #endif 503 504 /* 505 * eSPI - Enhanced SPI 506 */ 507 #define CONFIG_FSL_ESPI 508 #define CONFIG_SPI_FLASH 509 #define CONFIG_SPI_FLASH_STMICRO 510 #define CONFIG_SPI_FLASH_BAR 511 #define CONFIG_CMD_SF 512 #define CONFIG_SF_DEFAULT_SPEED 10000000 513 #define CONFIG_SF_DEFAULT_MODE 0 514 #define CONFIG_ENV_SPI_BUS 0 515 #define CONFIG_ENV_SPI_CS 0 516 #define CONFIG_ENV_SPI_MAX_HZ 10000000 517 #define CONFIG_ENV_SPI_MODE 0 518 519 /* 520 * General PCI 521 * Memory space is mapped 1-1, but I/O space must start from 0. 522 */ 523 524 #ifdef CONFIG_PCI 525 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 526 #ifdef CONFIG_PCIE1 527 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 528 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 529 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 530 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 531 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 532 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 533 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 534 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 535 #endif 536 537 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 538 #ifdef CONFIG_PCIE2 539 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 540 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 542 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 543 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 544 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 545 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 546 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 547 #endif 548 549 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 550 #ifdef CONFIG_PCIE3 551 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 552 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 553 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 554 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 555 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 556 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 557 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 558 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 559 #endif 560 561 /* controller 4, Base address 203000 */ 562 #ifdef CONFIG_PCIE4 563 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 564 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 566 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 568 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 569 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 570 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 571 #endif 572 573 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 574 #define CONFIG_E1000 575 576 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 577 #define CONFIG_DOS_PARTITION 578 #endif /* CONFIG_PCI */ 579 580 /* SATA */ 581 #define CONFIG_FSL_SATA_V2 582 #ifdef CONFIG_FSL_SATA_V2 583 #define CONFIG_LIBATA 584 #define CONFIG_FSL_SATA 585 586 #define CONFIG_SYS_SATA_MAX_DEVICE 1 587 #define CONFIG_SATA1 588 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 589 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 590 591 #define CONFIG_LBA48 592 #define CONFIG_CMD_SATA 593 #define CONFIG_DOS_PARTITION 594 #define CONFIG_CMD_EXT2 595 #endif 596 597 /* 598 * USB 599 */ 600 #define CONFIG_HAS_FSL_DR_USB 601 602 #ifdef CONFIG_HAS_FSL_DR_USB 603 #define CONFIG_USB_EHCI 604 605 #ifdef CONFIG_USB_EHCI 606 #define CONFIG_CMD_USB 607 #define CONFIG_USB_STORAGE 608 #define CONFIG_USB_EHCI_FSL 609 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 610 #define CONFIG_CMD_EXT2 611 #endif 612 #endif 613 614 #define CONFIG_MMC 615 616 #ifdef CONFIG_MMC 617 #define CONFIG_FSL_ESDHC 618 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 619 #define CONFIG_CMD_MMC 620 #define CONFIG_GENERIC_MMC 621 #define CONFIG_CMD_EXT2 622 #define CONFIG_CMD_FAT 623 #define CONFIG_DOS_PARTITION 624 #endif 625 626 /* Qman/Bman */ 627 #ifndef CONFIG_NOBQFMAN 628 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 629 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 630 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 631 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 632 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 633 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 634 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 635 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 636 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 637 638 #define CONFIG_SYS_DPAA_FMAN 639 #define CONFIG_SYS_DPAA_PME 640 641 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 642 #define CONFIG_QE 643 #define CONFIG_U_QE 644 #endif 645 646 /* Default address of microcode for the Linux Fman driver */ 647 #if defined(CONFIG_SPIFLASH) 648 /* 649 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 650 * env, so we got 0x110000. 651 */ 652 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 653 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 654 #elif defined(CONFIG_SDCARD) 655 /* 656 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 657 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 658 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 659 */ 660 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 661 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 662 #elif defined(CONFIG_NAND) 663 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 664 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 665 #else 666 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 667 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 668 #endif 669 670 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 671 #if defined(CONFIG_SPIFLASH) 672 #define CONFIG_SYS_QE_FW_ADDR 0x130000 673 #elif defined(CONFIG_SDCARD) 674 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 675 #elif defined(CONFIG_NAND) 676 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 677 #else 678 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 679 #endif 680 #endif 681 682 683 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 684 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 685 #endif /* CONFIG_NOBQFMAN */ 686 687 #ifdef CONFIG_SYS_DPAA_FMAN 688 #define CONFIG_FMAN_ENET 689 #define CONFIG_PHY_VITESSE 690 #define CONFIG_PHY_REALTEK 691 #endif 692 693 #ifdef CONFIG_FMAN_ENET 694 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 695 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 696 #endif 697 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 698 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 699 700 #define CONFIG_MII /* MII PHY management */ 701 #define CONFIG_ETHPRIME "FM1@DTSEC4" 702 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 703 #endif 704 705 /* 706 * Environment 707 */ 708 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 709 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 710 711 /* 712 * Command line configuration. 713 */ 714 #include <config_cmd_default.h> 715 716 #ifdef CONFIG_T1042RDB_PI 717 #define CONFIG_CMD_DATE 718 #endif 719 #define CONFIG_CMD_DHCP 720 #define CONFIG_CMD_ELF 721 #define CONFIG_CMD_ERRATA 722 #define CONFIG_CMD_GREPENV 723 #define CONFIG_CMD_IRQ 724 #define CONFIG_CMD_I2C 725 #define CONFIG_CMD_MII 726 #define CONFIG_CMD_PING 727 #define CONFIG_CMD_REGINFO 728 #define CONFIG_CMD_SETEXPR 729 730 #ifdef CONFIG_PCI 731 #define CONFIG_CMD_PCI 732 #define CONFIG_CMD_NET 733 #endif 734 735 /* Hash command with SHA acceleration supported in hardware */ 736 #ifdef CONFIG_FSL_CAAM 737 #define CONFIG_CMD_HASH 738 #define CONFIG_SHA_HW_ACCEL 739 #endif 740 741 /* 742 * Miscellaneous configurable options 743 */ 744 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 745 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 746 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 747 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 748 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 749 #ifdef CONFIG_CMD_KGDB 750 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 751 #else 752 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 753 #endif 754 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 755 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 756 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 757 758 /* 759 * For booting Linux, the board info and command line data 760 * have to be in the first 64 MB of memory, since this is 761 * the maximum mapped by the Linux kernel during initialization. 762 */ 763 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 764 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 765 766 #ifdef CONFIG_CMD_KGDB 767 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 768 #endif 769 770 /* 771 * Dynamic MTD Partition support with mtdparts 772 */ 773 #ifndef CONFIG_SYS_NO_FLASH 774 #define CONFIG_MTD_DEVICE 775 #define CONFIG_MTD_PARTITIONS 776 #define CONFIG_CMD_MTDPARTS 777 #define CONFIG_FLASH_CFI_MTD 778 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 779 "spi0=spife110000.0" 780 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 781 "128k(dtb),96m(fs),-(user);"\ 782 "fff800000.flash:2m(uboot),9m(kernel),"\ 783 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 784 "2m(uboot),9m(kernel),128k(dtb),-(user)" 785 #endif 786 787 /* 788 * Environment Configuration 789 */ 790 #define CONFIG_ROOTPATH "/opt/nfsroot" 791 #define CONFIG_BOOTFILE "uImage" 792 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 793 794 /* default location for tftp and bootm */ 795 #define CONFIG_LOADADDR 1000000 796 797 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 798 799 #define CONFIG_BAUDRATE 115200 800 801 #define __USB_PHY_TYPE utmi 802 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 803 804 #ifdef CONFIG_T1040RDB 805 #define FDTFILE "t1040rdb/t1040rdb.dtb" 806 #elif defined(CONFIG_T1042RDB_PI) 807 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 808 #elif defined(CONFIG_T1042RDB) 809 #define FDTFILE "t1042rdb/t1042rdb.dtb" 810 #endif 811 812 #ifdef CONFIG_FSL_DIU_FB 813 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 814 #else 815 #define DIU_ENVIRONMENT 816 #endif 817 818 #define CONFIG_EXTRA_ENV_SETTINGS \ 819 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 820 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 821 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 822 "netdev=eth0\0" \ 823 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 824 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 825 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 826 "tftpflash=tftpboot $loadaddr $uboot && " \ 827 "protect off $ubootaddr +$filesize && " \ 828 "erase $ubootaddr +$filesize && " \ 829 "cp.b $loadaddr $ubootaddr $filesize && " \ 830 "protect on $ubootaddr +$filesize && " \ 831 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 832 "consoledev=ttyS0\0" \ 833 "ramdiskaddr=2000000\0" \ 834 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 835 "fdtaddr=c00000\0" \ 836 "fdtfile=" __stringify(FDTFILE) "\0" \ 837 "bdev=sda3\0" 838 839 #define CONFIG_LINUX \ 840 "setenv bootargs root=/dev/ram rw " \ 841 "console=$consoledev,$baudrate $othbootargs;" \ 842 "setenv ramdiskaddr 0x02000000;" \ 843 "setenv fdtaddr 0x00c00000;" \ 844 "setenv loadaddr 0x1000000;" \ 845 "bootm $loadaddr $ramdiskaddr $fdtaddr" 846 847 #define CONFIG_HDBOOT \ 848 "setenv bootargs root=/dev/$bdev rw " \ 849 "console=$consoledev,$baudrate $othbootargs;" \ 850 "tftp $loadaddr $bootfile;" \ 851 "tftp $fdtaddr $fdtfile;" \ 852 "bootm $loadaddr - $fdtaddr" 853 854 #define CONFIG_NFSBOOTCOMMAND \ 855 "setenv bootargs root=/dev/nfs rw " \ 856 "nfsroot=$serverip:$rootpath " \ 857 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 858 "console=$consoledev,$baudrate $othbootargs;" \ 859 "tftp $loadaddr $bootfile;" \ 860 "tftp $fdtaddr $fdtfile;" \ 861 "bootm $loadaddr - $fdtaddr" 862 863 #define CONFIG_RAMBOOTCOMMAND \ 864 "setenv bootargs root=/dev/ram rw " \ 865 "console=$consoledev,$baudrate $othbootargs;" \ 866 "tftp $ramdiskaddr $ramdiskfile;" \ 867 "tftp $loadaddr $bootfile;" \ 868 "tftp $fdtaddr $fdtfile;" \ 869 "bootm $loadaddr $ramdiskaddr $fdtaddr" 870 871 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 872 873 #ifdef CONFIG_SECURE_BOOT 874 #include <asm/fsl_secure_boot.h> 875 #define CONFIG_CMD_BLOB 876 #endif 877 878 #endif /* __CONFIG_H */ 879