1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #endif 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 37 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 38 #define CONFIG_FSL_IFC /* Enable IFC Support */ 39 #define CONFIG_PCI /* Enable PCI/PCIE */ 40 #define CONFIG_PCI_INDIRECT_BRIDGE 41 #define CONFIG_PCIE1 /* PCIE controler 1 */ 42 #define CONFIG_PCIE2 /* PCIE controler 2 */ 43 #define CONFIG_PCIE3 /* PCIE controler 3 */ 44 #define CONFIG_PCIE4 /* PCIE controler 4 */ 45 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 48 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 51 #define CONFIG_ENV_OVERWRITE 52 53 #ifdef CONFIG_SYS_NO_FLASH 54 #define CONFIG_ENV_IS_NOWHERE 55 #else 56 #define CONFIG_FLASH_CFI_DRIVER 57 #define CONFIG_SYS_FLASH_CFI 58 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 59 #endif 60 61 #ifndef CONFIG_SYS_NO_FLASH 62 #if defined(CONFIG_SPIFLASH) 63 #define CONFIG_SYS_EXTRA_ENV_RELOC 64 #define CONFIG_ENV_IS_IN_SPI_FLASH 65 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 66 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 67 #define CONFIG_ENV_SECT_SIZE 0x10000 68 #elif defined(CONFIG_SDCARD) 69 #define CONFIG_SYS_EXTRA_ENV_RELOC 70 #define CONFIG_ENV_IS_IN_MMC 71 #define CONFIG_SYS_MMC_ENV_DEV 0 72 #define CONFIG_ENV_SIZE 0x2000 73 #define CONFIG_ENV_OFFSET (512 * 1658) 74 #elif defined(CONFIG_NAND) 75 #define CONFIG_SYS_EXTRA_ENV_RELOC 76 #define CONFIG_ENV_IS_IN_NAND 77 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 78 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 79 #else 80 #define CONFIG_ENV_IS_IN_FLASH 81 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 82 #define CONFIG_ENV_SIZE 0x2000 83 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 84 #endif 85 #else /* CONFIG_SYS_NO_FLASH */ 86 #define CONFIG_ENV_SIZE 0x2000 87 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 88 #endif 89 90 #define CONFIG_SYS_CLK_FREQ 100000000 91 #define CONFIG_DDR_CLK_FREQ 66666666 92 93 /* 94 * These can be toggled for performance analysis, otherwise use default. 95 */ 96 #define CONFIG_SYS_CACHE_STASHING 97 #define CONFIG_BACKSIDE_L2_CACHE 98 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 99 #define CONFIG_BTB /* toggle branch predition */ 100 #define CONFIG_DDR_ECC 101 #ifdef CONFIG_DDR_ECC 102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 103 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 104 #endif 105 106 #define CONFIG_ENABLE_36BIT_PHYS 107 108 #define CONFIG_ADDR_MAP 109 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 110 111 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 112 #define CONFIG_SYS_MEMTEST_END 0x00400000 113 #define CONFIG_SYS_ALT_MEMTEST 114 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 115 116 /* 117 * Config the L3 Cache as L3 SRAM 118 */ 119 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 120 121 #define CONFIG_SYS_DCSRBAR 0xf0000000 122 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 123 124 /* 125 * DDR Setup 126 */ 127 #define CONFIG_VERY_BIG_RAM 128 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 130 131 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 132 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 133 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 134 135 #define CONFIG_DDR_SPD 136 #define CONFIG_SYS_DDR_RAW_TIMING 137 #define CONFIG_SYS_FSL_DDR3 138 139 #define CONFIG_SYS_SPD_BUS_NUM 0 140 #define SPD_EEPROM_ADDRESS 0x51 141 142 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 143 144 /* 145 * IFC Definitions 146 */ 147 #define CONFIG_SYS_FLASH_BASE 0xe8000000 148 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 149 150 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 151 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 152 CSPR_PORT_SIZE_16 | \ 153 CSPR_MSEL_NOR | \ 154 CSPR_V) 155 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 156 /* NOR Flash Timing Params */ 157 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 158 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 159 FTIM0_NOR_TEADC(0x5) | \ 160 FTIM0_NOR_TEAHC(0x5)) 161 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 162 FTIM1_NOR_TRAD_NOR(0x1A) |\ 163 FTIM1_NOR_TSEQRAD_NOR(0x13)) 164 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 165 FTIM2_NOR_TCH(0x4) | \ 166 FTIM2_NOR_TWPH(0x0E) | \ 167 FTIM2_NOR_TWP(0x1c)) 168 #define CONFIG_SYS_NOR_FTIM3 0x0 169 170 #define CONFIG_SYS_FLASH_QUIET_TEST 171 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 172 173 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 174 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 175 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 177 178 #define CONFIG_SYS_FLASH_EMPTY_INFO 179 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 180 181 /* CPLD on IFC */ 182 #define CPLD_LBMAP_MASK 0x3F 183 #define CPLD_BANK_SEL_MASK 0x07 184 #define CPLD_BANK_OVERRIDE 0x40 185 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 186 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 187 #define CPLD_LBMAP_RESET 0xFF 188 #define CPLD_LBMAP_SHIFT 0x03 189 190 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 191 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 192 #define CONFIG_SYS_CSPR2_EXT (0xf) 193 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 194 | CSPR_PORT_SIZE_8 \ 195 | CSPR_MSEL_GPCM \ 196 | CSPR_V) 197 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 198 #define CONFIG_SYS_CSOR2 0x0 199 /* CPLD Timing parameters for IFC CS2 */ 200 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 201 FTIM0_GPCM_TEADC(0x0e) | \ 202 FTIM0_GPCM_TEAHC(0x0e)) 203 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 204 FTIM1_GPCM_TRAD(0x1f)) 205 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 206 FTIM2_GPCM_TCH(0x0) | \ 207 FTIM2_GPCM_TWP(0x1f)) 208 #define CONFIG_SYS_CS2_FTIM3 0x0 209 210 /* NAND Flash on IFC */ 211 #define CONFIG_NAND_FSL_IFC 212 #define CONFIG_SYS_NAND_BASE 0xff800000 213 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 214 215 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 216 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 217 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 218 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 219 | CSPR_V) 220 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 221 222 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 223 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 224 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 225 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 226 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 227 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 228 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 229 230 #define CONFIG_SYS_NAND_ONFI_DETECTION 231 232 /* ONFI NAND Flash mode0 Timing Params */ 233 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 234 FTIM0_NAND_TWP(0x18) | \ 235 FTIM0_NAND_TWCHT(0x07) | \ 236 FTIM0_NAND_TWH(0x0a)) 237 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 238 FTIM1_NAND_TWBE(0x39) | \ 239 FTIM1_NAND_TRR(0x0e) | \ 240 FTIM1_NAND_TRP(0x18)) 241 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 242 FTIM2_NAND_TREH(0x0a) | \ 243 FTIM2_NAND_TWHRE(0x1e)) 244 #define CONFIG_SYS_NAND_FTIM3 0x0 245 246 #define CONFIG_SYS_NAND_DDR_LAW 11 247 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_MTD_NAND_VERIFY_WRITE 250 #define CONFIG_CMD_NAND 251 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 253 254 #if defined(CONFIG_NAND) 255 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 256 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 257 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 258 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 259 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 260 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 261 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 262 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 263 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 264 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 265 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 266 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 267 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 268 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 269 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 270 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 271 #else 272 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 273 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 274 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 275 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 276 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 277 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 278 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 279 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 280 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 281 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 282 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 283 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 284 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 285 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 286 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 287 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 288 #endif 289 290 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 291 292 #if defined(CONFIG_RAMBOOT_PBL) 293 #define CONFIG_SYS_RAMBOOT 294 #endif 295 296 #define CONFIG_BOARD_EARLY_INIT_R 297 #define CONFIG_MISC_INIT_R 298 299 #define CONFIG_HWCONFIG 300 301 /* define to use L1 as initial stack */ 302 #define CONFIG_L1_INIT_RAM 303 #define CONFIG_SYS_INIT_RAM_LOCK 304 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 307 /* The assembler doesn't like typecast */ 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 309 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 310 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 312 313 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 314 GENERATED_GBL_DATA_SIZE) 315 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 316 317 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 318 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 319 320 /* Serial Port - controlled on board with jumper J8 321 * open - index 2 322 * shorted - index 1 323 */ 324 #define CONFIG_CONS_INDEX 1 325 #define CONFIG_SYS_NS16550 326 #define CONFIG_SYS_NS16550_SERIAL 327 #define CONFIG_SYS_NS16550_REG_SIZE 1 328 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 329 330 #define CONFIG_SYS_BAUDRATE_TABLE \ 331 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 332 333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 335 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 336 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 337 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 338 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 339 340 /* Use the HUSH parser */ 341 #define CONFIG_SYS_HUSH_PARSER 342 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 343 344 /* pass open firmware flat tree */ 345 #define CONFIG_OF_LIBFDT 346 #define CONFIG_OF_BOARD_SETUP 347 #define CONFIG_OF_STDOUT_VIA_ALIAS 348 349 /* new uImage format support */ 350 #define CONFIG_FIT 351 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 352 353 /* I2C */ 354 #define CONFIG_SYS_I2C 355 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 356 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 357 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 358 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 359 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 360 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 361 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 362 363 /* I2C bus multiplexer */ 364 #define I2C_MUX_PCA_ADDR 0x70 365 #ifdef CONFIG_T1040RDB 366 #define I2C_MUX_CH_DEFAULT 0x8 367 #endif 368 369 #ifdef CONFIG_T1042RDB_PI 370 /* 371 * RTC configuration 372 */ 373 #define RTC 374 #define CONFIG_RTC_DS1337 1 375 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 376 377 /*DVI encoder*/ 378 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 379 #endif 380 381 /* 382 * eSPI - Enhanced SPI 383 */ 384 #define CONFIG_FSL_ESPI 385 #define CONFIG_SPI_FLASH 386 #define CONFIG_SPI_FLASH_STMICRO 387 #define CONFIG_CMD_SF 388 #define CONFIG_SF_DEFAULT_SPEED 10000000 389 #define CONFIG_SF_DEFAULT_MODE 0 390 #define CONFIG_ENV_SPI_BUS 0 391 #define CONFIG_ENV_SPI_CS 0 392 #define CONFIG_ENV_SPI_MAX_HZ 10000000 393 #define CONFIG_ENV_SPI_MODE 0 394 395 /* 396 * General PCI 397 * Memory space is mapped 1-1, but I/O space must start from 0. 398 */ 399 400 #ifdef CONFIG_PCI 401 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 402 #ifdef CONFIG_PCIE1 403 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 404 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 405 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 406 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 407 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 408 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 410 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 411 #endif 412 413 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 414 #ifdef CONFIG_PCIE2 415 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 416 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 417 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 418 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 419 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 420 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 421 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 422 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 423 #endif 424 425 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 426 #ifdef CONFIG_PCIE3 427 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 428 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 429 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 430 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 431 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 432 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 433 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 434 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 435 #endif 436 437 /* controller 4, Base address 203000 */ 438 #ifdef CONFIG_PCIE4 439 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 440 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 441 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 442 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 443 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 444 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 445 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 446 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 447 #endif 448 449 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 450 #define CONFIG_E1000 451 452 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 453 #define CONFIG_DOS_PARTITION 454 #endif /* CONFIG_PCI */ 455 456 /* SATA */ 457 #define CONFIG_FSL_SATA_V2 458 #ifdef CONFIG_FSL_SATA_V2 459 #define CONFIG_LIBATA 460 #define CONFIG_FSL_SATA 461 462 #define CONFIG_SYS_SATA_MAX_DEVICE 1 463 #define CONFIG_SATA1 464 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 465 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 466 467 #define CONFIG_LBA48 468 #define CONFIG_CMD_SATA 469 #define CONFIG_DOS_PARTITION 470 #define CONFIG_CMD_EXT2 471 #endif 472 473 /* 474 * USB 475 */ 476 #define CONFIG_HAS_FSL_DR_USB 477 478 #ifdef CONFIG_HAS_FSL_DR_USB 479 #define CONFIG_USB_EHCI 480 481 #ifdef CONFIG_USB_EHCI 482 #define CONFIG_CMD_USB 483 #define CONFIG_USB_STORAGE 484 #define CONFIG_USB_EHCI_FSL 485 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 486 #define CONFIG_CMD_EXT2 487 #endif 488 #endif 489 490 #define CONFIG_MMC 491 492 #ifdef CONFIG_MMC 493 #define CONFIG_FSL_ESDHC 494 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 495 #define CONFIG_CMD_MMC 496 #define CONFIG_GENERIC_MMC 497 #define CONFIG_CMD_EXT2 498 #define CONFIG_CMD_FAT 499 #define CONFIG_DOS_PARTITION 500 #endif 501 502 /* Qman/Bman */ 503 #ifndef CONFIG_NOBQFMAN 504 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 505 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 506 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 507 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 508 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 509 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 510 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 511 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 512 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 513 514 #define CONFIG_SYS_DPAA_FMAN 515 #define CONFIG_SYS_DPAA_PME 516 517 #define CONFIG_QE 518 #define CONFIG_U_QE 519 520 /* Default address of microcode for the Linux Fman driver */ 521 #if defined(CONFIG_SPIFLASH) 522 /* 523 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 524 * env, so we got 0x110000. 525 */ 526 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 527 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 528 #elif defined(CONFIG_SDCARD) 529 /* 530 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 531 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 532 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 533 */ 534 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 535 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 536 #elif defined(CONFIG_NAND) 537 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 538 #define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 539 #else 540 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 541 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 542 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 543 #endif 544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 545 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 546 #endif /* CONFIG_NOBQFMAN */ 547 548 #ifdef CONFIG_SYS_DPAA_FMAN 549 #define CONFIG_FMAN_ENET 550 #define CONFIG_PHY_VITESSE 551 #define CONFIG_PHY_REALTEK 552 #endif 553 554 #ifdef CONFIG_FMAN_ENET 555 #ifdef CONFIG_T1040RDB 556 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 557 #endif 558 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 559 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 560 561 #define CONFIG_MII /* MII PHY management */ 562 #define CONFIG_ETHPRIME "FM1@DTSEC4" 563 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 564 #endif 565 566 /* 567 * Environment 568 */ 569 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 570 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 571 572 /* 573 * Command line configuration. 574 */ 575 #include <config_cmd_default.h> 576 577 #ifdef CONFIG_T1042RDB_PI 578 #define CONFIG_CMD_DATE 579 #endif 580 #define CONFIG_CMD_DHCP 581 #define CONFIG_CMD_ELF 582 #define CONFIG_CMD_ERRATA 583 #define CONFIG_CMD_GREPENV 584 #define CONFIG_CMD_IRQ 585 #define CONFIG_CMD_I2C 586 #define CONFIG_CMD_MII 587 #define CONFIG_CMD_PING 588 #define CONFIG_CMD_REGINFO 589 #define CONFIG_CMD_SETEXPR 590 591 #ifdef CONFIG_PCI 592 #define CONFIG_CMD_PCI 593 #define CONFIG_CMD_NET 594 #endif 595 596 /* 597 * Miscellaneous configurable options 598 */ 599 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 600 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 601 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 602 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 603 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 604 #ifdef CONFIG_CMD_KGDB 605 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 606 #else 607 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 608 #endif 609 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 610 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 611 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 612 613 /* 614 * For booting Linux, the board info and command line data 615 * have to be in the first 64 MB of memory, since this is 616 * the maximum mapped by the Linux kernel during initialization. 617 */ 618 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 619 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 620 621 #ifdef CONFIG_CMD_KGDB 622 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 623 #endif 624 625 /* 626 * Dynamic MTD Partition support with mtdparts 627 */ 628 #ifndef CONFIG_SYS_NO_FLASH 629 #define CONFIG_MTD_DEVICE 630 #define CONFIG_MTD_PARTITIONS 631 #define CONFIG_CMD_MTDPARTS 632 #define CONFIG_FLASH_CFI_MTD 633 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 634 "spi0=spife110000.0" 635 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 636 "128k(dtb),96m(fs),-(user);"\ 637 "fff800000.flash:2m(uboot),9m(kernel),"\ 638 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 639 "2m(uboot),9m(kernel),128k(dtb),-(user)" 640 #endif 641 642 /* 643 * Environment Configuration 644 */ 645 #define CONFIG_ROOTPATH "/opt/nfsroot" 646 #define CONFIG_BOOTFILE "uImage" 647 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 648 649 /* default location for tftp and bootm */ 650 #define CONFIG_LOADADDR 1000000 651 652 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 653 654 #define CONFIG_BAUDRATE 115200 655 656 #define __USB_PHY_TYPE utmi 657 658 #ifdef CONFIG_T1040RDB 659 #define FDTFILE "t1040rdb/t1040rdb.dtb" 660 #define RAMDISKFILE "t1040rdb/ramdisk.uboot" 661 #elif CONFIG_T1042RDB_PI 662 #define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb" 663 #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" 664 #endif 665 666 #define CONFIG_EXTRA_ENV_SETTINGS \ 667 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 668 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 669 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 670 "netdev=eth0\0" \ 671 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 672 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 673 "tftpflash=tftpboot $loadaddr $uboot && " \ 674 "protect off $ubootaddr +$filesize && " \ 675 "erase $ubootaddr +$filesize && " \ 676 "cp.b $loadaddr $ubootaddr $filesize && " \ 677 "protect on $ubootaddr +$filesize && " \ 678 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 679 "consoledev=ttyS0\0" \ 680 "ramdiskaddr=2000000\0" \ 681 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 682 "fdtaddr=c00000\0" \ 683 "fdtfile=" __stringify(FDTFILE) "\0" \ 684 "bdev=sda3\0" \ 685 "c=ffe\0" 686 687 #define CONFIG_LINUX \ 688 "setenv bootargs root=/dev/ram rw " \ 689 "console=$consoledev,$baudrate $othbootargs;" \ 690 "setenv ramdiskaddr 0x02000000;" \ 691 "setenv fdtaddr 0x00c00000;" \ 692 "setenv loadaddr 0x1000000;" \ 693 "bootm $loadaddr $ramdiskaddr $fdtaddr" 694 695 #define CONFIG_HDBOOT \ 696 "setenv bootargs root=/dev/$bdev rw " \ 697 "console=$consoledev,$baudrate $othbootargs;" \ 698 "tftp $loadaddr $bootfile;" \ 699 "tftp $fdtaddr $fdtfile;" \ 700 "bootm $loadaddr - $fdtaddr" 701 702 #define CONFIG_NFSBOOTCOMMAND \ 703 "setenv bootargs root=/dev/nfs rw " \ 704 "nfsroot=$serverip:$rootpath " \ 705 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr - $fdtaddr" 710 711 #define CONFIG_RAMBOOTCOMMAND \ 712 "setenv bootargs root=/dev/ram rw " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "tftp $ramdiskaddr $ramdiskfile;" \ 715 "tftp $loadaddr $bootfile;" \ 716 "tftp $fdtaddr $fdtfile;" \ 717 "bootm $loadaddr $ramdiskaddr $fdtaddr" 718 719 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 720 721 #ifdef CONFIG_SECURE_BOOT 722 #include <asm/fsl_secure_boot.h> 723 #endif 724 725 #endif /* __CONFIG_H */ 726