1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #include <asm/config_mpc85xx.h> 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #ifdef CONFIG_T1040RDB 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 25 #endif 26 #ifdef CONFIG_T1042RDB_PI 27 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 28 #endif 29 #ifdef CONFIG_T1042RDB 30 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 31 #endif 32 #ifdef CONFIG_T1040D4RDB 33 #define CONFIG_SYS_FSL_PBL_RCW \ 34 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 35 #endif 36 #ifdef CONFIG_T1042D4RDB 37 #define CONFIG_SYS_FSL_PBL_RCW \ 38 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 39 #endif 40 41 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 42 #define CONFIG_SPL_ENV_SUPPORT 43 #define CONFIG_SPL_SERIAL_SUPPORT 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SPL_LIBGENERIC_SUPPORT 47 #define CONFIG_SPL_LIBCOMMON_SUPPORT 48 #define CONFIG_SPL_I2C_SUPPORT 49 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x30001000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 53 #define CONFIG_SPL_PAD_TO 0x40000 54 #define CONFIG_SPL_MAX_SIZE 0x28000 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 64 #ifdef CONFIG_NAND 65 #define CONFIG_SPL_NAND_SUPPORT 66 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 68 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 69 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_SPI_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_SUPPORT 78 #define CONFIG_SPL_SPI_FLASH_MINIMAL 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #define CONFIG_SPL_SPI_BOOT 88 #endif 89 90 #ifdef CONFIG_SDCARD 91 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 92 #define CONFIG_SPL_MMC_SUPPORT 93 #define CONFIG_SPL_MMC_MINIMAL 94 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 96 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 97 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #define CONFIG_SPL_MMC_BOOT 103 #endif 104 105 #endif 106 107 /* High Level Configuration Options */ 108 #define CONFIG_BOOKE 109 #define CONFIG_E500MC /* BOOKE e500mc family */ 110 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 111 #define CONFIG_MP /* support multiple processors */ 112 113 /* support deep sleep */ 114 #define CONFIG_DEEP_SLEEP 115 #if defined(CONFIG_DEEP_SLEEP) 116 #define CONFIG_BOARD_EARLY_INIT_F 117 #define CONFIG_SILENT_CONSOLE 118 #endif 119 120 #ifndef CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_TEXT_BASE 0xeff40000 122 #endif 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 129 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 130 #define CONFIG_FSL_IFC /* Enable IFC Support */ 131 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 132 #define CONFIG_PCI /* Enable PCI/PCIE */ 133 #define CONFIG_PCI_INDIRECT_BRIDGE 134 #define CONFIG_PCIE1 /* PCIE controler 1 */ 135 #define CONFIG_PCIE2 /* PCIE controler 2 */ 136 #define CONFIG_PCIE3 /* PCIE controler 3 */ 137 #define CONFIG_PCIE4 /* PCIE controler 4 */ 138 139 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 140 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 141 142 #define CONFIG_FSL_LAW /* Use common FSL init code */ 143 144 #define CONFIG_ENV_OVERWRITE 145 146 #ifndef CONFIG_SYS_NO_FLASH 147 #define CONFIG_FLASH_CFI_DRIVER 148 #define CONFIG_SYS_FLASH_CFI 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 150 #endif 151 152 #if defined(CONFIG_SPIFLASH) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_ENV_IS_IN_SPI_FLASH 155 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 156 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 157 #define CONFIG_ENV_SECT_SIZE 0x10000 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_MMC 161 #define CONFIG_SYS_MMC_ENV_DEV 0 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (512 * 0x800) 164 #elif defined(CONFIG_NAND) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_NAND 167 #define CONFIG_ENV_SIZE 0x2000 168 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 169 #else 170 #define CONFIG_ENV_IS_IN_FLASH 171 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 174 #endif 175 176 #define CONFIG_SYS_CLK_FREQ 100000000 177 #define CONFIG_DDR_CLK_FREQ 66666666 178 179 /* 180 * These can be toggled for performance analysis, otherwise use default. 181 */ 182 #define CONFIG_SYS_CACHE_STASHING 183 #define CONFIG_BACKSIDE_L2_CACHE 184 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 185 #define CONFIG_BTB /* toggle branch predition */ 186 #define CONFIG_DDR_ECC 187 #ifdef CONFIG_DDR_ECC 188 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 189 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 190 #endif 191 192 #define CONFIG_ENABLE_36BIT_PHYS 193 194 #define CONFIG_ADDR_MAP 195 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 196 197 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 198 #define CONFIG_SYS_MEMTEST_END 0x00400000 199 #define CONFIG_SYS_ALT_MEMTEST 200 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 201 202 /* 203 * Config the L3 Cache as L3 SRAM 204 */ 205 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 206 #define CONFIG_SYS_L3_SIZE 256 << 10 207 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 208 #ifdef CONFIG_RAMBOOT_PBL 209 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 210 #endif 211 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 212 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 213 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 214 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 215 216 #define CONFIG_SYS_DCSRBAR 0xf0000000 217 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 218 219 /* 220 * DDR Setup 221 */ 222 #define CONFIG_VERY_BIG_RAM 223 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 224 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 225 226 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 227 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 228 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 229 230 #define CONFIG_DDR_SPD 231 #ifndef CONFIG_SYS_FSL_DDR4 232 #define CONFIG_SYS_FSL_DDR3 233 #endif 234 235 #define CONFIG_SYS_SPD_BUS_NUM 0 236 #define SPD_EEPROM_ADDRESS 0x51 237 238 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 239 240 /* 241 * IFC Definitions 242 */ 243 #define CONFIG_SYS_FLASH_BASE 0xe8000000 244 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 245 246 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 247 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 248 CSPR_PORT_SIZE_16 | \ 249 CSPR_MSEL_NOR | \ 250 CSPR_V) 251 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 252 253 /* 254 * TDM Definition 255 */ 256 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 257 258 /* NOR Flash Timing Params */ 259 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 260 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 261 FTIM0_NOR_TEADC(0x5) | \ 262 FTIM0_NOR_TEAHC(0x5)) 263 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 264 FTIM1_NOR_TRAD_NOR(0x1A) |\ 265 FTIM1_NOR_TSEQRAD_NOR(0x13)) 266 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 267 FTIM2_NOR_TCH(0x4) | \ 268 FTIM2_NOR_TWPH(0x0E) | \ 269 FTIM2_NOR_TWP(0x1c)) 270 #define CONFIG_SYS_NOR_FTIM3 0x0 271 272 #define CONFIG_SYS_FLASH_QUIET_TEST 273 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 274 275 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 276 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 277 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 278 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 279 280 #define CONFIG_SYS_FLASH_EMPTY_INFO 281 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 282 283 /* CPLD on IFC */ 284 #define CPLD_LBMAP_MASK 0x3F 285 #define CPLD_BANK_SEL_MASK 0x07 286 #define CPLD_BANK_OVERRIDE 0x40 287 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 288 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 289 #define CPLD_LBMAP_RESET 0xFF 290 #define CPLD_LBMAP_SHIFT 0x03 291 292 #if defined(CONFIG_T1042RDB_PI) 293 #define CPLD_DIU_SEL_DFP 0x80 294 #elif defined(CONFIG_T1042D4RDB) 295 #define CPLD_DIU_SEL_DFP 0xc0 296 #endif 297 298 #if defined(CONFIG_T1040D4RDB) 299 #define CPLD_INT_MASK_ALL 0xFF 300 #define CPLD_INT_MASK_THERM 0x80 301 #define CPLD_INT_MASK_DVI_DFP 0x40 302 #define CPLD_INT_MASK_QSGMII1 0x20 303 #define CPLD_INT_MASK_QSGMII2 0x10 304 #define CPLD_INT_MASK_SGMI1 0x08 305 #define CPLD_INT_MASK_SGMI2 0x04 306 #define CPLD_INT_MASK_TDMR1 0x02 307 #define CPLD_INT_MASK_TDMR2 0x01 308 #endif 309 310 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 311 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 312 #define CONFIG_SYS_CSPR2_EXT (0xf) 313 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 314 | CSPR_PORT_SIZE_8 \ 315 | CSPR_MSEL_GPCM \ 316 | CSPR_V) 317 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 318 #define CONFIG_SYS_CSOR2 0x0 319 /* CPLD Timing parameters for IFC CS2 */ 320 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 321 FTIM0_GPCM_TEADC(0x0e) | \ 322 FTIM0_GPCM_TEAHC(0x0e)) 323 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 324 FTIM1_GPCM_TRAD(0x1f)) 325 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 326 FTIM2_GPCM_TCH(0x8) | \ 327 FTIM2_GPCM_TWP(0x1f)) 328 #define CONFIG_SYS_CS2_FTIM3 0x0 329 330 /* NAND Flash on IFC */ 331 #define CONFIG_NAND_FSL_IFC 332 #define CONFIG_SYS_NAND_BASE 0xff800000 333 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 334 335 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 336 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 337 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 338 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 339 | CSPR_V) 340 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 341 342 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 343 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 344 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 345 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 346 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 347 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 348 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 349 350 #define CONFIG_SYS_NAND_ONFI_DETECTION 351 352 /* ONFI NAND Flash mode0 Timing Params */ 353 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 354 FTIM0_NAND_TWP(0x18) | \ 355 FTIM0_NAND_TWCHT(0x07) | \ 356 FTIM0_NAND_TWH(0x0a)) 357 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 358 FTIM1_NAND_TWBE(0x39) | \ 359 FTIM1_NAND_TRR(0x0e) | \ 360 FTIM1_NAND_TRP(0x18)) 361 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 362 FTIM2_NAND_TREH(0x0a) | \ 363 FTIM2_NAND_TWHRE(0x1e)) 364 #define CONFIG_SYS_NAND_FTIM3 0x0 365 366 #define CONFIG_SYS_NAND_DDR_LAW 11 367 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 368 #define CONFIG_SYS_MAX_NAND_DEVICE 1 369 #define CONFIG_CMD_NAND 370 371 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 372 373 #if defined(CONFIG_NAND) 374 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 375 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 376 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 377 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 378 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 379 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 380 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 381 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 382 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 383 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 384 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 385 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 386 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 387 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 388 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 389 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 390 #else 391 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 392 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 393 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 394 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 395 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 396 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 397 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 398 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 399 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 400 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 401 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 402 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 403 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 404 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 405 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 406 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 407 #endif 408 409 #ifdef CONFIG_SPL_BUILD 410 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 411 #else 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 413 #endif 414 415 #if defined(CONFIG_RAMBOOT_PBL) 416 #define CONFIG_SYS_RAMBOOT 417 #endif 418 419 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 420 #if defined(CONFIG_NAND) 421 #define CONFIG_A008044_WORKAROUND 422 #endif 423 #endif 424 425 #define CONFIG_BOARD_EARLY_INIT_R 426 #define CONFIG_MISC_INIT_R 427 428 #define CONFIG_HWCONFIG 429 430 /* define to use L1 as initial stack */ 431 #define CONFIG_L1_INIT_RAM 432 #define CONFIG_SYS_INIT_RAM_LOCK 433 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 436 /* The assembler doesn't like typecast */ 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 438 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 439 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 440 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 441 442 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 443 GENERATED_GBL_DATA_SIZE) 444 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 445 446 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 447 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 448 449 /* Serial Port - controlled on board with jumper J8 450 * open - index 2 451 * shorted - index 1 452 */ 453 #define CONFIG_CONS_INDEX 1 454 #define CONFIG_SYS_NS16550 455 #define CONFIG_SYS_NS16550_SERIAL 456 #define CONFIG_SYS_NS16550_REG_SIZE 1 457 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 458 459 #define CONFIG_SYS_BAUDRATE_TABLE \ 460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 461 462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 464 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 465 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 466 #ifndef CONFIG_SPL_BUILD 467 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 468 #endif 469 470 /* Use the HUSH parser */ 471 #define CONFIG_SYS_HUSH_PARSER 472 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 473 474 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 475 /* Video */ 476 #define CONFIG_FSL_DIU_FB 477 478 #ifdef CONFIG_FSL_DIU_FB 479 #define CONFIG_FSL_DIU_CH7301 480 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 481 #define CONFIG_VIDEO 482 #define CONFIG_CMD_BMP 483 #define CONFIG_CFB_CONSOLE 484 #define CONFIG_CFB_CONSOLE_ANSI 485 #define CONFIG_VIDEO_SW_CURSOR 486 #define CONFIG_VGA_AS_SINGLE_DEVICE 487 #define CONFIG_VIDEO_LOGO 488 #define CONFIG_VIDEO_BMP_LOGO 489 #endif 490 #endif 491 492 /* pass open firmware flat tree */ 493 #define CONFIG_OF_LIBFDT 494 #define CONFIG_OF_BOARD_SETUP 495 #define CONFIG_OF_STDOUT_VIA_ALIAS 496 497 /* new uImage format support */ 498 #define CONFIG_FIT 499 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 500 501 /* I2C */ 502 #define CONFIG_SYS_I2C 503 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 504 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 505 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 506 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 507 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 508 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 509 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 510 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 511 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 512 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 513 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 514 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 515 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 516 517 /* I2C bus multiplexer */ 518 #define I2C_MUX_PCA_ADDR 0x70 519 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 520 #define I2C_MUX_CH_DEFAULT 0x8 521 #endif 522 523 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 524 /* LDI/DVI Encoder for display */ 525 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 526 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 527 528 /* 529 * RTC configuration 530 */ 531 #define RTC 532 #define CONFIG_RTC_DS1337 1 533 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 534 535 /*DVI encoder*/ 536 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 537 #endif 538 539 /* 540 * eSPI - Enhanced SPI 541 */ 542 #define CONFIG_FSL_ESPI 543 #define CONFIG_SPI_FLASH_STMICRO 544 #define CONFIG_SPI_FLASH_BAR 545 #define CONFIG_CMD_SF 546 #define CONFIG_SF_DEFAULT_SPEED 10000000 547 #define CONFIG_SF_DEFAULT_MODE 0 548 #define CONFIG_ENV_SPI_BUS 0 549 #define CONFIG_ENV_SPI_CS 0 550 #define CONFIG_ENV_SPI_MAX_HZ 10000000 551 #define CONFIG_ENV_SPI_MODE 0 552 553 /* 554 * General PCI 555 * Memory space is mapped 1-1, but I/O space must start from 0. 556 */ 557 558 #ifdef CONFIG_PCI 559 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 560 #ifdef CONFIG_PCIE1 561 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 562 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 563 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 564 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 565 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 566 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 567 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 568 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 569 #endif 570 571 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 572 #ifdef CONFIG_PCIE2 573 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 574 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 576 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 577 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 578 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 580 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 581 #endif 582 583 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 584 #ifdef CONFIG_PCIE3 585 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 586 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 587 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 588 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 590 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 591 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 592 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 593 #endif 594 595 /* controller 4, Base address 203000 */ 596 #ifdef CONFIG_PCIE4 597 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 598 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 599 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 600 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 601 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 602 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 603 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 604 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 608 609 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 610 #define CONFIG_DOS_PARTITION 611 #endif /* CONFIG_PCI */ 612 613 /* SATA */ 614 #define CONFIG_FSL_SATA_V2 615 #ifdef CONFIG_FSL_SATA_V2 616 #define CONFIG_LIBATA 617 #define CONFIG_FSL_SATA 618 619 #define CONFIG_SYS_SATA_MAX_DEVICE 1 620 #define CONFIG_SATA1 621 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 622 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 623 624 #define CONFIG_LBA48 625 #define CONFIG_CMD_SATA 626 #define CONFIG_DOS_PARTITION 627 #define CONFIG_CMD_EXT2 628 #endif 629 630 /* 631 * USB 632 */ 633 #define CONFIG_HAS_FSL_DR_USB 634 635 #ifdef CONFIG_HAS_FSL_DR_USB 636 #define CONFIG_USB_EHCI 637 638 #ifdef CONFIG_USB_EHCI 639 #define CONFIG_CMD_USB 640 #define CONFIG_USB_STORAGE 641 #define CONFIG_USB_EHCI_FSL 642 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 643 #define CONFIG_CMD_EXT2 644 #endif 645 #endif 646 647 #define CONFIG_MMC 648 649 #ifdef CONFIG_MMC 650 #define CONFIG_FSL_ESDHC 651 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 652 #define CONFIG_CMD_MMC 653 #define CONFIG_GENERIC_MMC 654 #define CONFIG_CMD_EXT2 655 #define CONFIG_CMD_FAT 656 #define CONFIG_DOS_PARTITION 657 #endif 658 659 /* Qman/Bman */ 660 #ifndef CONFIG_NOBQFMAN 661 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 662 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 663 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 664 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 665 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 666 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 667 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 668 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 669 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 670 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 671 CONFIG_SYS_BMAN_CENA_SIZE) 672 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 674 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 675 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 676 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 677 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 678 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 679 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 680 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 681 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 682 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 683 CONFIG_SYS_QMAN_CENA_SIZE) 684 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 685 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 686 687 #define CONFIG_SYS_DPAA_FMAN 688 #define CONFIG_SYS_DPAA_PME 689 690 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 691 #define CONFIG_QE 692 #define CONFIG_U_QE 693 #endif 694 695 /* Default address of microcode for the Linux Fman driver */ 696 #if defined(CONFIG_SPIFLASH) 697 /* 698 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 699 * env, so we got 0x110000. 700 */ 701 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 702 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 703 #elif defined(CONFIG_SDCARD) 704 /* 705 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 706 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 707 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 708 */ 709 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 710 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 711 #elif defined(CONFIG_NAND) 712 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 713 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 714 #else 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 716 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 717 #endif 718 719 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 720 #if defined(CONFIG_SPIFLASH) 721 #define CONFIG_SYS_QE_FW_ADDR 0x130000 722 #elif defined(CONFIG_SDCARD) 723 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 724 #elif defined(CONFIG_NAND) 725 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 726 #else 727 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 728 #endif 729 #endif 730 731 732 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 733 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 734 #endif /* CONFIG_NOBQFMAN */ 735 736 #ifdef CONFIG_SYS_DPAA_FMAN 737 #define CONFIG_FMAN_ENET 738 #define CONFIG_PHY_VITESSE 739 #define CONFIG_PHY_REALTEK 740 #endif 741 742 #ifdef CONFIG_FMAN_ENET 743 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 744 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 745 #elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) 746 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 747 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 748 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 749 #endif 750 751 #ifdef CONFIG_T104XD4RDB 752 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 753 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 754 #else 755 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 756 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 757 #endif 758 759 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 760 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 761 #define CONFIG_VSC9953 762 #define CONFIG_VSC9953_CMD 763 #ifdef CONFIG_T1040RDB 764 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 765 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 766 #else 767 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 768 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 769 #endif 770 #endif 771 772 #define CONFIG_MII /* MII PHY management */ 773 #define CONFIG_ETHPRIME "FM1@DTSEC4" 774 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 775 #endif 776 777 /* 778 * Environment 779 */ 780 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 781 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 782 783 /* 784 * Command line configuration. 785 */ 786 #ifdef CONFIG_T1042RDB_PI 787 #define CONFIG_CMD_DATE 788 #endif 789 #define CONFIG_CMD_DHCP 790 #define CONFIG_CMD_ELF 791 #define CONFIG_CMD_ERRATA 792 #define CONFIG_CMD_GREPENV 793 #define CONFIG_CMD_IRQ 794 #define CONFIG_CMD_I2C 795 #define CONFIG_CMD_MII 796 #define CONFIG_CMD_PING 797 #define CONFIG_CMD_REGINFO 798 799 #ifdef CONFIG_PCI 800 #define CONFIG_CMD_PCI 801 #endif 802 803 /* Hash command with SHA acceleration supported in hardware */ 804 #ifdef CONFIG_FSL_CAAM 805 #define CONFIG_CMD_HASH 806 #define CONFIG_SHA_HW_ACCEL 807 #endif 808 809 /* 810 * Miscellaneous configurable options 811 */ 812 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 813 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 814 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 815 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 816 #ifdef CONFIG_CMD_KGDB 817 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 818 #else 819 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 820 #endif 821 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 822 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 823 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 824 825 /* 826 * For booting Linux, the board info and command line data 827 * have to be in the first 64 MB of memory, since this is 828 * the maximum mapped by the Linux kernel during initialization. 829 */ 830 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 831 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 832 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 835 #endif 836 837 /* 838 * Dynamic MTD Partition support with mtdparts 839 */ 840 #ifndef CONFIG_SYS_NO_FLASH 841 #define CONFIG_MTD_DEVICE 842 #define CONFIG_MTD_PARTITIONS 843 #define CONFIG_CMD_MTDPARTS 844 #define CONFIG_FLASH_CFI_MTD 845 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 846 "spi0=spife110000.0" 847 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 848 "128k(dtb),96m(fs),-(user);"\ 849 "fff800000.flash:2m(uboot),9m(kernel),"\ 850 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 851 "2m(uboot),9m(kernel),128k(dtb),-(user)" 852 #endif 853 854 /* 855 * Environment Configuration 856 */ 857 #define CONFIG_ROOTPATH "/opt/nfsroot" 858 #define CONFIG_BOOTFILE "uImage" 859 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 860 861 /* default location for tftp and bootm */ 862 #define CONFIG_LOADADDR 1000000 863 864 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 865 866 #define CONFIG_BAUDRATE 115200 867 868 #define __USB_PHY_TYPE utmi 869 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 870 871 #ifdef CONFIG_T1040RDB 872 #define FDTFILE "t1040rdb/t1040rdb.dtb" 873 #elif defined(CONFIG_T1042RDB_PI) 874 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 875 #elif defined(CONFIG_T1042RDB) 876 #define FDTFILE "t1042rdb/t1042rdb.dtb" 877 #elif defined(CONFIG_T1040D4RDB) 878 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 879 #elif defined(CONFIG_T1042D4RDB) 880 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 881 #endif 882 883 #ifdef CONFIG_FSL_DIU_FB 884 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 885 #else 886 #define DIU_ENVIRONMENT 887 #endif 888 889 #define CONFIG_EXTRA_ENV_SETTINGS \ 890 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 891 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 892 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 893 "netdev=eth0\0" \ 894 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 895 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 896 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 897 "tftpflash=tftpboot $loadaddr $uboot && " \ 898 "protect off $ubootaddr +$filesize && " \ 899 "erase $ubootaddr +$filesize && " \ 900 "cp.b $loadaddr $ubootaddr $filesize && " \ 901 "protect on $ubootaddr +$filesize && " \ 902 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 903 "consoledev=ttyS0\0" \ 904 "ramdiskaddr=2000000\0" \ 905 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 906 "fdtaddr=c00000\0" \ 907 "fdtfile=" __stringify(FDTFILE) "\0" \ 908 "bdev=sda3\0" 909 910 #define CONFIG_LINUX \ 911 "setenv bootargs root=/dev/ram rw " \ 912 "console=$consoledev,$baudrate $othbootargs;" \ 913 "setenv ramdiskaddr 0x02000000;" \ 914 "setenv fdtaddr 0x00c00000;" \ 915 "setenv loadaddr 0x1000000;" \ 916 "bootm $loadaddr $ramdiskaddr $fdtaddr" 917 918 #define CONFIG_HDBOOT \ 919 "setenv bootargs root=/dev/$bdev rw " \ 920 "console=$consoledev,$baudrate $othbootargs;" \ 921 "tftp $loadaddr $bootfile;" \ 922 "tftp $fdtaddr $fdtfile;" \ 923 "bootm $loadaddr - $fdtaddr" 924 925 #define CONFIG_NFSBOOTCOMMAND \ 926 "setenv bootargs root=/dev/nfs rw " \ 927 "nfsroot=$serverip:$rootpath " \ 928 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 929 "console=$consoledev,$baudrate $othbootargs;" \ 930 "tftp $loadaddr $bootfile;" \ 931 "tftp $fdtaddr $fdtfile;" \ 932 "bootm $loadaddr - $fdtaddr" 933 934 #define CONFIG_RAMBOOTCOMMAND \ 935 "setenv bootargs root=/dev/ram rw " \ 936 "console=$consoledev,$baudrate $othbootargs;" \ 937 "tftp $ramdiskaddr $ramdiskfile;" \ 938 "tftp $loadaddr $bootfile;" \ 939 "tftp $fdtaddr $fdtfile;" \ 940 "bootm $loadaddr $ramdiskaddr $fdtaddr" 941 942 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 943 944 #ifdef CONFIG_SECURE_BOOT 945 #include <asm/fsl_secure_boot.h> 946 #define CONFIG_CMD_BLOB 947 #endif 948 949 #endif /* __CONFIG_H */ 950