1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 15 #define CONFIG_E500 /* BOOKE e500 family */ 16 #include <asm/config_mpc85xx.h> 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 20 #ifndef CONFIG_SECURE_BOOT 21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 22 #else 23 #define CONFIG_SYS_FSL_PBL_PBI \ 24 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 25 #endif 26 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_FSL_LAW /* Use common FSL init code */ 30 #define CONFIG_SYS_TEXT_BASE 0x30001000 31 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 32 #define CONFIG_SPL_PAD_TO 0x40000 33 #define CONFIG_SPL_MAX_SIZE 0x28000 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #define CONFIG_SYS_NO_FLASH 39 #endif 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 43 #ifdef CONFIG_NAND 44 #ifdef CONFIG_SECURE_BOOT 45 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 46 /* 47 * HDR would be appended at end of image and copied to DDR along 48 * with U-Boot image. 49 */ 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 51 CONFIG_U_BOOT_HDR_SIZE) 52 #else 53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 54 #endif 55 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #ifdef CONFIG_T1040RDB 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_T1042RDB_PI 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_T1042RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_T1040D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 74 #endif 75 #ifdef CONFIG_T1042D4RDB 76 #define CONFIG_SYS_FSL_PBL_RCW \ 77 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 78 #endif 79 #define CONFIG_SPL_NAND_BOOT 80 #endif 81 82 #ifdef CONFIG_SPIFLASH 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #ifdef CONFIG_T1040RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_T1042RDB_PI 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_T1042RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_T1040D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 108 #endif 109 #ifdef CONFIG_T1042D4RDB 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 112 #endif 113 #define CONFIG_SPL_SPI_BOOT 114 #endif 115 116 #ifdef CONFIG_SDCARD 117 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 118 #define CONFIG_SPL_MMC_MINIMAL 119 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 120 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 121 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 122 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 123 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 124 #ifndef CONFIG_SPL_BUILD 125 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 126 #endif 127 #ifdef CONFIG_T1040RDB 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_T1042RDB_PI 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_T1042RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_T1040D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 142 #endif 143 #ifdef CONFIG_T1042D4RDB 144 #define CONFIG_SYS_FSL_PBL_RCW \ 145 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 146 #endif 147 #define CONFIG_SPL_MMC_BOOT 148 #endif 149 150 #endif 151 152 /* High Level Configuration Options */ 153 #define CONFIG_BOOKE 154 #define CONFIG_E500MC /* BOOKE e500mc family */ 155 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 156 #define CONFIG_MP /* support multiple processors */ 157 158 /* support deep sleep */ 159 #define CONFIG_DEEP_SLEEP 160 #if defined(CONFIG_DEEP_SLEEP) 161 #define CONFIG_BOARD_EARLY_INIT_F 162 #endif 163 164 #ifndef CONFIG_SYS_TEXT_BASE 165 #define CONFIG_SYS_TEXT_BASE 0xeff40000 166 #endif 167 168 #ifndef CONFIG_RESET_VECTOR_ADDRESS 169 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 170 #endif 171 172 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 173 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 174 #define CONFIG_FSL_IFC /* Enable IFC Support */ 175 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 176 #define CONFIG_PCI /* Enable PCI/PCIE */ 177 #define CONFIG_PCI_INDIRECT_BRIDGE 178 #define CONFIG_PCIE1 /* PCIE controller 1 */ 179 #define CONFIG_PCIE2 /* PCIE controller 2 */ 180 #define CONFIG_PCIE3 /* PCIE controller 3 */ 181 #define CONFIG_PCIE4 /* PCIE controller 4 */ 182 183 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 184 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 185 186 #define CONFIG_FSL_LAW /* Use common FSL init code */ 187 188 #define CONFIG_ENV_OVERWRITE 189 190 #ifndef CONFIG_SYS_NO_FLASH 191 #define CONFIG_FLASH_CFI_DRIVER 192 #define CONFIG_SYS_FLASH_CFI 193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 194 #endif 195 196 #if defined(CONFIG_SPIFLASH) 197 #define CONFIG_SYS_EXTRA_ENV_RELOC 198 #define CONFIG_ENV_IS_IN_SPI_FLASH 199 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 200 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 201 #define CONFIG_ENV_SECT_SIZE 0x10000 202 #elif defined(CONFIG_SDCARD) 203 #define CONFIG_SYS_EXTRA_ENV_RELOC 204 #define CONFIG_ENV_IS_IN_MMC 205 #define CONFIG_SYS_MMC_ENV_DEV 0 206 #define CONFIG_ENV_SIZE 0x2000 207 #define CONFIG_ENV_OFFSET (512 * 0x800) 208 #elif defined(CONFIG_NAND) 209 #ifdef CONFIG_SECURE_BOOT 210 #define CONFIG_RAMBOOT_NAND 211 #define CONFIG_BOOTSCRIPT_COPY_RAM 212 #endif 213 #define CONFIG_SYS_EXTRA_ENV_RELOC 214 #define CONFIG_ENV_IS_IN_NAND 215 #define CONFIG_ENV_SIZE 0x2000 216 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 217 #else 218 #define CONFIG_ENV_IS_IN_FLASH 219 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 220 #define CONFIG_ENV_SIZE 0x2000 221 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 222 #endif 223 224 #define CONFIG_SYS_CLK_FREQ 100000000 225 #define CONFIG_DDR_CLK_FREQ 66666666 226 227 /* 228 * These can be toggled for performance analysis, otherwise use default. 229 */ 230 #define CONFIG_SYS_CACHE_STASHING 231 #define CONFIG_BACKSIDE_L2_CACHE 232 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 233 #define CONFIG_BTB /* toggle branch predition */ 234 #define CONFIG_DDR_ECC 235 #ifdef CONFIG_DDR_ECC 236 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 237 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 238 #endif 239 240 #define CONFIG_ENABLE_36BIT_PHYS 241 242 #define CONFIG_ADDR_MAP 243 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 244 245 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 246 #define CONFIG_SYS_MEMTEST_END 0x00400000 247 #define CONFIG_SYS_ALT_MEMTEST 248 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 249 250 /* 251 * Config the L3 Cache as L3 SRAM 252 */ 253 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 254 /* 255 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 256 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 257 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 258 */ 259 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 260 #define CONFIG_SYS_L3_SIZE 256 << 10 261 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 262 #ifdef CONFIG_RAMBOOT_PBL 263 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 264 #endif 265 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 266 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 267 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 268 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 269 270 #define CONFIG_SYS_DCSRBAR 0xf0000000 271 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 272 273 /* 274 * DDR Setup 275 */ 276 #define CONFIG_VERY_BIG_RAM 277 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 278 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 279 280 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 281 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 282 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 283 284 #define CONFIG_DDR_SPD 285 #ifndef CONFIG_SYS_FSL_DDR4 286 #define CONFIG_SYS_FSL_DDR3 287 #endif 288 289 #define CONFIG_SYS_SPD_BUS_NUM 0 290 #define SPD_EEPROM_ADDRESS 0x51 291 292 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 293 294 /* 295 * IFC Definitions 296 */ 297 #define CONFIG_SYS_FLASH_BASE 0xe8000000 298 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 299 300 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 301 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 302 CSPR_PORT_SIZE_16 | \ 303 CSPR_MSEL_NOR | \ 304 CSPR_V) 305 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 306 307 /* 308 * TDM Definition 309 */ 310 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 311 312 /* NOR Flash Timing Params */ 313 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 314 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 315 FTIM0_NOR_TEADC(0x5) | \ 316 FTIM0_NOR_TEAHC(0x5)) 317 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 318 FTIM1_NOR_TRAD_NOR(0x1A) |\ 319 FTIM1_NOR_TSEQRAD_NOR(0x13)) 320 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 321 FTIM2_NOR_TCH(0x4) | \ 322 FTIM2_NOR_TWPH(0x0E) | \ 323 FTIM2_NOR_TWP(0x1c)) 324 #define CONFIG_SYS_NOR_FTIM3 0x0 325 326 #define CONFIG_SYS_FLASH_QUIET_TEST 327 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 328 329 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 330 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 331 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 332 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 333 334 #define CONFIG_SYS_FLASH_EMPTY_INFO 335 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 336 337 /* CPLD on IFC */ 338 #define CPLD_LBMAP_MASK 0x3F 339 #define CPLD_BANK_SEL_MASK 0x07 340 #define CPLD_BANK_OVERRIDE 0x40 341 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 342 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 343 #define CPLD_LBMAP_RESET 0xFF 344 #define CPLD_LBMAP_SHIFT 0x03 345 346 #if defined(CONFIG_T1042RDB_PI) 347 #define CPLD_DIU_SEL_DFP 0x80 348 #elif defined(CONFIG_T1042D4RDB) 349 #define CPLD_DIU_SEL_DFP 0xc0 350 #endif 351 352 #if defined(CONFIG_T1040D4RDB) 353 #define CPLD_INT_MASK_ALL 0xFF 354 #define CPLD_INT_MASK_THERM 0x80 355 #define CPLD_INT_MASK_DVI_DFP 0x40 356 #define CPLD_INT_MASK_QSGMII1 0x20 357 #define CPLD_INT_MASK_QSGMII2 0x10 358 #define CPLD_INT_MASK_SGMI1 0x08 359 #define CPLD_INT_MASK_SGMI2 0x04 360 #define CPLD_INT_MASK_TDMR1 0x02 361 #define CPLD_INT_MASK_TDMR2 0x01 362 #endif 363 364 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 365 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 366 #define CONFIG_SYS_CSPR2_EXT (0xf) 367 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 368 | CSPR_PORT_SIZE_8 \ 369 | CSPR_MSEL_GPCM \ 370 | CSPR_V) 371 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 372 #define CONFIG_SYS_CSOR2 0x0 373 /* CPLD Timing parameters for IFC CS2 */ 374 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 375 FTIM0_GPCM_TEADC(0x0e) | \ 376 FTIM0_GPCM_TEAHC(0x0e)) 377 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 378 FTIM1_GPCM_TRAD(0x1f)) 379 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 380 FTIM2_GPCM_TCH(0x8) | \ 381 FTIM2_GPCM_TWP(0x1f)) 382 #define CONFIG_SYS_CS2_FTIM3 0x0 383 384 /* NAND Flash on IFC */ 385 #define CONFIG_NAND_FSL_IFC 386 #define CONFIG_SYS_NAND_BASE 0xff800000 387 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 388 389 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 390 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 391 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 392 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 393 | CSPR_V) 394 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 395 396 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 397 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 398 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 399 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 400 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 401 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 402 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 403 404 #define CONFIG_SYS_NAND_ONFI_DETECTION 405 406 /* ONFI NAND Flash mode0 Timing Params */ 407 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 408 FTIM0_NAND_TWP(0x18) | \ 409 FTIM0_NAND_TWCHT(0x07) | \ 410 FTIM0_NAND_TWH(0x0a)) 411 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 412 FTIM1_NAND_TWBE(0x39) | \ 413 FTIM1_NAND_TRR(0x0e) | \ 414 FTIM1_NAND_TRP(0x18)) 415 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 416 FTIM2_NAND_TREH(0x0a) | \ 417 FTIM2_NAND_TWHRE(0x1e)) 418 #define CONFIG_SYS_NAND_FTIM3 0x0 419 420 #define CONFIG_SYS_NAND_DDR_LAW 11 421 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 422 #define CONFIG_SYS_MAX_NAND_DEVICE 1 423 #define CONFIG_CMD_NAND 424 425 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 426 427 #if defined(CONFIG_NAND) 428 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 429 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 430 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 431 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 432 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 433 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 434 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 435 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 436 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 437 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 438 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 439 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 440 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 441 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 442 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 443 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 444 #else 445 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 446 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 447 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 448 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 449 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 450 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 451 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 452 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 453 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 454 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 455 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 456 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 457 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 458 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 459 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 460 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 461 #endif 462 463 #ifdef CONFIG_SPL_BUILD 464 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 465 #else 466 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 467 #endif 468 469 #if defined(CONFIG_RAMBOOT_PBL) 470 #define CONFIG_SYS_RAMBOOT 471 #endif 472 473 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 474 #if defined(CONFIG_NAND) 475 #define CONFIG_A008044_WORKAROUND 476 #endif 477 #endif 478 479 #define CONFIG_BOARD_EARLY_INIT_R 480 #define CONFIG_MISC_INIT_R 481 482 #define CONFIG_HWCONFIG 483 484 /* define to use L1 as initial stack */ 485 #define CONFIG_L1_INIT_RAM 486 #define CONFIG_SYS_INIT_RAM_LOCK 487 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 489 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 490 /* The assembler doesn't like typecast */ 491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 492 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 493 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 494 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 495 496 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 497 GENERATED_GBL_DATA_SIZE) 498 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 499 500 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 501 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 502 503 /* Serial Port - controlled on board with jumper J8 504 * open - index 2 505 * shorted - index 1 506 */ 507 #define CONFIG_CONS_INDEX 1 508 #define CONFIG_SYS_NS16550_SERIAL 509 #define CONFIG_SYS_NS16550_REG_SIZE 1 510 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 511 512 #define CONFIG_SYS_BAUDRATE_TABLE \ 513 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 514 515 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 516 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 517 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 518 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 519 520 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 521 /* Video */ 522 #define CONFIG_FSL_DIU_FB 523 524 #ifdef CONFIG_FSL_DIU_FB 525 #define CONFIG_FSL_DIU_CH7301 526 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 527 #define CONFIG_CMD_BMP 528 #define CONFIG_VIDEO_LOGO 529 #define CONFIG_VIDEO_BMP_LOGO 530 #endif 531 #endif 532 533 /* I2C */ 534 #define CONFIG_SYS_I2C 535 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 536 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 537 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 538 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 539 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 540 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 541 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 542 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 543 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 544 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 545 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 546 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 547 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 548 549 /* I2C bus multiplexer */ 550 #define I2C_MUX_PCA_ADDR 0x70 551 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 552 #define I2C_MUX_CH_DEFAULT 0x8 553 #endif 554 555 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 556 /* LDI/DVI Encoder for display */ 557 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 558 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 559 560 /* 561 * RTC configuration 562 */ 563 #define RTC 564 #define CONFIG_RTC_DS1337 1 565 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 566 567 /*DVI encoder*/ 568 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 569 #endif 570 571 /* 572 * eSPI - Enhanced SPI 573 */ 574 #define CONFIG_SPI_FLASH_BAR 575 #define CONFIG_SF_DEFAULT_SPEED 10000000 576 #define CONFIG_SF_DEFAULT_MODE 0 577 #define CONFIG_ENV_SPI_BUS 0 578 #define CONFIG_ENV_SPI_CS 0 579 #define CONFIG_ENV_SPI_MAX_HZ 10000000 580 #define CONFIG_ENV_SPI_MODE 0 581 582 /* 583 * General PCI 584 * Memory space is mapped 1-1, but I/O space must start from 0. 585 */ 586 587 #ifdef CONFIG_PCI 588 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 589 #ifdef CONFIG_PCIE1 590 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 591 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 592 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 593 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 594 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 595 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 596 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 597 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 598 #endif 599 600 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 601 #ifdef CONFIG_PCIE2 602 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 603 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 604 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 605 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 606 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 607 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 608 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 609 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 610 #endif 611 612 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 613 #ifdef CONFIG_PCIE3 614 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 615 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 616 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 617 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 618 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 619 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 620 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 621 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 622 #endif 623 624 /* controller 4, Base address 203000 */ 625 #ifdef CONFIG_PCIE4 626 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 627 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 628 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 629 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 630 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 631 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 632 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 633 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 634 #endif 635 636 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 637 638 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 639 #define CONFIG_DOS_PARTITION 640 #endif /* CONFIG_PCI */ 641 642 /* SATA */ 643 #define CONFIG_FSL_SATA_V2 644 #ifdef CONFIG_FSL_SATA_V2 645 #define CONFIG_LIBATA 646 #define CONFIG_FSL_SATA 647 648 #define CONFIG_SYS_SATA_MAX_DEVICE 1 649 #define CONFIG_SATA1 650 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 651 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 652 653 #define CONFIG_LBA48 654 #define CONFIG_CMD_SATA 655 #define CONFIG_DOS_PARTITION 656 #endif 657 658 /* 659 * USB 660 */ 661 #define CONFIG_HAS_FSL_DR_USB 662 663 #ifdef CONFIG_HAS_FSL_DR_USB 664 #define CONFIG_USB_EHCI 665 666 #ifdef CONFIG_USB_EHCI 667 #define CONFIG_USB_EHCI_FSL 668 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 669 #endif 670 #endif 671 672 #define CONFIG_MMC 673 674 #ifdef CONFIG_MMC 675 #define CONFIG_FSL_ESDHC 676 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 677 #define CONFIG_GENERIC_MMC 678 #define CONFIG_DOS_PARTITION 679 #endif 680 681 /* Qman/Bman */ 682 #ifndef CONFIG_NOBQFMAN 683 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 684 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 685 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 686 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 687 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 688 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 689 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 690 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 691 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 692 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 693 CONFIG_SYS_BMAN_CENA_SIZE) 694 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 695 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 696 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 697 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 698 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 699 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 700 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 701 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 702 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 703 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 704 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 705 CONFIG_SYS_QMAN_CENA_SIZE) 706 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 707 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 708 709 #define CONFIG_SYS_DPAA_FMAN 710 #define CONFIG_SYS_DPAA_PME 711 712 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 713 #define CONFIG_QE 714 #define CONFIG_U_QE 715 #endif 716 717 /* Default address of microcode for the Linux Fman driver */ 718 #if defined(CONFIG_SPIFLASH) 719 /* 720 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 721 * env, so we got 0x110000. 722 */ 723 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 724 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 725 #elif defined(CONFIG_SDCARD) 726 /* 727 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 728 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 729 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 730 */ 731 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 732 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 733 #elif defined(CONFIG_NAND) 734 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 735 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 736 #else 737 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 738 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 739 #endif 740 741 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 742 #if defined(CONFIG_SPIFLASH) 743 #define CONFIG_SYS_QE_FW_ADDR 0x130000 744 #elif defined(CONFIG_SDCARD) 745 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 746 #elif defined(CONFIG_NAND) 747 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 748 #else 749 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 750 #endif 751 #endif 752 753 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 754 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 755 #endif /* CONFIG_NOBQFMAN */ 756 757 #ifdef CONFIG_SYS_DPAA_FMAN 758 #define CONFIG_FMAN_ENET 759 #define CONFIG_PHY_VITESSE 760 #define CONFIG_PHY_REALTEK 761 #endif 762 763 #ifdef CONFIG_FMAN_ENET 764 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 765 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 766 #elif defined(CONFIG_T1040D4RDB) 767 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 768 #elif defined(CONFIG_T1042D4RDB) 769 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 770 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 771 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 772 #endif 773 774 #ifdef CONFIG_T104XD4RDB 775 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 776 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 777 #else 778 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 779 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 780 #endif 781 782 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 783 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 784 #define CONFIG_VSC9953 785 #define CONFIG_CMD_ETHSW 786 #ifdef CONFIG_T1040RDB 787 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 788 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 789 #else 790 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 791 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 792 #endif 793 #endif 794 795 #define CONFIG_MII /* MII PHY management */ 796 #define CONFIG_ETHPRIME "FM1@DTSEC4" 797 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 798 #endif 799 800 /* 801 * Environment 802 */ 803 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 804 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 805 806 /* 807 * Command line configuration. 808 */ 809 #ifdef CONFIG_T1042RDB_PI 810 #define CONFIG_CMD_DATE 811 #endif 812 #define CONFIG_CMD_ERRATA 813 #define CONFIG_CMD_IRQ 814 #define CONFIG_CMD_REGINFO 815 816 #ifdef CONFIG_PCI 817 #define CONFIG_CMD_PCI 818 #endif 819 820 /* Hash command with SHA acceleration supported in hardware */ 821 #ifdef CONFIG_FSL_CAAM 822 #define CONFIG_CMD_HASH 823 #define CONFIG_SHA_HW_ACCEL 824 #endif 825 826 /* 827 * Miscellaneous configurable options 828 */ 829 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 830 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 831 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 832 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 835 #else 836 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 837 #endif 838 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 839 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 840 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 841 842 /* 843 * For booting Linux, the board info and command line data 844 * have to be in the first 64 MB of memory, since this is 845 * the maximum mapped by the Linux kernel during initialization. 846 */ 847 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 848 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 849 850 #ifdef CONFIG_CMD_KGDB 851 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 852 #endif 853 854 /* 855 * Dynamic MTD Partition support with mtdparts 856 */ 857 #ifndef CONFIG_SYS_NO_FLASH 858 #define CONFIG_MTD_DEVICE 859 #define CONFIG_MTD_PARTITIONS 860 #define CONFIG_CMD_MTDPARTS 861 #define CONFIG_FLASH_CFI_MTD 862 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 863 "spi0=spife110000.0" 864 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 865 "128k(dtb),96m(fs),-(user);"\ 866 "fff800000.flash:2m(uboot),9m(kernel),"\ 867 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 868 "2m(uboot),9m(kernel),128k(dtb),-(user)" 869 #endif 870 871 /* 872 * Environment Configuration 873 */ 874 #define CONFIG_ROOTPATH "/opt/nfsroot" 875 #define CONFIG_BOOTFILE "uImage" 876 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 877 878 /* default location for tftp and bootm */ 879 #define CONFIG_LOADADDR 1000000 880 881 882 #define CONFIG_BAUDRATE 115200 883 884 #define __USB_PHY_TYPE utmi 885 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 886 887 #ifdef CONFIG_T1040RDB 888 #define FDTFILE "t1040rdb/t1040rdb.dtb" 889 #elif defined(CONFIG_T1042RDB_PI) 890 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 891 #elif defined(CONFIG_T1042RDB) 892 #define FDTFILE "t1042rdb/t1042rdb.dtb" 893 #elif defined(CONFIG_T1040D4RDB) 894 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 895 #elif defined(CONFIG_T1042D4RDB) 896 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 897 #endif 898 899 #ifdef CONFIG_FSL_DIU_FB 900 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 901 #else 902 #define DIU_ENVIRONMENT 903 #endif 904 905 #define CONFIG_EXTRA_ENV_SETTINGS \ 906 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 907 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 908 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 909 "netdev=eth0\0" \ 910 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 911 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 912 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 913 "tftpflash=tftpboot $loadaddr $uboot && " \ 914 "protect off $ubootaddr +$filesize && " \ 915 "erase $ubootaddr +$filesize && " \ 916 "cp.b $loadaddr $ubootaddr $filesize && " \ 917 "protect on $ubootaddr +$filesize && " \ 918 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 919 "consoledev=ttyS0\0" \ 920 "ramdiskaddr=2000000\0" \ 921 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 922 "fdtaddr=1e00000\0" \ 923 "fdtfile=" __stringify(FDTFILE) "\0" \ 924 "bdev=sda3\0" 925 926 #define CONFIG_LINUX \ 927 "setenv bootargs root=/dev/ram rw " \ 928 "console=$consoledev,$baudrate $othbootargs;" \ 929 "setenv ramdiskaddr 0x02000000;" \ 930 "setenv fdtaddr 0x00c00000;" \ 931 "setenv loadaddr 0x1000000;" \ 932 "bootm $loadaddr $ramdiskaddr $fdtaddr" 933 934 #define CONFIG_HDBOOT \ 935 "setenv bootargs root=/dev/$bdev rw " \ 936 "console=$consoledev,$baudrate $othbootargs;" \ 937 "tftp $loadaddr $bootfile;" \ 938 "tftp $fdtaddr $fdtfile;" \ 939 "bootm $loadaddr - $fdtaddr" 940 941 #define CONFIG_NFSBOOTCOMMAND \ 942 "setenv bootargs root=/dev/nfs rw " \ 943 "nfsroot=$serverip:$rootpath " \ 944 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 945 "console=$consoledev,$baudrate $othbootargs;" \ 946 "tftp $loadaddr $bootfile;" \ 947 "tftp $fdtaddr $fdtfile;" \ 948 "bootm $loadaddr - $fdtaddr" 949 950 #define CONFIG_RAMBOOTCOMMAND \ 951 "setenv bootargs root=/dev/ram rw " \ 952 "console=$consoledev,$baudrate $othbootargs;" \ 953 "tftp $ramdiskaddr $ramdiskfile;" \ 954 "tftp $loadaddr $bootfile;" \ 955 "tftp $fdtaddr $fdtfile;" \ 956 "bootm $loadaddr $ramdiskaddr $fdtaddr" 957 958 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 959 960 #include <asm/fsl_secure_boot.h> 961 962 #endif /* __CONFIG_H */ 963