1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * T104x RDB board configuration file 11 */ 12 #include <asm/config_mpc85xx.h> 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 16 #ifndef CONFIG_SECURE_BOOT 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #else 19 #define CONFIG_SYS_FSL_PBL_PBI \ 20 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 21 #endif 22 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_SPL_SKIP_RELOCATE 29 #define CONFIG_SPL_COMMON_INIT_DDR 30 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 31 #endif 32 #define RESET_VECTOR_OFFSET 0x27FFC 33 #define BOOT_PAGE_OFFSET 0x27000 34 35 #ifdef CONFIG_NAND 36 #ifdef CONFIG_SECURE_BOOT 37 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 38 /* 39 * HDR would be appended at end of image and copied to DDR along 40 * with U-Boot image. 41 */ 42 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 43 CONFIG_U_BOOT_HDR_SIZE) 44 #else 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #endif 47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 48 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 51 #ifdef CONFIG_TARGET_T1040RDB 52 #define CONFIG_SYS_FSL_PBL_RCW \ 53 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 54 #endif 55 #ifdef CONFIG_TARGET_T1042RDB_PI 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1040D4RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1042D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 70 #endif 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_SPI_FLASH_MINIMAL 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #ifdef CONFIG_TARGET_T1040RDB 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 88 #endif 89 #ifdef CONFIG_TARGET_T1042RDB_PI 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1040D4RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1042D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 104 #endif 105 #define CONFIG_SPL_SPI_BOOT 106 #endif 107 108 #ifdef CONFIG_SDCARD 109 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 110 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 111 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 112 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 113 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 114 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 115 #ifndef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 117 #endif 118 #ifdef CONFIG_TARGET_T1040RDB 119 #define CONFIG_SYS_FSL_PBL_RCW \ 120 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 121 #endif 122 #ifdef CONFIG_TARGET_T1042RDB_PI 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1040D4RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1042D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 137 #endif 138 #define CONFIG_SPL_MMC_BOOT 139 #endif 140 141 #endif 142 143 /* High Level Configuration Options */ 144 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 145 146 /* support deep sleep */ 147 #define CONFIG_DEEP_SLEEP 148 149 #ifndef CONFIG_RESET_VECTOR_ADDRESS 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 151 #endif 152 153 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 154 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 155 #define CONFIG_PCI_INDIRECT_BRIDGE 156 #define CONFIG_PCIE1 /* PCIE controller 1 */ 157 #define CONFIG_PCIE2 /* PCIE controller 2 */ 158 #define CONFIG_PCIE3 /* PCIE controller 3 */ 159 #define CONFIG_PCIE4 /* PCIE controller 4 */ 160 161 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 162 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 163 164 #define CONFIG_ENV_OVERWRITE 165 166 #ifdef CONFIG_MTD_NOR_FLASH 167 #define CONFIG_FLASH_CFI_DRIVER 168 #define CONFIG_SYS_FLASH_CFI 169 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 170 #endif 171 172 #if defined(CONFIG_SPIFLASH) 173 #define CONFIG_SYS_EXTRA_ENV_RELOC 174 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 175 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 176 #define CONFIG_ENV_SECT_SIZE 0x10000 177 #elif defined(CONFIG_SDCARD) 178 #define CONFIG_SYS_EXTRA_ENV_RELOC 179 #define CONFIG_SYS_MMC_ENV_DEV 0 180 #define CONFIG_ENV_SIZE 0x2000 181 #define CONFIG_ENV_OFFSET (512 * 0x800) 182 #elif defined(CONFIG_NAND) 183 #ifdef CONFIG_SECURE_BOOT 184 #define CONFIG_RAMBOOT_NAND 185 #define CONFIG_BOOTSCRIPT_COPY_RAM 186 #endif 187 #define CONFIG_SYS_EXTRA_ENV_RELOC 188 #define CONFIG_ENV_SIZE 0x2000 189 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 190 #else 191 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 192 #define CONFIG_ENV_SIZE 0x2000 193 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 194 #endif 195 196 #define CONFIG_SYS_CLK_FREQ 100000000 197 #define CONFIG_DDR_CLK_FREQ 66666666 198 199 /* 200 * These can be toggled for performance analysis, otherwise use default. 201 */ 202 #define CONFIG_SYS_CACHE_STASHING 203 #define CONFIG_BACKSIDE_L2_CACHE 204 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 205 #define CONFIG_BTB /* toggle branch predition */ 206 #define CONFIG_DDR_ECC 207 #ifdef CONFIG_DDR_ECC 208 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 209 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 210 #endif 211 212 #define CONFIG_ENABLE_36BIT_PHYS 213 214 #define CONFIG_ADDR_MAP 215 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 216 217 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 218 #define CONFIG_SYS_MEMTEST_END 0x00400000 219 220 /* 221 * Config the L3 Cache as L3 SRAM 222 */ 223 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 224 /* 225 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 226 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 227 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 228 */ 229 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 230 #define CONFIG_SYS_L3_SIZE 256 << 10 231 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 232 #ifdef CONFIG_RAMBOOT_PBL 233 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 234 #endif 235 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 236 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 237 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 238 239 #define CONFIG_SYS_DCSRBAR 0xf0000000 240 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 241 242 /* 243 * DDR Setup 244 */ 245 #define CONFIG_VERY_BIG_RAM 246 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 247 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 248 249 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 250 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 251 252 #define CONFIG_DDR_SPD 253 254 #define CONFIG_SYS_SPD_BUS_NUM 0 255 #define SPD_EEPROM_ADDRESS 0x51 256 257 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 258 259 /* 260 * IFC Definitions 261 */ 262 #define CONFIG_SYS_FLASH_BASE 0xe8000000 263 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 264 265 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 266 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 267 CSPR_PORT_SIZE_16 | \ 268 CSPR_MSEL_NOR | \ 269 CSPR_V) 270 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 271 272 /* 273 * TDM Definition 274 */ 275 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 276 277 /* NOR Flash Timing Params */ 278 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 279 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 280 FTIM0_NOR_TEADC(0x5) | \ 281 FTIM0_NOR_TEAHC(0x5)) 282 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 283 FTIM1_NOR_TRAD_NOR(0x1A) |\ 284 FTIM1_NOR_TSEQRAD_NOR(0x13)) 285 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 286 FTIM2_NOR_TCH(0x4) | \ 287 FTIM2_NOR_TWPH(0x0E) | \ 288 FTIM2_NOR_TWP(0x1c)) 289 #define CONFIG_SYS_NOR_FTIM3 0x0 290 291 #define CONFIG_SYS_FLASH_QUIET_TEST 292 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 293 294 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 295 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 296 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 297 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 298 299 #define CONFIG_SYS_FLASH_EMPTY_INFO 300 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 301 302 /* CPLD on IFC */ 303 #define CPLD_LBMAP_MASK 0x3F 304 #define CPLD_BANK_SEL_MASK 0x07 305 #define CPLD_BANK_OVERRIDE 0x40 306 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 307 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 308 #define CPLD_LBMAP_RESET 0xFF 309 #define CPLD_LBMAP_SHIFT 0x03 310 311 #if defined(CONFIG_TARGET_T1042RDB_PI) 312 #define CPLD_DIU_SEL_DFP 0x80 313 #elif defined(CONFIG_TARGET_T1042D4RDB) 314 #define CPLD_DIU_SEL_DFP 0xc0 315 #endif 316 317 #if defined(CONFIG_TARGET_T1040D4RDB) 318 #define CPLD_INT_MASK_ALL 0xFF 319 #define CPLD_INT_MASK_THERM 0x80 320 #define CPLD_INT_MASK_DVI_DFP 0x40 321 #define CPLD_INT_MASK_QSGMII1 0x20 322 #define CPLD_INT_MASK_QSGMII2 0x10 323 #define CPLD_INT_MASK_SGMI1 0x08 324 #define CPLD_INT_MASK_SGMI2 0x04 325 #define CPLD_INT_MASK_TDMR1 0x02 326 #define CPLD_INT_MASK_TDMR2 0x01 327 #endif 328 329 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 330 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 331 #define CONFIG_SYS_CSPR2_EXT (0xf) 332 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 333 | CSPR_PORT_SIZE_8 \ 334 | CSPR_MSEL_GPCM \ 335 | CSPR_V) 336 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 337 #define CONFIG_SYS_CSOR2 0x0 338 /* CPLD Timing parameters for IFC CS2 */ 339 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 340 FTIM0_GPCM_TEADC(0x0e) | \ 341 FTIM0_GPCM_TEAHC(0x0e)) 342 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 343 FTIM1_GPCM_TRAD(0x1f)) 344 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 345 FTIM2_GPCM_TCH(0x8) | \ 346 FTIM2_GPCM_TWP(0x1f)) 347 #define CONFIG_SYS_CS2_FTIM3 0x0 348 349 /* NAND Flash on IFC */ 350 #define CONFIG_NAND_FSL_IFC 351 #define CONFIG_SYS_NAND_BASE 0xff800000 352 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 353 354 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 355 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 356 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 357 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 358 | CSPR_V) 359 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 360 361 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 364 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 365 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 366 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 367 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 368 369 #define CONFIG_SYS_NAND_ONFI_DETECTION 370 371 /* ONFI NAND Flash mode0 Timing Params */ 372 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 373 FTIM0_NAND_TWP(0x18) | \ 374 FTIM0_NAND_TWCHT(0x07) | \ 375 FTIM0_NAND_TWH(0x0a)) 376 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 377 FTIM1_NAND_TWBE(0x39) | \ 378 FTIM1_NAND_TRR(0x0e) | \ 379 FTIM1_NAND_TRP(0x18)) 380 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 381 FTIM2_NAND_TREH(0x0a) | \ 382 FTIM2_NAND_TWHRE(0x1e)) 383 #define CONFIG_SYS_NAND_FTIM3 0x0 384 385 #define CONFIG_SYS_NAND_DDR_LAW 11 386 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 387 #define CONFIG_SYS_MAX_NAND_DEVICE 1 388 389 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 390 391 #if defined(CONFIG_NAND) 392 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 393 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 394 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 395 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 396 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 397 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 398 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 399 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 400 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 401 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 402 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 403 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 404 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 405 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 406 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 407 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 408 #else 409 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 410 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 411 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 412 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 413 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 414 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 415 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 416 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 417 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 418 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 419 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 420 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 421 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 422 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 423 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 424 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 425 #endif 426 427 #ifdef CONFIG_SPL_BUILD 428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 429 #else 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 431 #endif 432 433 #if defined(CONFIG_RAMBOOT_PBL) 434 #define CONFIG_SYS_RAMBOOT 435 #endif 436 437 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 438 #if defined(CONFIG_NAND) 439 #define CONFIG_A008044_WORKAROUND 440 #endif 441 #endif 442 443 #define CONFIG_MISC_INIT_R 444 445 #define CONFIG_HWCONFIG 446 447 /* define to use L1 as initial stack */ 448 #define CONFIG_L1_INIT_RAM 449 #define CONFIG_SYS_INIT_RAM_LOCK 450 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 453 /* The assembler doesn't like typecast */ 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 455 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 456 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 457 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 458 459 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 460 GENERATED_GBL_DATA_SIZE) 461 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 462 463 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 464 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 465 466 /* Serial Port - controlled on board with jumper J8 467 * open - index 2 468 * shorted - index 1 469 */ 470 #define CONFIG_SYS_NS16550_SERIAL 471 #define CONFIG_SYS_NS16550_REG_SIZE 1 472 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 473 474 #define CONFIG_SYS_BAUDRATE_TABLE \ 475 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 476 477 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 478 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 479 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 480 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 481 482 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 483 /* Video */ 484 #define CONFIG_FSL_DIU_FB 485 486 #ifdef CONFIG_FSL_DIU_FB 487 #define CONFIG_FSL_DIU_CH7301 488 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 489 #define CONFIG_VIDEO_LOGO 490 #define CONFIG_VIDEO_BMP_LOGO 491 #endif 492 #endif 493 494 /* I2C */ 495 #define CONFIG_SYS_I2C 496 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 497 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 498 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 499 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 500 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 501 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 502 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 503 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 504 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 505 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 506 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 507 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 508 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 509 510 /* I2C bus multiplexer */ 511 #define I2C_MUX_PCA_ADDR 0x70 512 #define I2C_MUX_CH_DEFAULT 0x8 513 514 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 515 defined(CONFIG_TARGET_T1040D4RDB) || \ 516 defined(CONFIG_TARGET_T1042D4RDB) 517 /* LDI/DVI Encoder for display */ 518 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 519 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 520 521 /* 522 * RTC configuration 523 */ 524 #define RTC 525 #define CONFIG_RTC_DS1337 1 526 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 527 528 /*DVI encoder*/ 529 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 530 #endif 531 532 /* 533 * eSPI - Enhanced SPI 534 */ 535 #define CONFIG_SPI_FLASH_BAR 536 #define CONFIG_SF_DEFAULT_SPEED 10000000 537 #define CONFIG_SF_DEFAULT_MODE 0 538 #define CONFIG_ENV_SPI_BUS 0 539 #define CONFIG_ENV_SPI_CS 0 540 #define CONFIG_ENV_SPI_MAX_HZ 10000000 541 #define CONFIG_ENV_SPI_MODE 0 542 543 /* 544 * General PCI 545 * Memory space is mapped 1-1, but I/O space must start from 0. 546 */ 547 548 #ifdef CONFIG_PCI 549 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 550 #ifdef CONFIG_PCIE1 551 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 552 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 553 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 554 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 555 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 556 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 557 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 558 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 559 #endif 560 561 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 562 #ifdef CONFIG_PCIE2 563 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 564 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 566 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 568 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 569 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 570 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 571 #endif 572 573 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 574 #ifdef CONFIG_PCIE3 575 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 576 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 577 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 578 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 579 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 580 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 581 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 582 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 583 #endif 584 585 /* controller 4, Base address 203000 */ 586 #ifdef CONFIG_PCIE4 587 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 588 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 589 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 590 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 591 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 592 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 593 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 594 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 595 #endif 596 597 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 598 #endif /* CONFIG_PCI */ 599 600 /* SATA */ 601 #define CONFIG_FSL_SATA_V2 602 #ifdef CONFIG_FSL_SATA_V2 603 #define CONFIG_SYS_SATA_MAX_DEVICE 1 604 #define CONFIG_SATA1 605 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 606 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 607 608 #define CONFIG_LBA48 609 #endif 610 611 /* 612 * USB 613 */ 614 #define CONFIG_HAS_FSL_DR_USB 615 616 #ifdef CONFIG_HAS_FSL_DR_USB 617 #ifdef CONFIG_USB_EHCI_HCD 618 #define CONFIG_USB_EHCI_FSL 619 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 620 #define CONFIG_EHCI_DESC_BIG_ENDIAN 621 #endif 622 #endif 623 624 #ifdef CONFIG_MMC 625 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 626 #endif 627 628 /* Qman/Bman */ 629 #ifndef CONFIG_NOBQFMAN 630 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 631 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 632 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 633 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 634 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 635 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 636 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 637 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 638 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 639 CONFIG_SYS_BMAN_CENA_SIZE) 640 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 642 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 643 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 644 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 645 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 646 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 647 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 648 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 649 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 650 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 651 CONFIG_SYS_QMAN_CENA_SIZE) 652 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 653 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 654 655 #define CONFIG_SYS_DPAA_FMAN 656 #define CONFIG_SYS_DPAA_PME 657 658 #define CONFIG_QE 659 #define CONFIG_U_QE 660 661 /* Default address of microcode for the Linux Fman driver */ 662 #if defined(CONFIG_SPIFLASH) 663 /* 664 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 665 * env, so we got 0x110000. 666 */ 667 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 668 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 669 #elif defined(CONFIG_SDCARD) 670 /* 671 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 672 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 673 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 674 */ 675 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 676 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 677 #elif defined(CONFIG_NAND) 678 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 679 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 680 #else 681 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 682 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 683 #endif 684 685 #if defined(CONFIG_SPIFLASH) 686 #define CONFIG_SYS_QE_FW_ADDR 0x130000 687 #elif defined(CONFIG_SDCARD) 688 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 689 #elif defined(CONFIG_NAND) 690 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 691 #else 692 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 693 #endif 694 695 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 696 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 697 #endif /* CONFIG_NOBQFMAN */ 698 699 #ifdef CONFIG_SYS_DPAA_FMAN 700 #define CONFIG_FMAN_ENET 701 #define CONFIG_PHY_VITESSE 702 #define CONFIG_PHY_REALTEK 703 #endif 704 705 #ifdef CONFIG_FMAN_ENET 706 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 707 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 708 #elif defined(CONFIG_TARGET_T1040D4RDB) 709 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 710 #elif defined(CONFIG_TARGET_T1042D4RDB) 711 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 712 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 713 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 714 #endif 715 716 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 717 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 718 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 719 #else 720 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 721 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 722 #endif 723 724 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 725 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 726 #define CONFIG_VSC9953 727 #ifdef CONFIG_TARGET_T1040RDB 728 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 729 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 730 #else 731 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 732 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 733 #endif 734 #endif 735 736 #define CONFIG_MII /* MII PHY management */ 737 #define CONFIG_ETHPRIME "FM1@DTSEC4" 738 #endif 739 740 /* 741 * Environment 742 */ 743 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 744 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 745 746 /* 747 * Miscellaneous configurable options 748 */ 749 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 750 751 /* 752 * For booting Linux, the board info and command line data 753 * have to be in the first 64 MB of memory, since this is 754 * the maximum mapped by the Linux kernel during initialization. 755 */ 756 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 757 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 758 759 #ifdef CONFIG_CMD_KGDB 760 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 761 #endif 762 763 /* 764 * Dynamic MTD Partition support with mtdparts 765 */ 766 #ifdef CONFIG_MTD_NOR_FLASH 767 #define CONFIG_FLASH_CFI_MTD 768 #endif 769 770 /* 771 * Environment Configuration 772 */ 773 #define CONFIG_ROOTPATH "/opt/nfsroot" 774 #define CONFIG_BOOTFILE "uImage" 775 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 776 777 /* default location for tftp and bootm */ 778 #define CONFIG_LOADADDR 1000000 779 780 #define __USB_PHY_TYPE utmi 781 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 782 783 #ifdef CONFIG_TARGET_T1040RDB 784 #define FDTFILE "t1040rdb/t1040rdb.dtb" 785 #elif defined(CONFIG_TARGET_T1042RDB_PI) 786 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 787 #elif defined(CONFIG_TARGET_T1042RDB) 788 #define FDTFILE "t1042rdb/t1042rdb.dtb" 789 #elif defined(CONFIG_TARGET_T1040D4RDB) 790 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 791 #elif defined(CONFIG_TARGET_T1042D4RDB) 792 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 793 #endif 794 795 #ifdef CONFIG_FSL_DIU_FB 796 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 797 #else 798 #define DIU_ENVIRONMENT 799 #endif 800 801 #define CONFIG_EXTRA_ENV_SETTINGS \ 802 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 803 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 804 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 805 "netdev=eth0\0" \ 806 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 807 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 808 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 809 "tftpflash=tftpboot $loadaddr $uboot && " \ 810 "protect off $ubootaddr +$filesize && " \ 811 "erase $ubootaddr +$filesize && " \ 812 "cp.b $loadaddr $ubootaddr $filesize && " \ 813 "protect on $ubootaddr +$filesize && " \ 814 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 815 "consoledev=ttyS0\0" \ 816 "ramdiskaddr=2000000\0" \ 817 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 818 "fdtaddr=1e00000\0" \ 819 "fdtfile=" __stringify(FDTFILE) "\0" \ 820 "bdev=sda3\0" 821 822 #define CONFIG_LINUX \ 823 "setenv bootargs root=/dev/ram rw " \ 824 "console=$consoledev,$baudrate $othbootargs;" \ 825 "setenv ramdiskaddr 0x02000000;" \ 826 "setenv fdtaddr 0x00c00000;" \ 827 "setenv loadaddr 0x1000000;" \ 828 "bootm $loadaddr $ramdiskaddr $fdtaddr" 829 830 #define CONFIG_HDBOOT \ 831 "setenv bootargs root=/dev/$bdev rw " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "tftp $loadaddr $bootfile;" \ 834 "tftp $fdtaddr $fdtfile;" \ 835 "bootm $loadaddr - $fdtaddr" 836 837 #define CONFIG_NFSBOOTCOMMAND \ 838 "setenv bootargs root=/dev/nfs rw " \ 839 "nfsroot=$serverip:$rootpath " \ 840 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 841 "console=$consoledev,$baudrate $othbootargs;" \ 842 "tftp $loadaddr $bootfile;" \ 843 "tftp $fdtaddr $fdtfile;" \ 844 "bootm $loadaddr - $fdtaddr" 845 846 #define CONFIG_RAMBOOTCOMMAND \ 847 "setenv bootargs root=/dev/ram rw " \ 848 "console=$consoledev,$baudrate $othbootargs;" \ 849 "tftp $ramdiskaddr $ramdiskfile;" \ 850 "tftp $loadaddr $bootfile;" \ 851 "tftp $fdtaddr $fdtfile;" \ 852 "bootm $loadaddr $ramdiskaddr $fdtaddr" 853 854 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 855 856 #include <asm/fsl_secure_boot.h> 857 858 #endif /* __CONFIG_H */ 859