1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 #define CONFIG_PHYS_64BIT 31 #define CONFIG_SYS_GENERIC_BOARD 32 #define CONFIG_DISPLAY_BOARDINFO 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 38 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 43 #define CONFIG_E500 /* BOOKE e500 family */ 44 #define CONFIG_E500MC /* BOOKE e500mc family */ 45 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 /* support deep sleep */ 49 #define CONFIG_DEEP_SLEEP 50 #if defined(CONFIG_DEEP_SLEEP) 51 #define CONFIG_SILENT_CONSOLE 52 #define CONFIG_BOARD_EARLY_INIT_F 53 #endif 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xeff40000 57 #endif 58 59 #ifndef CONFIG_RESET_VECTOR_ADDRESS 60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 61 #endif 62 63 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 64 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 65 #define CONFIG_FSL_IFC /* Enable IFC Support */ 66 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 67 #define CONFIG_PCI /* Enable PCI/PCIE */ 68 #define CONFIG_PCI_INDIRECT_BRIDGE 69 #define CONFIG_PCIE1 /* PCIE controler 1 */ 70 #define CONFIG_PCIE2 /* PCIE controler 2 */ 71 #define CONFIG_PCIE3 /* PCIE controler 3 */ 72 #define CONFIG_PCIE4 /* PCIE controler 4 */ 73 74 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 75 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 76 77 #define CONFIG_FSL_LAW /* Use common FSL init code */ 78 79 #define CONFIG_ENV_OVERWRITE 80 81 #ifdef CONFIG_SYS_NO_FLASH 82 #define CONFIG_ENV_IS_NOWHERE 83 #else 84 #define CONFIG_FLASH_CFI_DRIVER 85 #define CONFIG_SYS_FLASH_CFI 86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 87 #endif 88 89 #ifndef CONFIG_SYS_NO_FLASH 90 #if defined(CONFIG_SPIFLASH) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_SPI_FLASH 93 #define CONFIG_ENV_SPI_BUS 0 94 #define CONFIG_ENV_SPI_CS 0 95 #define CONFIG_ENV_SPI_MAX_HZ 10000000 96 #define CONFIG_ENV_SPI_MODE 0 97 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 98 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 99 #define CONFIG_ENV_SECT_SIZE 0x10000 100 #elif defined(CONFIG_SDCARD) 101 #define CONFIG_SYS_EXTRA_ENV_RELOC 102 #define CONFIG_ENV_IS_IN_MMC 103 #define CONFIG_SYS_MMC_ENV_DEV 0 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_OFFSET (512 * 1658) 106 #elif defined(CONFIG_NAND) 107 #define CONFIG_SYS_EXTRA_ENV_RELOC 108 #define CONFIG_ENV_IS_IN_NAND 109 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 110 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 111 #else 112 #define CONFIG_ENV_IS_IN_FLASH 113 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 116 #endif 117 #else /* CONFIG_SYS_NO_FLASH */ 118 #define CONFIG_ENV_SIZE 0x2000 119 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 120 #endif 121 122 #ifndef __ASSEMBLY__ 123 unsigned long get_board_sys_clk(void); 124 unsigned long get_board_ddr_clk(void); 125 #endif 126 127 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 128 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 129 130 /* 131 * These can be toggled for performance analysis, otherwise use default. 132 */ 133 #define CONFIG_SYS_CACHE_STASHING 134 #define CONFIG_BACKSIDE_L2_CACHE 135 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 136 #define CONFIG_BTB /* toggle branch predition */ 137 #define CONFIG_DDR_ECC 138 #ifdef CONFIG_DDR_ECC 139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 140 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 141 #endif 142 143 #define CONFIG_ENABLE_36BIT_PHYS 144 145 #define CONFIG_ADDR_MAP 146 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 147 148 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 149 #define CONFIG_SYS_MEMTEST_END 0x00400000 150 #define CONFIG_SYS_ALT_MEMTEST 151 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 152 153 /* 154 * Config the L3 Cache as L3 SRAM 155 */ 156 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 157 158 #define CONFIG_SYS_DCSRBAR 0xf0000000 159 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 160 161 /* EEPROM */ 162 #define CONFIG_ID_EEPROM 163 #define CONFIG_SYS_I2C_EEPROM_NXID 164 #define CONFIG_SYS_EEPROM_BUS_NUM 0 165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 169 170 /* 171 * DDR Setup 172 */ 173 #define CONFIG_VERY_BIG_RAM 174 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 175 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 176 177 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 178 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 179 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 180 181 #define CONFIG_DDR_SPD 182 #ifndef CONFIG_SYS_FSL_DDR4 183 #define CONFIG_SYS_FSL_DDR3 184 #endif 185 #define CONFIG_FSL_DDR_INTERACTIVE 186 187 #define CONFIG_SYS_SPD_BUS_NUM 0 188 #define SPD_EEPROM_ADDRESS 0x51 189 190 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 191 192 /* 193 * IFC Definitions 194 */ 195 #define CONFIG_SYS_FLASH_BASE 0xe0000000 196 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 197 198 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 199 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 200 + 0x8000000) | \ 201 CSPR_PORT_SIZE_16 | \ 202 CSPR_MSEL_NOR | \ 203 CSPR_V) 204 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 205 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 206 CSPR_PORT_SIZE_16 | \ 207 CSPR_MSEL_NOR | \ 208 CSPR_V) 209 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 210 211 /* 212 * TDM Definition 213 */ 214 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 215 216 /* NOR Flash Timing Params */ 217 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 218 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 219 FTIM0_NOR_TEADC(0x5) | \ 220 FTIM0_NOR_TEAHC(0x5)) 221 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 222 FTIM1_NOR_TRAD_NOR(0x1A) |\ 223 FTIM1_NOR_TSEQRAD_NOR(0x13)) 224 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 225 FTIM2_NOR_TCH(0x4) | \ 226 FTIM2_NOR_TWPH(0x0E) | \ 227 FTIM2_NOR_TWP(0x1c)) 228 #define CONFIG_SYS_NOR_FTIM3 0x0 229 230 #define CONFIG_SYS_FLASH_QUIET_TEST 231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 232 233 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 234 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237 238 #define CONFIG_SYS_FLASH_EMPTY_INFO 239 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 240 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 241 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 242 #define QIXIS_BASE 0xffdf0000 243 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 244 #define QIXIS_LBMAP_SWITCH 0x06 245 #define QIXIS_LBMAP_MASK 0x0f 246 #define QIXIS_LBMAP_SHIFT 0 247 #define QIXIS_LBMAP_DFLTBANK 0x00 248 #define QIXIS_LBMAP_ALTBANK 0x04 249 #define QIXIS_RST_CTL_RESET 0x31 250 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 251 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 252 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 253 #define QIXIS_RST_FORCE_MEM 0x01 254 255 #define CONFIG_SYS_CSPR3_EXT (0xf) 256 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 257 | CSPR_PORT_SIZE_8 \ 258 | CSPR_MSEL_GPCM \ 259 | CSPR_V) 260 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 261 #define CONFIG_SYS_CSOR3 0x0 262 /* QIXIS Timing parameters for IFC CS3 */ 263 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 264 FTIM0_GPCM_TEADC(0x0e) | \ 265 FTIM0_GPCM_TEAHC(0x0e)) 266 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 267 FTIM1_GPCM_TRAD(0x3f)) 268 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 269 FTIM2_GPCM_TCH(0x8) | \ 270 FTIM2_GPCM_TWP(0x1f)) 271 #define CONFIG_SYS_CS3_FTIM3 0x0 272 273 #define CONFIG_NAND_FSL_IFC 274 #define CONFIG_SYS_NAND_BASE 0xff800000 275 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 276 277 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 278 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 279 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 280 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 281 | CSPR_V) 282 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 283 284 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 285 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 286 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 287 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 288 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 289 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 290 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 291 292 #define CONFIG_SYS_NAND_ONFI_DETECTION 293 294 /* ONFI NAND Flash mode0 Timing Params */ 295 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 296 FTIM0_NAND_TWP(0x18) | \ 297 FTIM0_NAND_TWCHT(0x07) | \ 298 FTIM0_NAND_TWH(0x0a)) 299 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 300 FTIM1_NAND_TWBE(0x39) | \ 301 FTIM1_NAND_TRR(0x0e) | \ 302 FTIM1_NAND_TRP(0x18)) 303 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 304 FTIM2_NAND_TREH(0x0a) | \ 305 FTIM2_NAND_TWHRE(0x1e)) 306 #define CONFIG_SYS_NAND_FTIM3 0x0 307 308 #define CONFIG_SYS_NAND_DDR_LAW 11 309 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 310 #define CONFIG_SYS_MAX_NAND_DEVICE 1 311 #define CONFIG_MTD_NAND_VERIFY_WRITE 312 #define CONFIG_CMD_NAND 313 314 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 315 316 #if defined(CONFIG_NAND) 317 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 318 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 319 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 320 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 321 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 322 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 323 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 324 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 325 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 326 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 327 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 328 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 329 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 330 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 331 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 332 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 333 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 334 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 335 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #else 342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 351 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 352 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 353 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 354 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 355 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 356 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 357 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 358 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 359 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 360 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 361 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 362 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 363 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 364 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 365 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 366 #endif 367 368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 369 370 #if defined(CONFIG_RAMBOOT_PBL) 371 #define CONFIG_SYS_RAMBOOT 372 #endif 373 374 #define CONFIG_BOARD_EARLY_INIT_R 375 #define CONFIG_MISC_INIT_R 376 377 #define CONFIG_HWCONFIG 378 379 /* define to use L1 as initial stack */ 380 #define CONFIG_L1_INIT_RAM 381 #define CONFIG_SYS_INIT_RAM_LOCK 382 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 385 /* The assembler doesn't like typecast */ 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 387 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 388 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 389 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 390 391 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 392 GENERATED_GBL_DATA_SIZE) 393 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 394 395 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 396 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 397 398 /* Serial Port - controlled on board with jumper J8 399 * open - index 2 400 * shorted - index 1 401 */ 402 #define CONFIG_CONS_INDEX 1 403 #define CONFIG_SYS_NS16550 404 #define CONFIG_SYS_NS16550_SERIAL 405 #define CONFIG_SYS_NS16550_REG_SIZE 1 406 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 407 408 #define CONFIG_SYS_BAUDRATE_TABLE \ 409 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 410 411 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 412 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 413 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 414 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 415 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 416 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 417 418 /* Use the HUSH parser */ 419 #define CONFIG_SYS_HUSH_PARSER 420 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 421 422 /* Video */ 423 #define CONFIG_FSL_DIU_FB 424 #ifdef CONFIG_FSL_DIU_FB 425 #define CONFIG_FSL_DIU_CH7301 426 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 427 #define CONFIG_VIDEO 428 #define CONFIG_CMD_BMP 429 #define CONFIG_CFB_CONSOLE 430 #define CONFIG_VIDEO_SW_CURSOR 431 #define CONFIG_VGA_AS_SINGLE_DEVICE 432 #define CONFIG_VIDEO_LOGO 433 #define CONFIG_VIDEO_BMP_LOGO 434 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 435 /* 436 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 437 * disable empty flash sector detection, which is I/O-intensive. 438 */ 439 #undef CONFIG_SYS_FLASH_EMPTY_INFO 440 #endif 441 442 /* pass open firmware flat tree */ 443 #define CONFIG_OF_LIBFDT 444 #define CONFIG_OF_BOARD_SETUP 445 #define CONFIG_OF_STDOUT_VIA_ALIAS 446 447 /* new uImage format support */ 448 #define CONFIG_FIT 449 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 450 451 /* I2C */ 452 #define CONFIG_SYS_I2C 453 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 454 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 455 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 456 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 457 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 458 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 460 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 461 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 462 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 463 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 464 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 465 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 466 467 #define I2C_MUX_PCA_ADDR 0x77 468 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 469 470 471 /* I2C bus multiplexer */ 472 #define I2C_MUX_CH_DEFAULT 0x8 473 #define I2C_MUX_CH_DIU 0xC 474 475 /* LDI/DVI Encoder for display */ 476 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 477 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 478 479 /* 480 * RTC configuration 481 */ 482 #define RTC 483 #define CONFIG_RTC_DS3231 1 484 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 485 486 /* 487 * eSPI - Enhanced SPI 488 */ 489 #define CONFIG_FSL_ESPI 490 #define CONFIG_SPI_FLASH 491 #define CONFIG_SPI_FLASH_STMICRO 492 #define CONFIG_SPI_FLASH_SST 493 #define CONFIG_SPI_FLASH_EON 494 #define CONFIG_CMD_SF 495 #define CONFIG_SF_DEFAULT_SPEED 10000000 496 #define CONFIG_SF_DEFAULT_MODE 0 497 498 /* 499 * General PCI 500 * Memory space is mapped 1-1, but I/O space must start from 0. 501 */ 502 503 #ifdef CONFIG_PCI 504 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 505 #ifdef CONFIG_PCIE1 506 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 507 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 508 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 509 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 510 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 511 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 512 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 513 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 514 #endif 515 516 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 517 #ifdef CONFIG_PCIE2 518 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 519 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 520 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 521 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 522 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 523 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 525 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 526 #endif 527 528 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 529 #ifdef CONFIG_PCIE3 530 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 531 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 532 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 533 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 534 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 535 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 536 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 537 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 538 #endif 539 540 /* controller 4, Base address 203000 */ 541 #ifdef CONFIG_PCIE4 542 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 543 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 544 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 545 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 546 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 547 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 548 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 549 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 550 #endif 551 552 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 553 #define CONFIG_E1000 554 555 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 556 #define CONFIG_DOS_PARTITION 557 #endif /* CONFIG_PCI */ 558 559 /* SATA */ 560 #define CONFIG_FSL_SATA_V2 561 #ifdef CONFIG_FSL_SATA_V2 562 #define CONFIG_LIBATA 563 #define CONFIG_FSL_SATA 564 565 #define CONFIG_SYS_SATA_MAX_DEVICE 2 566 #define CONFIG_SATA1 567 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 568 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 569 #define CONFIG_SATA2 570 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 571 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 572 573 #define CONFIG_LBA48 574 #define CONFIG_CMD_SATA 575 #define CONFIG_DOS_PARTITION 576 #define CONFIG_CMD_EXT2 577 #endif 578 579 /* 580 * USB 581 */ 582 #define CONFIG_HAS_FSL_DR_USB 583 584 #ifdef CONFIG_HAS_FSL_DR_USB 585 #define CONFIG_USB_EHCI 586 587 #ifdef CONFIG_USB_EHCI 588 #define CONFIG_CMD_USB 589 #define CONFIG_USB_STORAGE 590 #define CONFIG_USB_EHCI_FSL 591 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 592 #define CONFIG_CMD_EXT2 593 #endif 594 #endif 595 596 #define CONFIG_MMC 597 598 #ifdef CONFIG_MMC 599 #define CONFIG_FSL_ESDHC 600 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 601 #define CONFIG_CMD_MMC 602 #define CONFIG_GENERIC_MMC 603 #define CONFIG_CMD_EXT2 604 #define CONFIG_CMD_FAT 605 #define CONFIG_DOS_PARTITION 606 #endif 607 608 /* Qman/Bman */ 609 #ifndef CONFIG_NOBQFMAN 610 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 611 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 612 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 613 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 614 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 615 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 616 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 617 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 618 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 620 CONFIG_SYS_BMAN_CENA_SIZE) 621 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 623 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 624 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 625 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 626 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 627 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 628 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 629 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 630 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 631 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 632 CONFIG_SYS_QMAN_CENA_SIZE) 633 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 634 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 635 636 #define CONFIG_SYS_DPAA_FMAN 637 #define CONFIG_SYS_DPAA_PME 638 639 #define CONFIG_QE 640 #define CONFIG_U_QE 641 /* Default address of microcode for the Linux Fman driver */ 642 #if defined(CONFIG_SPIFLASH) 643 /* 644 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 645 * env, so we got 0x110000. 646 */ 647 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 648 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 649 #elif defined(CONFIG_SDCARD) 650 /* 651 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 652 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 653 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 654 */ 655 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 656 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 657 #elif defined(CONFIG_NAND) 658 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 659 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 660 #else 661 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 662 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 663 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 664 #endif 665 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 666 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 667 #endif /* CONFIG_NOBQFMAN */ 668 669 #ifdef CONFIG_SYS_DPAA_FMAN 670 #define CONFIG_FMAN_ENET 671 #define CONFIG_PHYLIB_10G 672 #define CONFIG_PHY_VITESSE 673 #define CONFIG_PHY_REALTEK 674 #define CONFIG_PHY_TERANETICS 675 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 676 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 677 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 678 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 679 #endif 680 681 #ifdef CONFIG_FMAN_ENET 682 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 683 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 684 685 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 686 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 687 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 688 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 689 690 #define CONFIG_MII /* MII PHY management */ 691 #define CONFIG_ETHPRIME "FM1@DTSEC1" 692 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 693 #endif 694 695 /* Enable VSC9953 L2 Switch driver */ 696 #define CONFIG_VSC9953 697 #define CONFIG_VSC9953_CMD 698 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 699 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 700 701 /* 702 * Dynamic MTD Partition support with mtdparts 703 */ 704 #ifndef CONFIG_SYS_NO_FLASH 705 #define CONFIG_MTD_DEVICE 706 #define CONFIG_MTD_PARTITIONS 707 #define CONFIG_CMD_MTDPARTS 708 #define CONFIG_FLASH_CFI_MTD 709 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 710 "spi0=spife110000.0" 711 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 712 "128k(dtb),96m(fs),-(user);"\ 713 "fff800000.flash:2m(uboot),9m(kernel),"\ 714 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 715 "2m(uboot),9m(kernel),128k(dtb),-(user)" 716 #endif 717 718 /* 719 * Environment 720 */ 721 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 722 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 723 724 /* 725 * Command line configuration. 726 */ 727 #include <config_cmd_default.h> 728 729 #define CONFIG_CMD_DATE 730 #define CONFIG_CMD_DHCP 731 #define CONFIG_CMD_EEPROM 732 #define CONFIG_CMD_ELF 733 #define CONFIG_CMD_ERRATA 734 #define CONFIG_CMD_GREPENV 735 #define CONFIG_CMD_IRQ 736 #define CONFIG_CMD_I2C 737 #define CONFIG_CMD_MII 738 #define CONFIG_CMD_PING 739 #define CONFIG_CMD_REGINFO 740 #define CONFIG_CMD_SETEXPR 741 742 #ifdef CONFIG_PCI 743 #define CONFIG_CMD_PCI 744 #define CONFIG_CMD_NET 745 #endif 746 747 /* Hash command with SHA acceleration supported in hardware */ 748 #ifdef CONFIG_FSL_CAAM 749 #define CONFIG_CMD_HASH 750 #define CONFIG_SHA_HW_ACCEL 751 #endif 752 753 /* 754 * Miscellaneous configurable options 755 */ 756 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 757 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 758 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 759 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 760 #ifdef CONFIG_CMD_KGDB 761 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 762 #else 763 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 764 #endif 765 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 766 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 767 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 768 769 /* 770 * For booting Linux, the board info and command line data 771 * have to be in the first 64 MB of memory, since this is 772 * the maximum mapped by the Linux kernel during initialization. 773 */ 774 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 775 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 776 777 #ifdef CONFIG_CMD_KGDB 778 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 779 #endif 780 781 /* 782 * Environment Configuration 783 */ 784 #define CONFIG_ROOTPATH "/opt/nfsroot" 785 #define CONFIG_BOOTFILE "uImage" 786 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 787 788 /* default location for tftp and bootm */ 789 #define CONFIG_LOADADDR 1000000 790 791 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 792 793 #define CONFIG_BAUDRATE 115200 794 795 #define __USB_PHY_TYPE utmi 796 797 #define CONFIG_EXTRA_ENV_SETTINGS \ 798 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 799 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 800 "netdev=eth0\0" \ 801 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 802 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 803 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 804 "tftpflash=tftpboot $loadaddr $uboot && " \ 805 "protect off $ubootaddr +$filesize && " \ 806 "erase $ubootaddr +$filesize && " \ 807 "cp.b $loadaddr $ubootaddr $filesize && " \ 808 "protect on $ubootaddr +$filesize && " \ 809 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 810 "consoledev=ttyS0\0" \ 811 "ramdiskaddr=2000000\0" \ 812 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 813 "fdtaddr=c00000\0" \ 814 "fdtfile=t1040qds/t1040qds.dtb\0" \ 815 "bdev=sda3\0" 816 817 #define CONFIG_LINUX \ 818 "setenv bootargs root=/dev/ram rw " \ 819 "console=$consoledev,$baudrate $othbootargs;" \ 820 "setenv ramdiskaddr 0x02000000;" \ 821 "setenv fdtaddr 0x00c00000;" \ 822 "setenv loadaddr 0x1000000;" \ 823 "bootm $loadaddr $ramdiskaddr $fdtaddr" 824 825 #define CONFIG_HDBOOT \ 826 "setenv bootargs root=/dev/$bdev rw " \ 827 "console=$consoledev,$baudrate $othbootargs;" \ 828 "tftp $loadaddr $bootfile;" \ 829 "tftp $fdtaddr $fdtfile;" \ 830 "bootm $loadaddr - $fdtaddr" 831 832 #define CONFIG_NFSBOOTCOMMAND \ 833 "setenv bootargs root=/dev/nfs rw " \ 834 "nfsroot=$serverip:$rootpath " \ 835 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 836 "console=$consoledev,$baudrate $othbootargs;" \ 837 "tftp $loadaddr $bootfile;" \ 838 "tftp $fdtaddr $fdtfile;" \ 839 "bootm $loadaddr - $fdtaddr" 840 841 #define CONFIG_RAMBOOTCOMMAND \ 842 "setenv bootargs root=/dev/ram rw " \ 843 "console=$consoledev,$baudrate $othbootargs;" \ 844 "tftp $ramdiskaddr $ramdiskfile;" \ 845 "tftp $loadaddr $bootfile;" \ 846 "tftp $fdtaddr $fdtfile;" \ 847 "bootm $loadaddr $ramdiskaddr $fdtaddr" 848 849 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 850 851 #ifdef CONFIG_SECURE_BOOT 852 #include <asm/fsl_secure_boot.h> 853 #define CONFIG_CMD_BLOB 854 #endif 855 856 #endif /* __CONFIG_H */ 857