1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 /* support deep sleep */ 46 #define CONFIG_DEEP_SLEEP 47 #if defined(CONFIG_DEEP_SLEEP) 48 #define CONFIG_SILENT_CONSOLE 49 #define CONFIG_BOARD_EARLY_INIT_F 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 61 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 62 #define CONFIG_FSL_IFC /* Enable IFC Support */ 63 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 64 #define CONFIG_PCI /* Enable PCI/PCIE */ 65 #define CONFIG_PCI_INDIRECT_BRIDGE 66 #define CONFIG_PCIE1 /* PCIE controller 1 */ 67 #define CONFIG_PCIE2 /* PCIE controller 2 */ 68 #define CONFIG_PCIE3 /* PCIE controller 3 */ 69 #define CONFIG_PCIE4 /* PCIE controller 4 */ 70 71 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 72 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 73 74 #define CONFIG_FSL_LAW /* Use common FSL init code */ 75 76 #define CONFIG_ENV_OVERWRITE 77 78 #ifdef CONFIG_SYS_NO_FLASH 79 #define CONFIG_ENV_IS_NOWHERE 80 #else 81 #define CONFIG_FLASH_CFI_DRIVER 82 #define CONFIG_SYS_FLASH_CFI 83 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 84 #endif 85 86 #ifndef CONFIG_SYS_NO_FLASH 87 #if defined(CONFIG_SPIFLASH) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_SPI_FLASH 90 #define CONFIG_ENV_SPI_BUS 0 91 #define CONFIG_ENV_SPI_CS 0 92 #define CONFIG_ENV_SPI_MAX_HZ 10000000 93 #define CONFIG_ENV_SPI_MODE 0 94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 96 #define CONFIG_ENV_SECT_SIZE 0x10000 97 #elif defined(CONFIG_SDCARD) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_MMC 100 #define CONFIG_SYS_MMC_ENV_DEV 0 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_OFFSET (512 * 1658) 103 #elif defined(CONFIG_NAND) 104 #define CONFIG_SYS_EXTRA_ENV_RELOC 105 #define CONFIG_ENV_IS_IN_NAND 106 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 107 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 108 #else 109 #define CONFIG_ENV_IS_IN_FLASH 110 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 113 #endif 114 #else /* CONFIG_SYS_NO_FLASH */ 115 #define CONFIG_ENV_SIZE 0x2000 116 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 117 #endif 118 119 #ifndef __ASSEMBLY__ 120 unsigned long get_board_sys_clk(void); 121 unsigned long get_board_ddr_clk(void); 122 #endif 123 124 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 125 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 126 127 /* 128 * These can be toggled for performance analysis, otherwise use default. 129 */ 130 #define CONFIG_SYS_CACHE_STASHING 131 #define CONFIG_BACKSIDE_L2_CACHE 132 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 133 #define CONFIG_BTB /* toggle branch predition */ 134 #define CONFIG_DDR_ECC 135 #ifdef CONFIG_DDR_ECC 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 138 #endif 139 140 #define CONFIG_ENABLE_36BIT_PHYS 141 142 #define CONFIG_ADDR_MAP 143 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 144 145 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 146 #define CONFIG_SYS_MEMTEST_END 0x00400000 147 #define CONFIG_SYS_ALT_MEMTEST 148 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 149 150 /* 151 * Config the L3 Cache as L3 SRAM 152 */ 153 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 154 155 #define CONFIG_SYS_DCSRBAR 0xf0000000 156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 157 158 /* EEPROM */ 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_NXID 161 #define CONFIG_SYS_EEPROM_BUS_NUM 0 162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 165 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 166 167 /* 168 * DDR Setup 169 */ 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 173 174 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 175 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 176 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 177 178 #define CONFIG_DDR_SPD 179 #ifndef CONFIG_SYS_FSL_DDR4 180 #define CONFIG_SYS_FSL_DDR3 181 #endif 182 #define CONFIG_FSL_DDR_INTERACTIVE 183 184 #define CONFIG_SYS_SPD_BUS_NUM 0 185 #define SPD_EEPROM_ADDRESS 0x51 186 187 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 188 189 /* 190 * IFC Definitions 191 */ 192 #define CONFIG_SYS_FLASH_BASE 0xe0000000 193 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 194 195 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 196 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 197 + 0x8000000) | \ 198 CSPR_PORT_SIZE_16 | \ 199 CSPR_MSEL_NOR | \ 200 CSPR_V) 201 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 202 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 203 CSPR_PORT_SIZE_16 | \ 204 CSPR_MSEL_NOR | \ 205 CSPR_V) 206 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 207 208 /* 209 * TDM Definition 210 */ 211 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 212 213 /* NOR Flash Timing Params */ 214 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 215 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 216 FTIM0_NOR_TEADC(0x5) | \ 217 FTIM0_NOR_TEAHC(0x5)) 218 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 219 FTIM1_NOR_TRAD_NOR(0x1A) |\ 220 FTIM1_NOR_TSEQRAD_NOR(0x13)) 221 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 222 FTIM2_NOR_TCH(0x4) | \ 223 FTIM2_NOR_TWPH(0x0E) | \ 224 FTIM2_NOR_TWP(0x1c)) 225 #define CONFIG_SYS_NOR_FTIM3 0x0 226 227 #define CONFIG_SYS_FLASH_QUIET_TEST 228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 229 230 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 232 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 233 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 234 235 #define CONFIG_SYS_FLASH_EMPTY_INFO 236 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 237 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 238 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 239 #define QIXIS_BASE 0xffdf0000 240 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 241 #define QIXIS_LBMAP_SWITCH 0x06 242 #define QIXIS_LBMAP_MASK 0x0f 243 #define QIXIS_LBMAP_SHIFT 0 244 #define QIXIS_LBMAP_DFLTBANK 0x00 245 #define QIXIS_LBMAP_ALTBANK 0x04 246 #define QIXIS_RST_CTL_RESET 0x31 247 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 248 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 249 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 250 #define QIXIS_RST_FORCE_MEM 0x01 251 252 #define CONFIG_SYS_CSPR3_EXT (0xf) 253 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 254 | CSPR_PORT_SIZE_8 \ 255 | CSPR_MSEL_GPCM \ 256 | CSPR_V) 257 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 258 #define CONFIG_SYS_CSOR3 0x0 259 /* QIXIS Timing parameters for IFC CS3 */ 260 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 261 FTIM0_GPCM_TEADC(0x0e) | \ 262 FTIM0_GPCM_TEAHC(0x0e)) 263 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 264 FTIM1_GPCM_TRAD(0x3f)) 265 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 266 FTIM2_GPCM_TCH(0x8) | \ 267 FTIM2_GPCM_TWP(0x1f)) 268 #define CONFIG_SYS_CS3_FTIM3 0x0 269 270 #define CONFIG_NAND_FSL_IFC 271 #define CONFIG_SYS_NAND_BASE 0xff800000 272 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 273 274 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 275 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 276 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 277 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 278 | CSPR_V) 279 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 280 281 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 282 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 283 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 284 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 285 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 286 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 287 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 288 289 #define CONFIG_SYS_NAND_ONFI_DETECTION 290 291 /* ONFI NAND Flash mode0 Timing Params */ 292 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 293 FTIM0_NAND_TWP(0x18) | \ 294 FTIM0_NAND_TWCHT(0x07) | \ 295 FTIM0_NAND_TWH(0x0a)) 296 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 297 FTIM1_NAND_TWBE(0x39) | \ 298 FTIM1_NAND_TRR(0x0e) | \ 299 FTIM1_NAND_TRP(0x18)) 300 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 301 FTIM2_NAND_TREH(0x0a) | \ 302 FTIM2_NAND_TWHRE(0x1e)) 303 #define CONFIG_SYS_NAND_FTIM3 0x0 304 305 #define CONFIG_SYS_NAND_DDR_LAW 11 306 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 307 #define CONFIG_SYS_MAX_NAND_DEVICE 1 308 #define CONFIG_CMD_NAND 309 310 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 311 312 #if defined(CONFIG_NAND) 313 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 314 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 315 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 316 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 317 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 318 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 319 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 320 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 321 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 322 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 323 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 324 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 325 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 326 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 327 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 328 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 329 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 330 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 331 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 332 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 333 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 334 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 335 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 336 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 337 #else 338 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 339 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 340 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 341 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 342 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 343 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 344 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 345 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 346 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 347 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 348 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 349 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 350 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 351 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 352 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 353 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 354 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #endif 363 364 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 365 366 #if defined(CONFIG_RAMBOOT_PBL) 367 #define CONFIG_SYS_RAMBOOT 368 #endif 369 370 #define CONFIG_BOARD_EARLY_INIT_R 371 #define CONFIG_MISC_INIT_R 372 373 #define CONFIG_HWCONFIG 374 375 /* define to use L1 as initial stack */ 376 #define CONFIG_L1_INIT_RAM 377 #define CONFIG_SYS_INIT_RAM_LOCK 378 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 381 /* The assembler doesn't like typecast */ 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 383 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 384 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 385 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 386 387 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 388 GENERATED_GBL_DATA_SIZE) 389 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 390 391 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 392 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 393 394 /* Serial Port - controlled on board with jumper J8 395 * open - index 2 396 * shorted - index 1 397 */ 398 #define CONFIG_CONS_INDEX 1 399 #define CONFIG_SYS_NS16550_SERIAL 400 #define CONFIG_SYS_NS16550_REG_SIZE 1 401 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 402 403 #define CONFIG_SYS_BAUDRATE_TABLE \ 404 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 405 406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 408 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 409 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 410 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 411 412 /* Video */ 413 #define CONFIG_FSL_DIU_FB 414 #ifdef CONFIG_FSL_DIU_FB 415 #define CONFIG_FSL_DIU_CH7301 416 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 417 #define CONFIG_VIDEO 418 #define CONFIG_CMD_BMP 419 #define CONFIG_CFB_CONSOLE 420 #define CONFIG_VIDEO_SW_CURSOR 421 #define CONFIG_VGA_AS_SINGLE_DEVICE 422 #define CONFIG_VIDEO_LOGO 423 #define CONFIG_VIDEO_BMP_LOGO 424 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 425 /* 426 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 427 * disable empty flash sector detection, which is I/O-intensive. 428 */ 429 #undef CONFIG_SYS_FLASH_EMPTY_INFO 430 #endif 431 432 /* I2C */ 433 #define CONFIG_SYS_I2C 434 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 435 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 436 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 437 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 438 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 439 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 440 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 441 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 442 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 443 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 444 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 445 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 446 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 447 448 #define I2C_MUX_PCA_ADDR 0x77 449 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 450 451 /* I2C bus multiplexer */ 452 #define I2C_MUX_CH_DEFAULT 0x8 453 #define I2C_MUX_CH_DIU 0xC 454 455 /* LDI/DVI Encoder for display */ 456 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 457 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 458 459 /* 460 * RTC configuration 461 */ 462 #define RTC 463 #define CONFIG_RTC_DS3231 1 464 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 465 466 /* 467 * eSPI - Enhanced SPI 468 */ 469 #define CONFIG_SF_DEFAULT_SPEED 10000000 470 #define CONFIG_SF_DEFAULT_MODE 0 471 472 /* 473 * General PCI 474 * Memory space is mapped 1-1, but I/O space must start from 0. 475 */ 476 477 #ifdef CONFIG_PCI 478 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 479 #ifdef CONFIG_PCIE1 480 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 481 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 482 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 483 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 484 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 485 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 486 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 487 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 488 #endif 489 490 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 491 #ifdef CONFIG_PCIE2 492 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 493 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 495 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 497 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 498 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 499 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 500 #endif 501 502 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 503 #ifdef CONFIG_PCIE3 504 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 505 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 506 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 507 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 508 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 509 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 510 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 511 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 512 #endif 513 514 /* controller 4, Base address 203000 */ 515 #ifdef CONFIG_PCIE4 516 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 517 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 519 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 520 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 521 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 522 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 523 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 524 #endif 525 526 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 527 528 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 529 #define CONFIG_DOS_PARTITION 530 #endif /* CONFIG_PCI */ 531 532 /* SATA */ 533 #define CONFIG_FSL_SATA_V2 534 #ifdef CONFIG_FSL_SATA_V2 535 #define CONFIG_LIBATA 536 #define CONFIG_FSL_SATA 537 538 #define CONFIG_SYS_SATA_MAX_DEVICE 2 539 #define CONFIG_SATA1 540 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 541 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 542 #define CONFIG_SATA2 543 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 544 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 545 546 #define CONFIG_LBA48 547 #define CONFIG_CMD_SATA 548 #define CONFIG_DOS_PARTITION 549 #endif 550 551 /* 552 * USB 553 */ 554 #define CONFIG_HAS_FSL_DR_USB 555 556 #ifdef CONFIG_HAS_FSL_DR_USB 557 #define CONFIG_USB_EHCI 558 559 #ifdef CONFIG_USB_EHCI 560 #define CONFIG_USB_EHCI_FSL 561 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 562 #endif 563 #endif 564 565 #define CONFIG_MMC 566 567 #ifdef CONFIG_MMC 568 #define CONFIG_FSL_ESDHC 569 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 570 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 571 #define CONFIG_GENERIC_MMC 572 #define CONFIG_DOS_PARTITION 573 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 574 #endif 575 576 /* Qman/Bman */ 577 #ifndef CONFIG_NOBQFMAN 578 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 579 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 580 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 581 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 582 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 583 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 584 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 585 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 586 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 587 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 588 CONFIG_SYS_BMAN_CENA_SIZE) 589 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 590 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 591 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 592 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 593 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 594 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 595 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 596 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 597 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 598 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 599 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 600 CONFIG_SYS_QMAN_CENA_SIZE) 601 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 602 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 603 604 #define CONFIG_SYS_DPAA_FMAN 605 #define CONFIG_SYS_DPAA_PME 606 607 #define CONFIG_QE 608 #define CONFIG_U_QE 609 /* Default address of microcode for the Linux Fman driver */ 610 #if defined(CONFIG_SPIFLASH) 611 /* 612 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 613 * env, so we got 0x110000. 614 */ 615 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 616 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 617 #elif defined(CONFIG_SDCARD) 618 /* 619 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 620 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 621 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 622 */ 623 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 624 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 625 #elif defined(CONFIG_NAND) 626 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 627 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 628 #else 629 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 630 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 631 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 632 #endif 633 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 634 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 635 #endif /* CONFIG_NOBQFMAN */ 636 637 #ifdef CONFIG_SYS_DPAA_FMAN 638 #define CONFIG_FMAN_ENET 639 #define CONFIG_PHYLIB_10G 640 #define CONFIG_PHY_VITESSE 641 #define CONFIG_PHY_REALTEK 642 #define CONFIG_PHY_TERANETICS 643 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 644 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 645 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 646 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 647 #endif 648 649 #ifdef CONFIG_FMAN_ENET 650 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 651 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 652 653 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 654 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 655 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 656 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 657 658 #define CONFIG_MII /* MII PHY management */ 659 #define CONFIG_ETHPRIME "FM1@DTSEC1" 660 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 661 #endif 662 663 /* Enable VSC9953 L2 Switch driver */ 664 #define CONFIG_VSC9953 665 #define CONFIG_CMD_ETHSW 666 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 667 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 668 669 /* 670 * Dynamic MTD Partition support with mtdparts 671 */ 672 #ifndef CONFIG_SYS_NO_FLASH 673 #define CONFIG_MTD_DEVICE 674 #define CONFIG_MTD_PARTITIONS 675 #define CONFIG_CMD_MTDPARTS 676 #define CONFIG_FLASH_CFI_MTD 677 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 678 "spi0=spife110000.0" 679 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 680 "128k(dtb),96m(fs),-(user);"\ 681 "fff800000.flash:2m(uboot),9m(kernel),"\ 682 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 683 "2m(uboot),9m(kernel),128k(dtb),-(user)" 684 #endif 685 686 /* 687 * Environment 688 */ 689 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 690 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 691 692 /* 693 * Command line configuration. 694 */ 695 #define CONFIG_CMD_DATE 696 #define CONFIG_CMD_EEPROM 697 #define CONFIG_CMD_ERRATA 698 #define CONFIG_CMD_IRQ 699 #define CONFIG_CMD_REGINFO 700 701 #ifdef CONFIG_PCI 702 #define CONFIG_CMD_PCI 703 #endif 704 705 /* Hash command with SHA acceleration supported in hardware */ 706 #ifdef CONFIG_FSL_CAAM 707 #define CONFIG_CMD_HASH 708 #define CONFIG_SHA_HW_ACCEL 709 #endif 710 711 /* 712 * Miscellaneous configurable options 713 */ 714 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 715 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 716 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 717 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 718 #ifdef CONFIG_CMD_KGDB 719 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 720 #else 721 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 722 #endif 723 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 724 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 725 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 726 727 /* 728 * For booting Linux, the board info and command line data 729 * have to be in the first 64 MB of memory, since this is 730 * the maximum mapped by the Linux kernel during initialization. 731 */ 732 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 733 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 734 735 #ifdef CONFIG_CMD_KGDB 736 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 737 #endif 738 739 /* 740 * Environment Configuration 741 */ 742 #define CONFIG_ROOTPATH "/opt/nfsroot" 743 #define CONFIG_BOOTFILE "uImage" 744 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 745 746 /* default location for tftp and bootm */ 747 #define CONFIG_LOADADDR 1000000 748 749 750 #define CONFIG_BAUDRATE 115200 751 752 #define __USB_PHY_TYPE utmi 753 754 #define CONFIG_EXTRA_ENV_SETTINGS \ 755 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 756 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 757 "netdev=eth0\0" \ 758 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 759 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 760 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 761 "tftpflash=tftpboot $loadaddr $uboot && " \ 762 "protect off $ubootaddr +$filesize && " \ 763 "erase $ubootaddr +$filesize && " \ 764 "cp.b $loadaddr $ubootaddr $filesize && " \ 765 "protect on $ubootaddr +$filesize && " \ 766 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 767 "consoledev=ttyS0\0" \ 768 "ramdiskaddr=2000000\0" \ 769 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 770 "fdtaddr=1e00000\0" \ 771 "fdtfile=t1040qds/t1040qds.dtb\0" \ 772 "bdev=sda3\0" 773 774 #define CONFIG_LINUX \ 775 "setenv bootargs root=/dev/ram rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "setenv ramdiskaddr 0x02000000;" \ 778 "setenv fdtaddr 0x00c00000;" \ 779 "setenv loadaddr 0x1000000;" \ 780 "bootm $loadaddr $ramdiskaddr $fdtaddr" 781 782 #define CONFIG_HDBOOT \ 783 "setenv bootargs root=/dev/$bdev rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr - $fdtaddr" 788 789 #define CONFIG_NFSBOOTCOMMAND \ 790 "setenv bootargs root=/dev/nfs rw " \ 791 "nfsroot=$serverip:$rootpath " \ 792 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 793 "console=$consoledev,$baudrate $othbootargs;" \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr - $fdtaddr" 797 798 #define CONFIG_RAMBOOTCOMMAND \ 799 "setenv bootargs root=/dev/ram rw " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "tftp $ramdiskaddr $ramdiskfile;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr $ramdiskaddr $fdtaddr" 805 806 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 807 808 #include <asm/fsl_secure_boot.h> 809 810 #endif /* __CONFIG_H */ 811