1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 40 /* support deep sleep */ 41 #define CONFIG_DEEP_SLEEP 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 49 #define CONFIG_PCI_INDIRECT_BRIDGE 50 #define CONFIG_PCIE1 /* PCIE controller 1 */ 51 #define CONFIG_PCIE2 /* PCIE controller 2 */ 52 #define CONFIG_PCIE3 /* PCIE controller 3 */ 53 #define CONFIG_PCIE4 /* PCIE controller 4 */ 54 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #ifdef CONFIG_MTD_NOR_FLASH 61 #if defined(CONFIG_SPIFLASH) 62 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 63 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 64 #define CONFIG_ENV_SECT_SIZE 0x10000 65 #elif defined(CONFIG_SDCARD) 66 #define CONFIG_SYS_MMC_ENV_DEV 0 67 #define CONFIG_ENV_SIZE 0x2000 68 #define CONFIG_ENV_OFFSET (512 * 1658) 69 #elif defined(CONFIG_NAND) 70 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 71 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 72 #else 73 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 74 #define CONFIG_ENV_SIZE 0x2000 75 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 76 #endif 77 #else /* CONFIG_MTD_NOR_FLASH */ 78 #define CONFIG_ENV_SIZE 0x2000 79 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 80 #endif 81 82 #ifndef __ASSEMBLY__ 83 unsigned long get_board_sys_clk(void); 84 unsigned long get_board_ddr_clk(void); 85 #endif 86 87 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 88 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 89 90 /* 91 * These can be toggled for performance analysis, otherwise use default. 92 */ 93 #define CONFIG_SYS_CACHE_STASHING 94 #define CONFIG_BACKSIDE_L2_CACHE 95 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 96 #define CONFIG_BTB /* toggle branch predition */ 97 #define CONFIG_DDR_ECC 98 #ifdef CONFIG_DDR_ECC 99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 100 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 101 #endif 102 103 #define CONFIG_ENABLE_36BIT_PHYS 104 105 #define CONFIG_ADDR_MAP 106 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 107 108 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 109 #define CONFIG_SYS_MEMTEST_END 0x00400000 110 111 /* 112 * Config the L3 Cache as L3 SRAM 113 */ 114 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 115 116 #define CONFIG_SYS_DCSRBAR 0xf0000000 117 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 118 119 /* EEPROM */ 120 #define CONFIG_ID_EEPROM 121 #define CONFIG_SYS_I2C_EEPROM_NXID 122 #define CONFIG_SYS_EEPROM_BUS_NUM 0 123 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 126 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_VERY_BIG_RAM 132 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 134 135 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 136 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 137 138 #define CONFIG_DDR_SPD 139 140 #define CONFIG_SYS_SPD_BUS_NUM 0 141 #define SPD_EEPROM_ADDRESS 0x51 142 143 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 144 145 /* 146 * IFC Definitions 147 */ 148 #define CONFIG_SYS_FLASH_BASE 0xe0000000 149 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 150 151 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 152 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 153 + 0x8000000) | \ 154 CSPR_PORT_SIZE_16 | \ 155 CSPR_MSEL_NOR | \ 156 CSPR_V) 157 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 158 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 159 CSPR_PORT_SIZE_16 | \ 160 CSPR_MSEL_NOR | \ 161 CSPR_V) 162 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 163 164 /* 165 * TDM Definition 166 */ 167 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 168 169 /* NOR Flash Timing Params */ 170 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 171 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 172 FTIM0_NOR_TEADC(0x5) | \ 173 FTIM0_NOR_TEAHC(0x5)) 174 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 175 FTIM1_NOR_TRAD_NOR(0x1A) |\ 176 FTIM1_NOR_TSEQRAD_NOR(0x13)) 177 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 178 FTIM2_NOR_TCH(0x4) | \ 179 FTIM2_NOR_TWPH(0x0E) | \ 180 FTIM2_NOR_TWP(0x1c)) 181 #define CONFIG_SYS_NOR_FTIM3 0x0 182 183 #define CONFIG_SYS_FLASH_QUIET_TEST 184 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 185 186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 187 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 191 #define CONFIG_SYS_FLASH_EMPTY_INFO 192 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 193 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 194 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 195 #define QIXIS_BASE 0xffdf0000 196 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 197 #define QIXIS_LBMAP_SWITCH 0x06 198 #define QIXIS_LBMAP_MASK 0x0f 199 #define QIXIS_LBMAP_SHIFT 0 200 #define QIXIS_LBMAP_DFLTBANK 0x00 201 #define QIXIS_LBMAP_ALTBANK 0x04 202 #define QIXIS_RST_CTL_RESET 0x31 203 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 204 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 205 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 206 #define QIXIS_RST_FORCE_MEM 0x01 207 208 #define CONFIG_SYS_CSPR3_EXT (0xf) 209 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 210 | CSPR_PORT_SIZE_8 \ 211 | CSPR_MSEL_GPCM \ 212 | CSPR_V) 213 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 214 #define CONFIG_SYS_CSOR3 0x0 215 /* QIXIS Timing parameters for IFC CS3 */ 216 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 217 FTIM0_GPCM_TEADC(0x0e) | \ 218 FTIM0_GPCM_TEAHC(0x0e)) 219 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 220 FTIM1_GPCM_TRAD(0x3f)) 221 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 222 FTIM2_GPCM_TCH(0x8) | \ 223 FTIM2_GPCM_TWP(0x1f)) 224 #define CONFIG_SYS_CS3_FTIM3 0x0 225 226 #define CONFIG_NAND_FSL_IFC 227 #define CONFIG_SYS_NAND_BASE 0xff800000 228 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 229 230 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 231 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 232 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 233 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 234 | CSPR_V) 235 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 236 237 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 238 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 239 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 240 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 241 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 242 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 243 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 244 245 #define CONFIG_SYS_NAND_ONFI_DETECTION 246 247 /* ONFI NAND Flash mode0 Timing Params */ 248 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 249 FTIM0_NAND_TWP(0x18) | \ 250 FTIM0_NAND_TWCHT(0x07) | \ 251 FTIM0_NAND_TWH(0x0a)) 252 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 253 FTIM1_NAND_TWBE(0x39) | \ 254 FTIM1_NAND_TRR(0x0e) | \ 255 FTIM1_NAND_TRP(0x18)) 256 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 257 FTIM2_NAND_TREH(0x0a) | \ 258 FTIM2_NAND_TWHRE(0x1e)) 259 #define CONFIG_SYS_NAND_FTIM3 0x0 260 261 #define CONFIG_SYS_NAND_DDR_LAW 11 262 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 263 #define CONFIG_SYS_MAX_NAND_DEVICE 1 264 265 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 266 267 #if defined(CONFIG_NAND) 268 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 270 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 271 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 272 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 273 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 274 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 275 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 276 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 277 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 278 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 279 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 280 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 281 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 282 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 283 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 284 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 285 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 286 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 287 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 288 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 289 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 290 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 291 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 292 #else 293 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 294 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 295 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 296 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 297 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 298 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 299 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 300 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 301 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 302 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 303 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 304 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 305 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 306 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 307 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 308 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 309 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 310 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 311 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 312 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 313 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 314 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 315 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 316 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 317 #endif 318 319 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 320 321 #if defined(CONFIG_RAMBOOT_PBL) 322 #define CONFIG_SYS_RAMBOOT 323 #endif 324 325 #define CONFIG_HWCONFIG 326 327 /* define to use L1 as initial stack */ 328 #define CONFIG_L1_INIT_RAM 329 #define CONFIG_SYS_INIT_RAM_LOCK 330 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 331 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 333 /* The assembler doesn't like typecast */ 334 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 335 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 336 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 337 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 338 339 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 340 GENERATED_GBL_DATA_SIZE) 341 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 342 343 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 344 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 345 346 /* Serial Port - controlled on board with jumper J8 347 * open - index 2 348 * shorted - index 1 349 */ 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 353 354 #define CONFIG_SYS_BAUDRATE_TABLE \ 355 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 356 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 359 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 360 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 361 362 /* Video */ 363 #define CONFIG_FSL_DIU_FB 364 #ifdef CONFIG_FSL_DIU_FB 365 #define CONFIG_FSL_DIU_CH7301 366 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 367 #define CONFIG_VIDEO_LOGO 368 #define CONFIG_VIDEO_BMP_LOGO 369 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 370 /* 371 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 372 * disable empty flash sector detection, which is I/O-intensive. 373 */ 374 #undef CONFIG_SYS_FLASH_EMPTY_INFO 375 #endif 376 377 /* I2C */ 378 #define CONFIG_SYS_I2C 379 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 380 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 381 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 382 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 383 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 384 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 385 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 386 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 387 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 388 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 389 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 390 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 391 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 392 393 #define I2C_MUX_PCA_ADDR 0x77 394 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 395 396 /* I2C bus multiplexer */ 397 #define I2C_MUX_CH_DEFAULT 0x8 398 #define I2C_MUX_CH_DIU 0xC 399 400 /* LDI/DVI Encoder for display */ 401 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 402 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 403 404 /* 405 * RTC configuration 406 */ 407 #define RTC 408 #define CONFIG_RTC_DS3231 1 409 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 410 411 /* 412 * eSPI - Enhanced SPI 413 */ 414 415 /* 416 * General PCI 417 * Memory space is mapped 1-1, but I/O space must start from 0. 418 */ 419 420 #ifdef CONFIG_PCI 421 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 422 #ifdef CONFIG_PCIE1 423 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 424 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 425 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 426 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 427 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 428 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 429 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 430 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 431 #endif 432 433 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 434 #ifdef CONFIG_PCIE2 435 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 436 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 437 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 438 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 439 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 440 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 441 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 442 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 443 #endif 444 445 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 446 #ifdef CONFIG_PCIE3 447 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 448 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 449 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 450 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 451 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 452 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 453 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 454 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 455 #endif 456 457 /* controller 4, Base address 203000 */ 458 #ifdef CONFIG_PCIE4 459 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 460 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 461 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 462 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 463 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 464 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 465 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 466 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 467 #endif 468 469 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 470 #endif /* CONFIG_PCI */ 471 472 /* SATA */ 473 #define CONFIG_FSL_SATA_V2 474 #ifdef CONFIG_FSL_SATA_V2 475 #define CONFIG_SYS_SATA_MAX_DEVICE 2 476 #define CONFIG_SATA1 477 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 478 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 479 #define CONFIG_SATA2 480 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 481 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 482 483 #define CONFIG_LBA48 484 #endif 485 486 /* 487 * USB 488 */ 489 #define CONFIG_HAS_FSL_DR_USB 490 491 #ifdef CONFIG_HAS_FSL_DR_USB 492 #ifdef CONFIG_USB_EHCI_HCD 493 #define CONFIG_USB_EHCI_FSL 494 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 495 #endif 496 #endif 497 498 #ifdef CONFIG_MMC 499 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 500 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 501 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 502 #endif 503 504 /* Qman/Bman */ 505 #ifndef CONFIG_NOBQFMAN 506 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 507 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 508 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 509 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 510 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 511 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 512 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 513 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 514 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 515 CONFIG_SYS_BMAN_CENA_SIZE) 516 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 517 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 518 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 519 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 520 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 521 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 522 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 523 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 524 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 525 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 526 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 527 CONFIG_SYS_QMAN_CENA_SIZE) 528 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 529 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 530 531 #define CONFIG_SYS_DPAA_FMAN 532 #define CONFIG_SYS_DPAA_PME 533 534 #define CONFIG_QE 535 /* Default address of microcode for the Linux Fman driver */ 536 #if defined(CONFIG_SPIFLASH) 537 /* 538 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 539 * env, so we got 0x110000. 540 */ 541 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 542 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 543 #elif defined(CONFIG_SDCARD) 544 /* 545 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 546 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 547 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 548 */ 549 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 550 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 551 #elif defined(CONFIG_NAND) 552 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 553 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 554 #else 555 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 556 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 557 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 558 #endif 559 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 560 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 561 #endif /* CONFIG_NOBQFMAN */ 562 563 #ifdef CONFIG_SYS_DPAA_FMAN 564 #define CONFIG_FMAN_ENET 565 #define CONFIG_PHYLIB_10G 566 #define CONFIG_PHY_VITESSE 567 #define CONFIG_PHY_REALTEK 568 #define CONFIG_PHY_TERANETICS 569 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 570 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 571 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 572 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 573 #endif 574 575 #ifdef CONFIG_FMAN_ENET 576 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 577 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 578 579 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 580 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 581 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 582 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 583 584 #define CONFIG_ETHPRIME "FM1@DTSEC1" 585 #endif 586 587 /* Enable VSC9953 L2 Switch driver */ 588 #define CONFIG_VSC9953 589 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 590 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 591 592 /* 593 * Dynamic MTD Partition support with mtdparts 594 */ 595 596 /* 597 * Environment 598 */ 599 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 600 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 601 602 /* 603 * Miscellaneous configurable options 604 */ 605 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 606 607 /* 608 * For booting Linux, the board info and command line data 609 * have to be in the first 64 MB of memory, since this is 610 * the maximum mapped by the Linux kernel during initialization. 611 */ 612 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 613 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 614 615 #ifdef CONFIG_CMD_KGDB 616 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 617 #endif 618 619 /* 620 * Environment Configuration 621 */ 622 #define CONFIG_ROOTPATH "/opt/nfsroot" 623 #define CONFIG_BOOTFILE "uImage" 624 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 625 626 /* default location for tftp and bootm */ 627 #define CONFIG_LOADADDR 1000000 628 629 #define __USB_PHY_TYPE utmi 630 631 #define CONFIG_EXTRA_ENV_SETTINGS \ 632 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 633 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 634 "netdev=eth0\0" \ 635 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 636 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 637 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 638 "tftpflash=tftpboot $loadaddr $uboot && " \ 639 "protect off $ubootaddr +$filesize && " \ 640 "erase $ubootaddr +$filesize && " \ 641 "cp.b $loadaddr $ubootaddr $filesize && " \ 642 "protect on $ubootaddr +$filesize && " \ 643 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 644 "consoledev=ttyS0\0" \ 645 "ramdiskaddr=2000000\0" \ 646 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 647 "fdtaddr=1e00000\0" \ 648 "fdtfile=t1040qds/t1040qds.dtb\0" \ 649 "bdev=sda3\0" 650 651 #define CONFIG_LINUX \ 652 "setenv bootargs root=/dev/ram rw " \ 653 "console=$consoledev,$baudrate $othbootargs;" \ 654 "setenv ramdiskaddr 0x02000000;" \ 655 "setenv fdtaddr 0x00c00000;" \ 656 "setenv loadaddr 0x1000000;" \ 657 "bootm $loadaddr $ramdiskaddr $fdtaddr" 658 659 #define CONFIG_HDBOOT \ 660 "setenv bootargs root=/dev/$bdev rw " \ 661 "console=$consoledev,$baudrate $othbootargs;" \ 662 "tftp $loadaddr $bootfile;" \ 663 "tftp $fdtaddr $fdtfile;" \ 664 "bootm $loadaddr - $fdtaddr" 665 666 #define CONFIG_NFSBOOTCOMMAND \ 667 "setenv bootargs root=/dev/nfs rw " \ 668 "nfsroot=$serverip:$rootpath " \ 669 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 670 "console=$consoledev,$baudrate $othbootargs;" \ 671 "tftp $loadaddr $bootfile;" \ 672 "tftp $fdtaddr $fdtfile;" \ 673 "bootm $loadaddr - $fdtaddr" 674 675 #define CONFIG_RAMBOOTCOMMAND \ 676 "setenv bootargs root=/dev/ram rw " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $ramdiskaddr $ramdiskfile;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr $ramdiskaddr $fdtaddr" 682 683 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 684 685 #include <asm/fsl_secure_boot.h> 686 687 #endif /* __CONFIG_H */ 688