1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 /* support deep sleep */ 42 #define CONFIG_DEEP_SLEEP 43 #if defined(CONFIG_DEEP_SLEEP) 44 #define CONFIG_BOARD_EARLY_INIT_F 45 #endif 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff40000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 59 #define CONFIG_PCI_INDIRECT_BRIDGE 60 #define CONFIG_PCIE1 /* PCIE controller 1 */ 61 #define CONFIG_PCIE2 /* PCIE controller 2 */ 62 #define CONFIG_PCIE3 /* PCIE controller 3 */ 63 #define CONFIG_PCIE4 /* PCIE controller 4 */ 64 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #define CONFIG_ENV_IS_NOWHERE 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #ifndef CONFIG_SYS_NO_FLASH 79 #if defined(CONFIG_SPIFLASH) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #elif defined(CONFIG_SDCARD) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #else 101 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #endif 106 #else /* CONFIG_SYS_NO_FLASH */ 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #endif 110 111 #ifndef __ASSEMBLY__ 112 unsigned long get_board_sys_clk(void); 113 unsigned long get_board_ddr_clk(void); 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #define CONFIG_ENABLE_36BIT_PHYS 133 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 142 /* 143 * Config the L3 Cache as L3 SRAM 144 */ 145 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 147 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 170 #define CONFIG_DDR_SPD 171 #define CONFIG_FSL_DDR_INTERACTIVE 172 173 #define CONFIG_SYS_SPD_BUS_NUM 0 174 #define SPD_EEPROM_ADDRESS 0x51 175 176 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 177 178 /* 179 * IFC Definitions 180 */ 181 #define CONFIG_SYS_FLASH_BASE 0xe0000000 182 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 183 184 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 185 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 186 + 0x8000000) | \ 187 CSPR_PORT_SIZE_16 | \ 188 CSPR_MSEL_NOR | \ 189 CSPR_V) 190 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 191 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 192 CSPR_PORT_SIZE_16 | \ 193 CSPR_MSEL_NOR | \ 194 CSPR_V) 195 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 196 197 /* 198 * TDM Definition 199 */ 200 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 201 202 /* NOR Flash Timing Params */ 203 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 204 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 205 FTIM0_NOR_TEADC(0x5) | \ 206 FTIM0_NOR_TEAHC(0x5)) 207 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 208 FTIM1_NOR_TRAD_NOR(0x1A) |\ 209 FTIM1_NOR_TSEQRAD_NOR(0x13)) 210 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 211 FTIM2_NOR_TCH(0x4) | \ 212 FTIM2_NOR_TWPH(0x0E) | \ 213 FTIM2_NOR_TWP(0x1c)) 214 #define CONFIG_SYS_NOR_FTIM3 0x0 215 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #define CONFIG_SYS_FLASH_EMPTY_INFO 225 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 226 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 227 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 228 #define QIXIS_BASE 0xffdf0000 229 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 230 #define QIXIS_LBMAP_SWITCH 0x06 231 #define QIXIS_LBMAP_MASK 0x0f 232 #define QIXIS_LBMAP_SHIFT 0 233 #define QIXIS_LBMAP_DFLTBANK 0x00 234 #define QIXIS_LBMAP_ALTBANK 0x04 235 #define QIXIS_RST_CTL_RESET 0x31 236 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 237 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 238 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 239 #define QIXIS_RST_FORCE_MEM 0x01 240 241 #define CONFIG_SYS_CSPR3_EXT (0xf) 242 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 243 | CSPR_PORT_SIZE_8 \ 244 | CSPR_MSEL_GPCM \ 245 | CSPR_V) 246 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 247 #define CONFIG_SYS_CSOR3 0x0 248 /* QIXIS Timing parameters for IFC CS3 */ 249 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 250 FTIM0_GPCM_TEADC(0x0e) | \ 251 FTIM0_GPCM_TEAHC(0x0e)) 252 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 253 FTIM1_GPCM_TRAD(0x3f)) 254 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 255 FTIM2_GPCM_TCH(0x8) | \ 256 FTIM2_GPCM_TWP(0x1f)) 257 #define CONFIG_SYS_CS3_FTIM3 0x0 258 259 #define CONFIG_NAND_FSL_IFC 260 #define CONFIG_SYS_NAND_BASE 0xff800000 261 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 262 263 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 264 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 265 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 266 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 267 | CSPR_V) 268 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 269 270 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 271 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 272 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 273 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 274 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 275 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 276 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 277 278 #define CONFIG_SYS_NAND_ONFI_DETECTION 279 280 /* ONFI NAND Flash mode0 Timing Params */ 281 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 282 FTIM0_NAND_TWP(0x18) | \ 283 FTIM0_NAND_TWCHT(0x07) | \ 284 FTIM0_NAND_TWH(0x0a)) 285 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 286 FTIM1_NAND_TWBE(0x39) | \ 287 FTIM1_NAND_TRR(0x0e) | \ 288 FTIM1_NAND_TRP(0x18)) 289 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 290 FTIM2_NAND_TREH(0x0a) | \ 291 FTIM2_NAND_TWHRE(0x1e)) 292 #define CONFIG_SYS_NAND_FTIM3 0x0 293 294 #define CONFIG_SYS_NAND_DDR_LAW 11 295 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 296 #define CONFIG_SYS_MAX_NAND_DEVICE 1 297 #define CONFIG_CMD_NAND 298 299 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 300 301 #if defined(CONFIG_NAND) 302 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 303 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 304 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 305 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 306 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 307 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 308 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 309 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 310 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 311 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 312 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 313 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 314 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 315 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 316 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 317 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 318 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 319 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 320 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #else 327 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 328 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 329 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 330 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 331 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 332 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 333 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 334 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 335 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 336 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 337 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 338 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 339 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 340 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 341 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 342 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 343 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 344 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 345 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 346 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 347 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 348 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 349 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 350 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 351 #endif 352 353 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 354 355 #if defined(CONFIG_RAMBOOT_PBL) 356 #define CONFIG_SYS_RAMBOOT 357 #endif 358 359 #define CONFIG_BOARD_EARLY_INIT_R 360 #define CONFIG_MISC_INIT_R 361 362 #define CONFIG_HWCONFIG 363 364 /* define to use L1 as initial stack */ 365 #define CONFIG_L1_INIT_RAM 366 #define CONFIG_SYS_INIT_RAM_LOCK 367 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 369 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 370 /* The assembler doesn't like typecast */ 371 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 372 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 373 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 374 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 375 376 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 377 GENERATED_GBL_DATA_SIZE) 378 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 379 380 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 381 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 382 383 /* Serial Port - controlled on board with jumper J8 384 * open - index 2 385 * shorted - index 1 386 */ 387 #define CONFIG_CONS_INDEX 1 388 #define CONFIG_SYS_NS16550_SERIAL 389 #define CONFIG_SYS_NS16550_REG_SIZE 1 390 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 391 392 #define CONFIG_SYS_BAUDRATE_TABLE \ 393 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 394 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 396 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 397 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 398 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 399 400 /* Video */ 401 #define CONFIG_FSL_DIU_FB 402 #ifdef CONFIG_FSL_DIU_FB 403 #define CONFIG_FSL_DIU_CH7301 404 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 405 #define CONFIG_CMD_BMP 406 #define CONFIG_VIDEO_LOGO 407 #define CONFIG_VIDEO_BMP_LOGO 408 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 409 /* 410 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 411 * disable empty flash sector detection, which is I/O-intensive. 412 */ 413 #undef CONFIG_SYS_FLASH_EMPTY_INFO 414 #endif 415 416 /* I2C */ 417 #define CONFIG_SYS_I2C 418 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 419 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 420 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 421 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 422 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 423 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 425 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 427 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 428 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 429 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 430 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 431 432 #define I2C_MUX_PCA_ADDR 0x77 433 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 434 435 /* I2C bus multiplexer */ 436 #define I2C_MUX_CH_DEFAULT 0x8 437 #define I2C_MUX_CH_DIU 0xC 438 439 /* LDI/DVI Encoder for display */ 440 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 441 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 442 443 /* 444 * RTC configuration 445 */ 446 #define RTC 447 #define CONFIG_RTC_DS3231 1 448 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 449 450 /* 451 * eSPI - Enhanced SPI 452 */ 453 #define CONFIG_SF_DEFAULT_SPEED 10000000 454 #define CONFIG_SF_DEFAULT_MODE 0 455 456 /* 457 * General PCI 458 * Memory space is mapped 1-1, but I/O space must start from 0. 459 */ 460 461 #ifdef CONFIG_PCI 462 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 463 #ifdef CONFIG_PCIE1 464 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 465 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 466 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 467 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 468 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 469 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 470 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 471 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 472 #endif 473 474 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 475 #ifdef CONFIG_PCIE2 476 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 477 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 479 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 480 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 481 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 482 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 483 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 484 #endif 485 486 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 487 #ifdef CONFIG_PCIE3 488 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 489 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 490 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 491 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 492 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 493 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 494 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 495 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 496 #endif 497 498 /* controller 4, Base address 203000 */ 499 #ifdef CONFIG_PCIE4 500 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 501 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 502 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 503 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 504 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 505 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 506 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 507 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 508 #endif 509 510 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 511 #define CONFIG_DOS_PARTITION 512 #endif /* CONFIG_PCI */ 513 514 /* SATA */ 515 #define CONFIG_FSL_SATA_V2 516 #ifdef CONFIG_FSL_SATA_V2 517 #define CONFIG_LIBATA 518 #define CONFIG_FSL_SATA 519 520 #define CONFIG_SYS_SATA_MAX_DEVICE 2 521 #define CONFIG_SATA1 522 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 523 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 524 #define CONFIG_SATA2 525 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 526 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 527 528 #define CONFIG_LBA48 529 #define CONFIG_CMD_SATA 530 #define CONFIG_DOS_PARTITION 531 #endif 532 533 /* 534 * USB 535 */ 536 #define CONFIG_HAS_FSL_DR_USB 537 538 #ifdef CONFIG_HAS_FSL_DR_USB 539 #define CONFIG_USB_EHCI 540 541 #ifdef CONFIG_USB_EHCI 542 #define CONFIG_USB_EHCI_FSL 543 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 544 #endif 545 #endif 546 547 #ifdef CONFIG_MMC 548 #define CONFIG_FSL_ESDHC 549 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 550 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 551 #define CONFIG_GENERIC_MMC 552 #define CONFIG_DOS_PARTITION 553 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 554 #endif 555 556 /* Qman/Bman */ 557 #ifndef CONFIG_NOBQFMAN 558 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 559 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 560 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 561 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 562 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 563 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 564 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 565 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 566 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 567 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 568 CONFIG_SYS_BMAN_CENA_SIZE) 569 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 570 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 571 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 572 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 573 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 574 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 575 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 576 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 577 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 578 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 579 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 580 CONFIG_SYS_QMAN_CENA_SIZE) 581 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 582 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 583 584 #define CONFIG_SYS_DPAA_FMAN 585 #define CONFIG_SYS_DPAA_PME 586 587 #define CONFIG_QE 588 #define CONFIG_U_QE 589 /* Default address of microcode for the Linux Fman driver */ 590 #if defined(CONFIG_SPIFLASH) 591 /* 592 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 593 * env, so we got 0x110000. 594 */ 595 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 596 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 597 #elif defined(CONFIG_SDCARD) 598 /* 599 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 600 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 601 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 602 */ 603 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 604 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 605 #elif defined(CONFIG_NAND) 606 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 607 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 608 #else 609 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 610 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 611 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 612 #endif 613 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 614 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 615 #endif /* CONFIG_NOBQFMAN */ 616 617 #ifdef CONFIG_SYS_DPAA_FMAN 618 #define CONFIG_FMAN_ENET 619 #define CONFIG_PHYLIB_10G 620 #define CONFIG_PHY_VITESSE 621 #define CONFIG_PHY_REALTEK 622 #define CONFIG_PHY_TERANETICS 623 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 624 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 625 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 626 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 627 #endif 628 629 #ifdef CONFIG_FMAN_ENET 630 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 631 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 632 633 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 634 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 635 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 636 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 637 638 #define CONFIG_MII /* MII PHY management */ 639 #define CONFIG_ETHPRIME "FM1@DTSEC1" 640 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 641 #endif 642 643 /* Enable VSC9953 L2 Switch driver */ 644 #define CONFIG_VSC9953 645 #define CONFIG_CMD_ETHSW 646 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 647 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 648 649 /* 650 * Dynamic MTD Partition support with mtdparts 651 */ 652 #ifndef CONFIG_SYS_NO_FLASH 653 #define CONFIG_MTD_DEVICE 654 #define CONFIG_MTD_PARTITIONS 655 #define CONFIG_CMD_MTDPARTS 656 #define CONFIG_FLASH_CFI_MTD 657 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 658 "spi0=spife110000.0" 659 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 660 "128k(dtb),96m(fs),-(user);"\ 661 "fff800000.flash:2m(uboot),9m(kernel),"\ 662 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 663 "2m(uboot),9m(kernel),128k(dtb),-(user)" 664 #endif 665 666 /* 667 * Environment 668 */ 669 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 670 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 671 672 /* 673 * Command line configuration. 674 */ 675 #define CONFIG_CMD_DATE 676 #define CONFIG_CMD_EEPROM 677 #define CONFIG_CMD_ERRATA 678 #define CONFIG_CMD_IRQ 679 #define CONFIG_CMD_REGINFO 680 681 #ifdef CONFIG_PCI 682 #define CONFIG_CMD_PCI 683 #endif 684 685 /* Hash command with SHA acceleration supported in hardware */ 686 #ifdef CONFIG_FSL_CAAM 687 #define CONFIG_CMD_HASH 688 #define CONFIG_SHA_HW_ACCEL 689 #endif 690 691 /* 692 * Miscellaneous configurable options 693 */ 694 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 695 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 696 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 697 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 698 #ifdef CONFIG_CMD_KGDB 699 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 700 #else 701 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 702 #endif 703 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 704 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 705 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 706 707 /* 708 * For booting Linux, the board info and command line data 709 * have to be in the first 64 MB of memory, since this is 710 * the maximum mapped by the Linux kernel during initialization. 711 */ 712 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 713 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 714 715 #ifdef CONFIG_CMD_KGDB 716 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 717 #endif 718 719 /* 720 * Environment Configuration 721 */ 722 #define CONFIG_ROOTPATH "/opt/nfsroot" 723 #define CONFIG_BOOTFILE "uImage" 724 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 725 726 /* default location for tftp and bootm */ 727 #define CONFIG_LOADADDR 1000000 728 729 730 #define CONFIG_BAUDRATE 115200 731 732 #define __USB_PHY_TYPE utmi 733 734 #define CONFIG_EXTRA_ENV_SETTINGS \ 735 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 736 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 737 "netdev=eth0\0" \ 738 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 739 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 740 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 741 "tftpflash=tftpboot $loadaddr $uboot && " \ 742 "protect off $ubootaddr +$filesize && " \ 743 "erase $ubootaddr +$filesize && " \ 744 "cp.b $loadaddr $ubootaddr $filesize && " \ 745 "protect on $ubootaddr +$filesize && " \ 746 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 747 "consoledev=ttyS0\0" \ 748 "ramdiskaddr=2000000\0" \ 749 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 750 "fdtaddr=1e00000\0" \ 751 "fdtfile=t1040qds/t1040qds.dtb\0" \ 752 "bdev=sda3\0" 753 754 #define CONFIG_LINUX \ 755 "setenv bootargs root=/dev/ram rw " \ 756 "console=$consoledev,$baudrate $othbootargs;" \ 757 "setenv ramdiskaddr 0x02000000;" \ 758 "setenv fdtaddr 0x00c00000;" \ 759 "setenv loadaddr 0x1000000;" \ 760 "bootm $loadaddr $ramdiskaddr $fdtaddr" 761 762 #define CONFIG_HDBOOT \ 763 "setenv bootargs root=/dev/$bdev rw " \ 764 "console=$consoledev,$baudrate $othbootargs;" \ 765 "tftp $loadaddr $bootfile;" \ 766 "tftp $fdtaddr $fdtfile;" \ 767 "bootm $loadaddr - $fdtaddr" 768 769 #define CONFIG_NFSBOOTCOMMAND \ 770 "setenv bootargs root=/dev/nfs rw " \ 771 "nfsroot=$serverip:$rootpath " \ 772 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 773 "console=$consoledev,$baudrate $othbootargs;" \ 774 "tftp $loadaddr $bootfile;" \ 775 "tftp $fdtaddr $fdtfile;" \ 776 "bootm $loadaddr - $fdtaddr" 777 778 #define CONFIG_RAMBOOTCOMMAND \ 779 "setenv bootargs root=/dev/ram rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "tftp $ramdiskaddr $ramdiskfile;" \ 782 "tftp $loadaddr $bootfile;" \ 783 "tftp $fdtaddr $fdtfile;" \ 784 "bootm $loadaddr $ramdiskaddr $fdtaddr" 785 786 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 787 788 #include <asm/fsl_secure_boot.h> 789 790 #endif /* __CONFIG_H */ 791