1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MP /* support multiple processors */ 45 46 /* support deep sleep */ 47 #define CONFIG_DEEP_SLEEP 48 #define CONFIG_SILENT_CONSOLE 49 50 #ifndef CONFIG_SYS_TEXT_BASE 51 #define CONFIG_SYS_TEXT_BASE 0xeff40000 52 #endif 53 54 #ifndef CONFIG_RESET_VECTOR_ADDRESS 55 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 56 #endif 57 58 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 59 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 60 #define CONFIG_FSL_IFC /* Enable IFC Support */ 61 #define CONFIG_PCI /* Enable PCI/PCIE */ 62 #define CONFIG_PCI_INDIRECT_BRIDGE 63 #define CONFIG_PCIE1 /* PCIE controler 1 */ 64 #define CONFIG_PCIE2 /* PCIE controler 2 */ 65 #define CONFIG_PCIE3 /* PCIE controler 3 */ 66 #define CONFIG_PCIE4 /* PCIE controler 4 */ 67 68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 70 71 #define CONFIG_FSL_LAW /* Use common FSL init code */ 72 73 #define CONFIG_ENV_OVERWRITE 74 75 #ifdef CONFIG_SYS_NO_FLASH 76 #define CONFIG_ENV_IS_NOWHERE 77 #else 78 #define CONFIG_FLASH_CFI_DRIVER 79 #define CONFIG_SYS_FLASH_CFI 80 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 81 #endif 82 83 #ifndef CONFIG_SYS_NO_FLASH 84 #if defined(CONFIG_SPIFLASH) 85 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_ENV_IS_IN_SPI_FLASH 87 #define CONFIG_ENV_SPI_BUS 0 88 #define CONFIG_ENV_SPI_CS 0 89 #define CONFIG_ENV_SPI_MAX_HZ 10000000 90 #define CONFIG_ENV_SPI_MODE 0 91 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 92 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 93 #define CONFIG_ENV_SECT_SIZE 0x10000 94 #elif defined(CONFIG_SDCARD) 95 #define CONFIG_SYS_EXTRA_ENV_RELOC 96 #define CONFIG_ENV_IS_IN_MMC 97 #define CONFIG_SYS_MMC_ENV_DEV 0 98 #define CONFIG_ENV_SIZE 0x2000 99 #define CONFIG_ENV_OFFSET (512 * 1658) 100 #elif defined(CONFIG_NAND) 101 #define CONFIG_SYS_EXTRA_ENV_RELOC 102 #define CONFIG_ENV_IS_IN_NAND 103 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 104 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 105 #else 106 #define CONFIG_ENV_IS_IN_FLASH 107 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 108 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 110 #endif 111 #else /* CONFIG_SYS_NO_FLASH */ 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 114 #endif 115 116 #ifndef __ASSEMBLY__ 117 unsigned long get_board_sys_clk(void); 118 unsigned long get_board_ddr_clk(void); 119 #endif 120 121 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 122 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 123 124 /* 125 * These can be toggled for performance analysis, otherwise use default. 126 */ 127 #define CONFIG_SYS_CACHE_STASHING 128 #define CONFIG_BACKSIDE_L2_CACHE 129 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 130 #define CONFIG_BTB /* toggle branch predition */ 131 #define CONFIG_DDR_ECC 132 #ifdef CONFIG_DDR_ECC 133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 135 #endif 136 137 #define CONFIG_ENABLE_36BIT_PHYS 138 139 #define CONFIG_ADDR_MAP 140 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 141 142 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 143 #define CONFIG_SYS_MEMTEST_END 0x00400000 144 #define CONFIG_SYS_ALT_MEMTEST 145 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 146 147 /* 148 * Config the L3 Cache as L3 SRAM 149 */ 150 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 151 152 #define CONFIG_SYS_DCSRBAR 0xf0000000 153 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 154 155 /* EEPROM */ 156 #define CONFIG_ID_EEPROM 157 #define CONFIG_SYS_I2C_EEPROM_NXID 158 #define CONFIG_SYS_EEPROM_BUS_NUM 0 159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 163 164 /* 165 * DDR Setup 166 */ 167 #define CONFIG_VERY_BIG_RAM 168 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 169 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 170 171 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 173 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 174 175 #define CONFIG_DDR_SPD 176 #ifndef CONFIG_SYS_FSL_DDR4 177 #define CONFIG_SYS_FSL_DDR3 178 #define CONFIG_FSL_DDR_INTERACTIVE 179 #endif 180 181 #define CONFIG_SYS_SPD_BUS_NUM 0 182 #define SPD_EEPROM_ADDRESS 0x51 183 184 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 185 186 /* 187 * IFC Definitions 188 */ 189 #define CONFIG_SYS_FLASH_BASE 0xe0000000 190 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 191 192 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 193 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 194 + 0x8000000) | \ 195 CSPR_PORT_SIZE_16 | \ 196 CSPR_MSEL_NOR | \ 197 CSPR_V) 198 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 199 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 200 CSPR_PORT_SIZE_16 | \ 201 CSPR_MSEL_NOR | \ 202 CSPR_V) 203 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 204 205 /* 206 * TDM Definition 207 */ 208 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 209 210 /* NOR Flash Timing Params */ 211 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 212 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 213 FTIM0_NOR_TEADC(0x5) | \ 214 FTIM0_NOR_TEAHC(0x5)) 215 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 216 FTIM1_NOR_TRAD_NOR(0x1A) |\ 217 FTIM1_NOR_TSEQRAD_NOR(0x13)) 218 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 219 FTIM2_NOR_TCH(0x4) | \ 220 FTIM2_NOR_TWPH(0x0E) | \ 221 FTIM2_NOR_TWP(0x1c)) 222 #define CONFIG_SYS_NOR_FTIM3 0x0 223 224 #define CONFIG_SYS_FLASH_QUIET_TEST 225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 226 227 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 231 232 #define CONFIG_SYS_FLASH_EMPTY_INFO 233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 234 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 235 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 236 #define QIXIS_BASE 0xffdf0000 237 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 238 #define QIXIS_LBMAP_SWITCH 0x06 239 #define QIXIS_LBMAP_MASK 0x0f 240 #define QIXIS_LBMAP_SHIFT 0 241 #define QIXIS_LBMAP_DFLTBANK 0x00 242 #define QIXIS_LBMAP_ALTBANK 0x04 243 #define QIXIS_RST_CTL_RESET 0x31 244 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 245 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 246 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 247 #define QIXIS_RST_FORCE_MEM 0x01 248 249 #define CONFIG_SYS_CSPR3_EXT (0xf) 250 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 251 | CSPR_PORT_SIZE_8 \ 252 | CSPR_MSEL_GPCM \ 253 | CSPR_V) 254 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 255 #define CONFIG_SYS_CSOR3 0x0 256 /* QIXIS Timing parameters for IFC CS3 */ 257 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 258 FTIM0_GPCM_TEADC(0x0e) | \ 259 FTIM0_GPCM_TEAHC(0x0e)) 260 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 261 FTIM1_GPCM_TRAD(0x3f)) 262 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 263 FTIM2_GPCM_TCH(0x8) | \ 264 FTIM2_GPCM_TWP(0x1f)) 265 #define CONFIG_SYS_CS3_FTIM3 0x0 266 267 #define CONFIG_NAND_FSL_IFC 268 #define CONFIG_SYS_NAND_BASE 0xff800000 269 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 270 271 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 272 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 273 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 274 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 275 | CSPR_V) 276 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 277 278 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 279 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 280 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 281 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 282 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 283 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 284 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 285 286 #define CONFIG_SYS_NAND_ONFI_DETECTION 287 288 /* ONFI NAND Flash mode0 Timing Params */ 289 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 290 FTIM0_NAND_TWP(0x18) | \ 291 FTIM0_NAND_TWCHT(0x07) | \ 292 FTIM0_NAND_TWH(0x0a)) 293 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 294 FTIM1_NAND_TWBE(0x39) | \ 295 FTIM1_NAND_TRR(0x0e) | \ 296 FTIM1_NAND_TRP(0x18)) 297 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 298 FTIM2_NAND_TREH(0x0a) | \ 299 FTIM2_NAND_TWHRE(0x1e)) 300 #define CONFIG_SYS_NAND_FTIM3 0x0 301 302 #define CONFIG_SYS_NAND_DDR_LAW 11 303 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 304 #define CONFIG_SYS_MAX_NAND_DEVICE 1 305 #define CONFIG_MTD_NAND_VERIFY_WRITE 306 #define CONFIG_CMD_NAND 307 308 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 309 310 #if defined(CONFIG_NAND) 311 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 312 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 313 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 314 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 315 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 316 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 317 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 318 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 319 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 327 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 328 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 329 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 330 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 331 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 332 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 333 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 334 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 335 #else 336 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 344 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 345 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 346 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 347 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 348 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 349 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 350 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 351 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 352 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 353 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 354 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 355 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 356 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 357 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 358 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 359 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 360 #endif 361 362 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 363 364 #if defined(CONFIG_RAMBOOT_PBL) 365 #define CONFIG_SYS_RAMBOOT 366 #endif 367 368 #define CONFIG_BOARD_EARLY_INIT_R 369 #define CONFIG_MISC_INIT_R 370 371 #define CONFIG_HWCONFIG 372 373 /* define to use L1 as initial stack */ 374 #define CONFIG_L1_INIT_RAM 375 #define CONFIG_SYS_INIT_RAM_LOCK 376 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 379 /* The assembler doesn't like typecast */ 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 381 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 382 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 383 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 384 385 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 386 GENERATED_GBL_DATA_SIZE) 387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 388 389 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 390 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 391 392 /* Serial Port - controlled on board with jumper J8 393 * open - index 2 394 * shorted - index 1 395 */ 396 #define CONFIG_CONS_INDEX 1 397 #define CONFIG_SYS_NS16550 398 #define CONFIG_SYS_NS16550_SERIAL 399 #define CONFIG_SYS_NS16550_REG_SIZE 1 400 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 401 402 #define CONFIG_SYS_BAUDRATE_TABLE \ 403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 404 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 409 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 410 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 411 412 /* Use the HUSH parser */ 413 #define CONFIG_SYS_HUSH_PARSER 414 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 415 416 /* Video */ 417 #define CONFIG_FSL_DIU_FB 418 #ifdef CONFIG_FSL_DIU_FB 419 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 420 #define CONFIG_VIDEO 421 #define CONFIG_CMD_BMP 422 #define CONFIG_CFB_CONSOLE 423 #define CONFIG_VIDEO_SW_CURSOR 424 #define CONFIG_VGA_AS_SINGLE_DEVICE 425 #define CONFIG_VIDEO_LOGO 426 #define CONFIG_VIDEO_BMP_LOGO 427 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 428 /* 429 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 430 * disable empty flash sector detection, which is I/O-intensive. 431 */ 432 #undef CONFIG_SYS_FLASH_EMPTY_INFO 433 #endif 434 435 /* pass open firmware flat tree */ 436 #define CONFIG_OF_LIBFDT 437 #define CONFIG_OF_BOARD_SETUP 438 #define CONFIG_OF_STDOUT_VIA_ALIAS 439 440 /* new uImage format support */ 441 #define CONFIG_FIT 442 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 443 444 /* I2C */ 445 #define CONFIG_SYS_I2C 446 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 447 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 448 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 449 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 450 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 451 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 454 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 455 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 456 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 457 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 458 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 459 460 #define I2C_MUX_PCA_ADDR 0x77 461 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 462 463 464 /* I2C bus multiplexer */ 465 #define I2C_MUX_CH_DEFAULT 0x8 466 #define I2C_MUX_CH_DIU 0xC 467 468 /* LDI/DVI Encoder for display */ 469 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 470 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 471 472 /* 473 * RTC configuration 474 */ 475 #define RTC 476 #define CONFIG_RTC_DS3231 1 477 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 478 479 /* 480 * eSPI - Enhanced SPI 481 */ 482 #define CONFIG_FSL_ESPI 483 #define CONFIG_SPI_FLASH 484 #define CONFIG_SPI_FLASH_STMICRO 485 #define CONFIG_SPI_FLASH_SST 486 #define CONFIG_SPI_FLASH_EON 487 #define CONFIG_CMD_SF 488 #define CONFIG_SF_DEFAULT_SPEED 10000000 489 #define CONFIG_SF_DEFAULT_MODE 0 490 491 /* 492 * General PCI 493 * Memory space is mapped 1-1, but I/O space must start from 0. 494 */ 495 496 #ifdef CONFIG_PCI 497 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 498 #ifdef CONFIG_PCIE1 499 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 500 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 502 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 503 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 504 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 506 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 507 #endif 508 509 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 510 #ifdef CONFIG_PCIE2 511 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 512 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 513 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 514 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 515 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 516 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 517 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 518 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 519 #endif 520 521 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 522 #ifdef CONFIG_PCIE3 523 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 524 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 526 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 527 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 528 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 529 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 530 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 531 #endif 532 533 /* controller 4, Base address 203000 */ 534 #ifdef CONFIG_PCIE4 535 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 536 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 537 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 538 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 539 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 540 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 541 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 542 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 543 #endif 544 545 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 546 #define CONFIG_E1000 547 548 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 549 #define CONFIG_DOS_PARTITION 550 #endif /* CONFIG_PCI */ 551 552 /* SATA */ 553 #define CONFIG_FSL_SATA_V2 554 #ifdef CONFIG_FSL_SATA_V2 555 #define CONFIG_LIBATA 556 #define CONFIG_FSL_SATA 557 558 #define CONFIG_SYS_SATA_MAX_DEVICE 2 559 #define CONFIG_SATA1 560 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 561 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 562 #define CONFIG_SATA2 563 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 564 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 565 566 #define CONFIG_LBA48 567 #define CONFIG_CMD_SATA 568 #define CONFIG_DOS_PARTITION 569 #define CONFIG_CMD_EXT2 570 #endif 571 572 /* 573 * USB 574 */ 575 #define CONFIG_HAS_FSL_DR_USB 576 577 #ifdef CONFIG_HAS_FSL_DR_USB 578 #define CONFIG_USB_EHCI 579 580 #ifdef CONFIG_USB_EHCI 581 #define CONFIG_CMD_USB 582 #define CONFIG_USB_STORAGE 583 #define CONFIG_USB_EHCI_FSL 584 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 585 #define CONFIG_CMD_EXT2 586 #endif 587 #endif 588 589 #define CONFIG_MMC 590 591 #ifdef CONFIG_MMC 592 #define CONFIG_FSL_ESDHC 593 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 594 #define CONFIG_CMD_MMC 595 #define CONFIG_GENERIC_MMC 596 #define CONFIG_CMD_EXT2 597 #define CONFIG_CMD_FAT 598 #define CONFIG_DOS_PARTITION 599 #endif 600 601 /* Qman/Bman */ 602 #ifndef CONFIG_NOBQFMAN 603 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 604 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 605 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 606 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 607 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 608 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 609 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 610 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 611 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 612 613 #define CONFIG_SYS_DPAA_FMAN 614 #define CONFIG_SYS_DPAA_PME 615 616 #define CONFIG_QE 617 #define CONFIG_U_QE 618 /* Default address of microcode for the Linux Fman driver */ 619 #if defined(CONFIG_SPIFLASH) 620 /* 621 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 622 * env, so we got 0x110000. 623 */ 624 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 625 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 626 #elif defined(CONFIG_SDCARD) 627 /* 628 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 629 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 630 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 631 */ 632 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 633 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 634 #elif defined(CONFIG_NAND) 635 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 636 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 637 #else 638 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 639 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 640 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 641 #endif 642 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 643 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 644 #endif /* CONFIG_NOBQFMAN */ 645 646 #ifdef CONFIG_SYS_DPAA_FMAN 647 #define CONFIG_FMAN_ENET 648 #define CONFIG_PHYLIB_10G 649 #define CONFIG_PHY_VITESSE 650 #define CONFIG_PHY_REALTEK 651 #define CONFIG_PHY_TERANETICS 652 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 653 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 654 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 655 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 656 #endif 657 658 #ifdef CONFIG_FMAN_ENET 659 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 660 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 661 662 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 663 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 664 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 665 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 666 667 #define CONFIG_MII /* MII PHY management */ 668 #define CONFIG_ETHPRIME "FM1@DTSEC1" 669 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 670 #endif 671 672 /* 673 * Dynamic MTD Partition support with mtdparts 674 */ 675 #ifndef CONFIG_SYS_NO_FLASH 676 #define CONFIG_MTD_DEVICE 677 #define CONFIG_MTD_PARTITIONS 678 #define CONFIG_CMD_MTDPARTS 679 #define CONFIG_FLASH_CFI_MTD 680 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 681 "spi0=spife110000.0" 682 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 683 "128k(dtb),96m(fs),-(user);"\ 684 "fff800000.flash:2m(uboot),9m(kernel),"\ 685 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 686 "2m(uboot),9m(kernel),128k(dtb),-(user)" 687 #endif 688 689 /* 690 * Environment 691 */ 692 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 693 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 694 695 /* 696 * Command line configuration. 697 */ 698 #include <config_cmd_default.h> 699 700 #define CONFIG_CMD_DATE 701 #define CONFIG_CMD_DHCP 702 #define CONFIG_CMD_EEPROM 703 #define CONFIG_CMD_ELF 704 #define CONFIG_CMD_ERRATA 705 #define CONFIG_CMD_GREPENV 706 #define CONFIG_CMD_IRQ 707 #define CONFIG_CMD_I2C 708 #define CONFIG_CMD_MII 709 #define CONFIG_CMD_PING 710 #define CONFIG_CMD_REGINFO 711 #define CONFIG_CMD_SETEXPR 712 713 #ifdef CONFIG_PCI 714 #define CONFIG_CMD_PCI 715 #define CONFIG_CMD_NET 716 #endif 717 718 /* 719 * Miscellaneous configurable options 720 */ 721 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 722 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 723 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 724 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 725 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 726 #ifdef CONFIG_CMD_KGDB 727 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 728 #else 729 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 730 #endif 731 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 732 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 733 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 734 735 /* 736 * For booting Linux, the board info and command line data 737 * have to be in the first 64 MB of memory, since this is 738 * the maximum mapped by the Linux kernel during initialization. 739 */ 740 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 741 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 742 743 #ifdef CONFIG_CMD_KGDB 744 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 745 #endif 746 747 /* 748 * Environment Configuration 749 */ 750 #define CONFIG_ROOTPATH "/opt/nfsroot" 751 #define CONFIG_BOOTFILE "uImage" 752 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 753 754 /* default location for tftp and bootm */ 755 #define CONFIG_LOADADDR 1000000 756 757 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 758 759 #define CONFIG_BAUDRATE 115200 760 761 #define __USB_PHY_TYPE utmi 762 763 #define CONFIG_EXTRA_ENV_SETTINGS \ 764 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 765 "bank_intlv=cs0_cs1;" \ 766 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 767 "netdev=eth0\0" \ 768 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 769 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 770 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 771 "tftpflash=tftpboot $loadaddr $uboot && " \ 772 "protect off $ubootaddr +$filesize && " \ 773 "erase $ubootaddr +$filesize && " \ 774 "cp.b $loadaddr $ubootaddr $filesize && " \ 775 "protect on $ubootaddr +$filesize && " \ 776 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 777 "consoledev=ttyS0\0" \ 778 "ramdiskaddr=2000000\0" \ 779 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 780 "fdtaddr=c00000\0" \ 781 "fdtfile=t1040qds/t1040qds.dtb\0" \ 782 "bdev=sda3\0" 783 784 #define CONFIG_LINUX \ 785 "setenv bootargs root=/dev/ram rw " \ 786 "console=$consoledev,$baudrate $othbootargs;" \ 787 "setenv ramdiskaddr 0x02000000;" \ 788 "setenv fdtaddr 0x00c00000;" \ 789 "setenv loadaddr 0x1000000;" \ 790 "bootm $loadaddr $ramdiskaddr $fdtaddr" 791 792 #define CONFIG_HDBOOT \ 793 "setenv bootargs root=/dev/$bdev rw " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "tftp $loadaddr $bootfile;" \ 796 "tftp $fdtaddr $fdtfile;" \ 797 "bootm $loadaddr - $fdtaddr" 798 799 #define CONFIG_NFSBOOTCOMMAND \ 800 "setenv bootargs root=/dev/nfs rw " \ 801 "nfsroot=$serverip:$rootpath " \ 802 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 803 "console=$consoledev,$baudrate $othbootargs;" \ 804 "tftp $loadaddr $bootfile;" \ 805 "tftp $fdtaddr $fdtfile;" \ 806 "bootm $loadaddr - $fdtaddr" 807 808 #define CONFIG_RAMBOOTCOMMAND \ 809 "setenv bootargs root=/dev/ram rw " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "tftp $ramdiskaddr $ramdiskfile;" \ 812 "tftp $loadaddr $bootfile;" \ 813 "tftp $fdtaddr $fdtfile;" \ 814 "bootm $loadaddr $ramdiskaddr $fdtaddr" 815 816 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 817 818 #ifdef CONFIG_SECURE_BOOT 819 #include <asm/fsl_secure_boot.h> 820 #endif 821 822 #endif /* __CONFIG_H */ 823