1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 #define CONFIG_DISPLAY_BOARDINFO 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MP /* support multiple processors */ 45 46 /* support deep sleep */ 47 #define CONFIG_DEEP_SLEEP 48 #if defined(CONFIG_DEEP_SLEEP) 49 #define CONFIG_SILENT_CONSOLE 50 #define CONFIG_BOARD_EARLY_INIT_F 51 #endif 52 53 #ifndef CONFIG_SYS_TEXT_BASE 54 #define CONFIG_SYS_TEXT_BASE 0xeff40000 55 #endif 56 57 #ifndef CONFIG_RESET_VECTOR_ADDRESS 58 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 59 #endif 60 61 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 62 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 63 #define CONFIG_FSL_IFC /* Enable IFC Support */ 64 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 65 #define CONFIG_PCI /* Enable PCI/PCIE */ 66 #define CONFIG_PCI_INDIRECT_BRIDGE 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_PCIE2 /* PCIE controller 2 */ 69 #define CONFIG_PCIE3 /* PCIE controller 3 */ 70 #define CONFIG_PCIE4 /* PCIE controller 4 */ 71 72 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 74 75 #define CONFIG_FSL_LAW /* Use common FSL init code */ 76 77 #define CONFIG_ENV_OVERWRITE 78 79 #ifdef CONFIG_SYS_NO_FLASH 80 #define CONFIG_ENV_IS_NOWHERE 81 #else 82 #define CONFIG_FLASH_CFI_DRIVER 83 #define CONFIG_SYS_FLASH_CFI 84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 85 #endif 86 87 #ifndef CONFIG_SYS_NO_FLASH 88 #if defined(CONFIG_SPIFLASH) 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_ENV_IS_IN_SPI_FLASH 91 #define CONFIG_ENV_SPI_BUS 0 92 #define CONFIG_ENV_SPI_CS 0 93 #define CONFIG_ENV_SPI_MAX_HZ 10000000 94 #define CONFIG_ENV_SPI_MODE 0 95 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 96 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 97 #define CONFIG_ENV_SECT_SIZE 0x10000 98 #elif defined(CONFIG_SDCARD) 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_ENV_IS_IN_MMC 101 #define CONFIG_SYS_MMC_ENV_DEV 0 102 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_OFFSET (512 * 1658) 104 #elif defined(CONFIG_NAND) 105 #define CONFIG_SYS_EXTRA_ENV_RELOC 106 #define CONFIG_ENV_IS_IN_NAND 107 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 108 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 109 #else 110 #define CONFIG_ENV_IS_IN_FLASH 111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 114 #endif 115 #else /* CONFIG_SYS_NO_FLASH */ 116 #define CONFIG_ENV_SIZE 0x2000 117 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 118 #endif 119 120 #ifndef __ASSEMBLY__ 121 unsigned long get_board_sys_clk(void); 122 unsigned long get_board_ddr_clk(void); 123 #endif 124 125 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 126 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 127 128 /* 129 * These can be toggled for performance analysis, otherwise use default. 130 */ 131 #define CONFIG_SYS_CACHE_STASHING 132 #define CONFIG_BACKSIDE_L2_CACHE 133 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 134 #define CONFIG_BTB /* toggle branch predition */ 135 #define CONFIG_DDR_ECC 136 #ifdef CONFIG_DDR_ECC 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 138 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 139 #endif 140 141 #define CONFIG_ENABLE_36BIT_PHYS 142 143 #define CONFIG_ADDR_MAP 144 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 145 146 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 147 #define CONFIG_SYS_MEMTEST_END 0x00400000 148 #define CONFIG_SYS_ALT_MEMTEST 149 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 150 151 /* 152 * Config the L3 Cache as L3 SRAM 153 */ 154 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 155 156 #define CONFIG_SYS_DCSRBAR 0xf0000000 157 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 158 159 /* EEPROM */ 160 #define CONFIG_ID_EEPROM 161 #define CONFIG_SYS_I2C_EEPROM_NXID 162 #define CONFIG_SYS_EEPROM_BUS_NUM 0 163 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 165 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 166 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 167 168 /* 169 * DDR Setup 170 */ 171 #define CONFIG_VERY_BIG_RAM 172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 174 175 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 176 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 177 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 178 179 #define CONFIG_DDR_SPD 180 #ifndef CONFIG_SYS_FSL_DDR4 181 #define CONFIG_SYS_FSL_DDR3 182 #endif 183 #define CONFIG_FSL_DDR_INTERACTIVE 184 185 #define CONFIG_SYS_SPD_BUS_NUM 0 186 #define SPD_EEPROM_ADDRESS 0x51 187 188 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 189 190 /* 191 * IFC Definitions 192 */ 193 #define CONFIG_SYS_FLASH_BASE 0xe0000000 194 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 195 196 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 197 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 198 + 0x8000000) | \ 199 CSPR_PORT_SIZE_16 | \ 200 CSPR_MSEL_NOR | \ 201 CSPR_V) 202 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 203 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 204 CSPR_PORT_SIZE_16 | \ 205 CSPR_MSEL_NOR | \ 206 CSPR_V) 207 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 208 209 /* 210 * TDM Definition 211 */ 212 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 213 214 /* NOR Flash Timing Params */ 215 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 216 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 217 FTIM0_NOR_TEADC(0x5) | \ 218 FTIM0_NOR_TEAHC(0x5)) 219 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 220 FTIM1_NOR_TRAD_NOR(0x1A) |\ 221 FTIM1_NOR_TSEQRAD_NOR(0x13)) 222 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 223 FTIM2_NOR_TCH(0x4) | \ 224 FTIM2_NOR_TWPH(0x0E) | \ 225 FTIM2_NOR_TWP(0x1c)) 226 #define CONFIG_SYS_NOR_FTIM3 0x0 227 228 #define CONFIG_SYS_FLASH_QUIET_TEST 229 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 230 231 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 235 236 #define CONFIG_SYS_FLASH_EMPTY_INFO 237 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 238 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 239 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 240 #define QIXIS_BASE 0xffdf0000 241 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 242 #define QIXIS_LBMAP_SWITCH 0x06 243 #define QIXIS_LBMAP_MASK 0x0f 244 #define QIXIS_LBMAP_SHIFT 0 245 #define QIXIS_LBMAP_DFLTBANK 0x00 246 #define QIXIS_LBMAP_ALTBANK 0x04 247 #define QIXIS_RST_CTL_RESET 0x31 248 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 249 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 250 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 251 #define QIXIS_RST_FORCE_MEM 0x01 252 253 #define CONFIG_SYS_CSPR3_EXT (0xf) 254 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 255 | CSPR_PORT_SIZE_8 \ 256 | CSPR_MSEL_GPCM \ 257 | CSPR_V) 258 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 259 #define CONFIG_SYS_CSOR3 0x0 260 /* QIXIS Timing parameters for IFC CS3 */ 261 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 262 FTIM0_GPCM_TEADC(0x0e) | \ 263 FTIM0_GPCM_TEAHC(0x0e)) 264 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 265 FTIM1_GPCM_TRAD(0x3f)) 266 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 267 FTIM2_GPCM_TCH(0x8) | \ 268 FTIM2_GPCM_TWP(0x1f)) 269 #define CONFIG_SYS_CS3_FTIM3 0x0 270 271 #define CONFIG_NAND_FSL_IFC 272 #define CONFIG_SYS_NAND_BASE 0xff800000 273 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 274 275 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 276 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 277 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 278 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 279 | CSPR_V) 280 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 281 282 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 283 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 284 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 285 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 286 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 287 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 288 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 289 290 #define CONFIG_SYS_NAND_ONFI_DETECTION 291 292 /* ONFI NAND Flash mode0 Timing Params */ 293 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 294 FTIM0_NAND_TWP(0x18) | \ 295 FTIM0_NAND_TWCHT(0x07) | \ 296 FTIM0_NAND_TWH(0x0a)) 297 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 298 FTIM1_NAND_TWBE(0x39) | \ 299 FTIM1_NAND_TRR(0x0e) | \ 300 FTIM1_NAND_TRP(0x18)) 301 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 302 FTIM2_NAND_TREH(0x0a) | \ 303 FTIM2_NAND_TWHRE(0x1e)) 304 #define CONFIG_SYS_NAND_FTIM3 0x0 305 306 #define CONFIG_SYS_NAND_DDR_LAW 11 307 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 308 #define CONFIG_SYS_MAX_NAND_DEVICE 1 309 #define CONFIG_CMD_NAND 310 311 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 312 313 #if defined(CONFIG_NAND) 314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 331 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 332 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #else 339 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 340 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 341 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 342 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 343 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 344 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 345 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 346 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 347 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 348 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 349 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 350 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 351 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 352 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 353 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 354 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 355 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 356 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 357 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 358 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 359 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 360 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 361 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 362 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 363 #endif 364 365 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 366 367 #if defined(CONFIG_RAMBOOT_PBL) 368 #define CONFIG_SYS_RAMBOOT 369 #endif 370 371 #define CONFIG_BOARD_EARLY_INIT_R 372 #define CONFIG_MISC_INIT_R 373 374 #define CONFIG_HWCONFIG 375 376 /* define to use L1 as initial stack */ 377 #define CONFIG_L1_INIT_RAM 378 #define CONFIG_SYS_INIT_RAM_LOCK 379 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 382 /* The assembler doesn't like typecast */ 383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 384 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 385 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 386 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 387 388 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 389 GENERATED_GBL_DATA_SIZE) 390 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 391 392 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 393 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 394 395 /* Serial Port - controlled on board with jumper J8 396 * open - index 2 397 * shorted - index 1 398 */ 399 #define CONFIG_CONS_INDEX 1 400 #define CONFIG_SYS_NS16550_SERIAL 401 #define CONFIG_SYS_NS16550_REG_SIZE 1 402 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 403 404 #define CONFIG_SYS_BAUDRATE_TABLE \ 405 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 406 407 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 408 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 409 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 410 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 411 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 412 413 /* Video */ 414 #define CONFIG_FSL_DIU_FB 415 #ifdef CONFIG_FSL_DIU_FB 416 #define CONFIG_FSL_DIU_CH7301 417 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 418 #define CONFIG_VIDEO 419 #define CONFIG_CMD_BMP 420 #define CONFIG_CFB_CONSOLE 421 #define CONFIG_VIDEO_SW_CURSOR 422 #define CONFIG_VGA_AS_SINGLE_DEVICE 423 #define CONFIG_VIDEO_LOGO 424 #define CONFIG_VIDEO_BMP_LOGO 425 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 426 /* 427 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 428 * disable empty flash sector detection, which is I/O-intensive. 429 */ 430 #undef CONFIG_SYS_FLASH_EMPTY_INFO 431 #endif 432 433 /* I2C */ 434 #define CONFIG_SYS_I2C 435 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 436 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 437 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 438 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 439 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 440 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 441 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 442 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 443 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 444 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 445 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 446 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 447 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 448 449 #define I2C_MUX_PCA_ADDR 0x77 450 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 451 452 /* I2C bus multiplexer */ 453 #define I2C_MUX_CH_DEFAULT 0x8 454 #define I2C_MUX_CH_DIU 0xC 455 456 /* LDI/DVI Encoder for display */ 457 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 458 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 459 460 /* 461 * RTC configuration 462 */ 463 #define RTC 464 #define CONFIG_RTC_DS3231 1 465 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 466 467 /* 468 * eSPI - Enhanced SPI 469 */ 470 #define CONFIG_SF_DEFAULT_SPEED 10000000 471 #define CONFIG_SF_DEFAULT_MODE 0 472 473 /* 474 * General PCI 475 * Memory space is mapped 1-1, but I/O space must start from 0. 476 */ 477 478 #ifdef CONFIG_PCI 479 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 480 #ifdef CONFIG_PCIE1 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 484 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 485 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 486 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 488 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 489 #endif 490 491 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 492 #ifdef CONFIG_PCIE2 493 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 494 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 495 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 496 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 497 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 498 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 499 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 500 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 501 #endif 502 503 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 504 #ifdef CONFIG_PCIE3 505 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 506 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 508 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 509 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 510 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 511 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 512 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 513 #endif 514 515 /* controller 4, Base address 203000 */ 516 #ifdef CONFIG_PCIE4 517 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 518 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 519 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 520 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 521 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 522 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 523 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 524 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 525 #endif 526 527 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 528 529 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 530 #define CONFIG_DOS_PARTITION 531 #endif /* CONFIG_PCI */ 532 533 /* SATA */ 534 #define CONFIG_FSL_SATA_V2 535 #ifdef CONFIG_FSL_SATA_V2 536 #define CONFIG_LIBATA 537 #define CONFIG_FSL_SATA 538 539 #define CONFIG_SYS_SATA_MAX_DEVICE 2 540 #define CONFIG_SATA1 541 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 542 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 543 #define CONFIG_SATA2 544 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 545 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 546 547 #define CONFIG_LBA48 548 #define CONFIG_CMD_SATA 549 #define CONFIG_DOS_PARTITION 550 #endif 551 552 /* 553 * USB 554 */ 555 #define CONFIG_HAS_FSL_DR_USB 556 557 #ifdef CONFIG_HAS_FSL_DR_USB 558 #define CONFIG_USB_EHCI 559 560 #ifdef CONFIG_USB_EHCI 561 #define CONFIG_USB_STORAGE 562 #define CONFIG_USB_EHCI_FSL 563 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 564 #endif 565 #endif 566 567 #define CONFIG_MMC 568 569 #ifdef CONFIG_MMC 570 #define CONFIG_FSL_ESDHC 571 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 572 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 573 #define CONFIG_GENERIC_MMC 574 #define CONFIG_DOS_PARTITION 575 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 576 #endif 577 578 /* Qman/Bman */ 579 #ifndef CONFIG_NOBQFMAN 580 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 581 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 582 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 583 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 584 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 585 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 586 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 587 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 588 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 589 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 590 CONFIG_SYS_BMAN_CENA_SIZE) 591 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 592 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 593 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 594 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 595 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 596 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 597 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 598 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 599 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 600 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 601 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 602 CONFIG_SYS_QMAN_CENA_SIZE) 603 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 604 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 605 606 #define CONFIG_SYS_DPAA_FMAN 607 #define CONFIG_SYS_DPAA_PME 608 609 #define CONFIG_QE 610 #define CONFIG_U_QE 611 /* Default address of microcode for the Linux Fman driver */ 612 #if defined(CONFIG_SPIFLASH) 613 /* 614 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 615 * env, so we got 0x110000. 616 */ 617 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 618 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 619 #elif defined(CONFIG_SDCARD) 620 /* 621 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 622 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 623 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 624 */ 625 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 626 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 627 #elif defined(CONFIG_NAND) 628 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 629 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 630 #else 631 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 632 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 633 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 634 #endif 635 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 636 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 637 #endif /* CONFIG_NOBQFMAN */ 638 639 #ifdef CONFIG_SYS_DPAA_FMAN 640 #define CONFIG_FMAN_ENET 641 #define CONFIG_PHYLIB_10G 642 #define CONFIG_PHY_VITESSE 643 #define CONFIG_PHY_REALTEK 644 #define CONFIG_PHY_TERANETICS 645 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 646 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 647 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 648 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 649 #endif 650 651 #ifdef CONFIG_FMAN_ENET 652 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 653 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 654 655 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 656 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 657 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 658 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 659 660 #define CONFIG_MII /* MII PHY management */ 661 #define CONFIG_ETHPRIME "FM1@DTSEC1" 662 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 663 #endif 664 665 /* Enable VSC9953 L2 Switch driver */ 666 #define CONFIG_VSC9953 667 #define CONFIG_CMD_ETHSW 668 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 669 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 670 671 /* 672 * Dynamic MTD Partition support with mtdparts 673 */ 674 #ifndef CONFIG_SYS_NO_FLASH 675 #define CONFIG_MTD_DEVICE 676 #define CONFIG_MTD_PARTITIONS 677 #define CONFIG_CMD_MTDPARTS 678 #define CONFIG_FLASH_CFI_MTD 679 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 680 "spi0=spife110000.0" 681 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 682 "128k(dtb),96m(fs),-(user);"\ 683 "fff800000.flash:2m(uboot),9m(kernel),"\ 684 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 685 "2m(uboot),9m(kernel),128k(dtb),-(user)" 686 #endif 687 688 /* 689 * Environment 690 */ 691 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 692 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 693 694 /* 695 * Command line configuration. 696 */ 697 #define CONFIG_CMD_DATE 698 #define CONFIG_CMD_EEPROM 699 #define CONFIG_CMD_ERRATA 700 #define CONFIG_CMD_IRQ 701 #define CONFIG_CMD_REGINFO 702 703 #ifdef CONFIG_PCI 704 #define CONFIG_CMD_PCI 705 #endif 706 707 /* Hash command with SHA acceleration supported in hardware */ 708 #ifdef CONFIG_FSL_CAAM 709 #define CONFIG_CMD_HASH 710 #define CONFIG_SHA_HW_ACCEL 711 #endif 712 713 /* 714 * Miscellaneous configurable options 715 */ 716 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 717 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 718 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 719 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 720 #ifdef CONFIG_CMD_KGDB 721 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 722 #else 723 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 724 #endif 725 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 726 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 727 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 728 729 /* 730 * For booting Linux, the board info and command line data 731 * have to be in the first 64 MB of memory, since this is 732 * the maximum mapped by the Linux kernel during initialization. 733 */ 734 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 735 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 736 737 #ifdef CONFIG_CMD_KGDB 738 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 739 #endif 740 741 /* 742 * Environment Configuration 743 */ 744 #define CONFIG_ROOTPATH "/opt/nfsroot" 745 #define CONFIG_BOOTFILE "uImage" 746 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 747 748 /* default location for tftp and bootm */ 749 #define CONFIG_LOADADDR 1000000 750 751 752 #define CONFIG_BAUDRATE 115200 753 754 #define __USB_PHY_TYPE utmi 755 756 #define CONFIG_EXTRA_ENV_SETTINGS \ 757 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 758 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 759 "netdev=eth0\0" \ 760 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 761 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 762 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 763 "tftpflash=tftpboot $loadaddr $uboot && " \ 764 "protect off $ubootaddr +$filesize && " \ 765 "erase $ubootaddr +$filesize && " \ 766 "cp.b $loadaddr $ubootaddr $filesize && " \ 767 "protect on $ubootaddr +$filesize && " \ 768 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 769 "consoledev=ttyS0\0" \ 770 "ramdiskaddr=2000000\0" \ 771 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 772 "fdtaddr=1e00000\0" \ 773 "fdtfile=t1040qds/t1040qds.dtb\0" \ 774 "bdev=sda3\0" 775 776 #define CONFIG_LINUX \ 777 "setenv bootargs root=/dev/ram rw " \ 778 "console=$consoledev,$baudrate $othbootargs;" \ 779 "setenv ramdiskaddr 0x02000000;" \ 780 "setenv fdtaddr 0x00c00000;" \ 781 "setenv loadaddr 0x1000000;" \ 782 "bootm $loadaddr $ramdiskaddr $fdtaddr" 783 784 #define CONFIG_HDBOOT \ 785 "setenv bootargs root=/dev/$bdev rw " \ 786 "console=$consoledev,$baudrate $othbootargs;" \ 787 "tftp $loadaddr $bootfile;" \ 788 "tftp $fdtaddr $fdtfile;" \ 789 "bootm $loadaddr - $fdtaddr" 790 791 #define CONFIG_NFSBOOTCOMMAND \ 792 "setenv bootargs root=/dev/nfs rw " \ 793 "nfsroot=$serverip:$rootpath " \ 794 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $loadaddr $bootfile;" \ 797 "tftp $fdtaddr $fdtfile;" \ 798 "bootm $loadaddr - $fdtaddr" 799 800 #define CONFIG_RAMBOOTCOMMAND \ 801 "setenv bootargs root=/dev/ram rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "tftp $ramdiskaddr $ramdiskfile;" \ 804 "tftp $loadaddr $bootfile;" \ 805 "tftp $fdtaddr $fdtfile;" \ 806 "bootm $loadaddr $ramdiskaddr $fdtaddr" 807 808 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 809 810 #include <asm/fsl_secure_boot.h> 811 812 #endif /* __CONFIG_H */ 813