1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 40 /* support deep sleep */ 41 #define CONFIG_DEEP_SLEEP 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 49 #define CONFIG_PCI_INDIRECT_BRIDGE 50 #define CONFIG_PCIE1 /* PCIE controller 1 */ 51 #define CONFIG_PCIE2 /* PCIE controller 2 */ 52 #define CONFIG_PCIE3 /* PCIE controller 3 */ 53 #define CONFIG_PCIE4 /* PCIE controller 4 */ 54 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #ifndef CONFIG_MTD_NOR_FLASH 61 #else 62 #define CONFIG_FLASH_CFI_DRIVER 63 #define CONFIG_SYS_FLASH_CFI 64 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 65 #endif 66 67 #ifdef CONFIG_MTD_NOR_FLASH 68 #if defined(CONFIG_SPIFLASH) 69 #define CONFIG_ENV_SPI_BUS 0 70 #define CONFIG_ENV_SPI_CS 0 71 #define CONFIG_ENV_SPI_MAX_HZ 10000000 72 #define CONFIG_ENV_SPI_MODE 0 73 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 74 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 75 #define CONFIG_ENV_SECT_SIZE 0x10000 76 #elif defined(CONFIG_SDCARD) 77 #define CONFIG_SYS_MMC_ENV_DEV 0 78 #define CONFIG_ENV_SIZE 0x2000 79 #define CONFIG_ENV_OFFSET (512 * 1658) 80 #elif defined(CONFIG_NAND) 81 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 82 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 83 #else 84 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 85 #define CONFIG_ENV_SIZE 0x2000 86 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 87 #endif 88 #else /* CONFIG_MTD_NOR_FLASH */ 89 #define CONFIG_ENV_SIZE 0x2000 90 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 91 #endif 92 93 #ifndef __ASSEMBLY__ 94 unsigned long get_board_sys_clk(void); 95 unsigned long get_board_ddr_clk(void); 96 #endif 97 98 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 99 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 100 101 /* 102 * These can be toggled for performance analysis, otherwise use default. 103 */ 104 #define CONFIG_SYS_CACHE_STASHING 105 #define CONFIG_BACKSIDE_L2_CACHE 106 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 107 #define CONFIG_BTB /* toggle branch predition */ 108 #define CONFIG_DDR_ECC 109 #ifdef CONFIG_DDR_ECC 110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 111 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 112 #endif 113 114 #define CONFIG_ENABLE_36BIT_PHYS 115 116 #define CONFIG_ADDR_MAP 117 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 118 119 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 120 #define CONFIG_SYS_MEMTEST_END 0x00400000 121 122 /* 123 * Config the L3 Cache as L3 SRAM 124 */ 125 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 126 127 #define CONFIG_SYS_DCSRBAR 0xf0000000 128 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 129 130 /* EEPROM */ 131 #define CONFIG_ID_EEPROM 132 #define CONFIG_SYS_I2C_EEPROM_NXID 133 #define CONFIG_SYS_EEPROM_BUS_NUM 0 134 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 135 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 136 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 137 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 138 139 /* 140 * DDR Setup 141 */ 142 #define CONFIG_VERY_BIG_RAM 143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 145 146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 147 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 148 149 #define CONFIG_DDR_SPD 150 #define CONFIG_FSL_DDR_INTERACTIVE 151 152 #define CONFIG_SYS_SPD_BUS_NUM 0 153 #define SPD_EEPROM_ADDRESS 0x51 154 155 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 156 157 /* 158 * IFC Definitions 159 */ 160 #define CONFIG_SYS_FLASH_BASE 0xe0000000 161 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 162 163 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 164 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 165 + 0x8000000) | \ 166 CSPR_PORT_SIZE_16 | \ 167 CSPR_MSEL_NOR | \ 168 CSPR_V) 169 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 170 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 171 CSPR_PORT_SIZE_16 | \ 172 CSPR_MSEL_NOR | \ 173 CSPR_V) 174 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 175 176 /* 177 * TDM Definition 178 */ 179 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 180 181 /* NOR Flash Timing Params */ 182 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 183 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 184 FTIM0_NOR_TEADC(0x5) | \ 185 FTIM0_NOR_TEAHC(0x5)) 186 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 187 FTIM1_NOR_TRAD_NOR(0x1A) |\ 188 FTIM1_NOR_TSEQRAD_NOR(0x13)) 189 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 190 FTIM2_NOR_TCH(0x4) | \ 191 FTIM2_NOR_TWPH(0x0E) | \ 192 FTIM2_NOR_TWP(0x1c)) 193 #define CONFIG_SYS_NOR_FTIM3 0x0 194 195 #define CONFIG_SYS_FLASH_QUIET_TEST 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 197 198 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 199 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 200 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 202 203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 205 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 206 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 207 #define QIXIS_BASE 0xffdf0000 208 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 209 #define QIXIS_LBMAP_SWITCH 0x06 210 #define QIXIS_LBMAP_MASK 0x0f 211 #define QIXIS_LBMAP_SHIFT 0 212 #define QIXIS_LBMAP_DFLTBANK 0x00 213 #define QIXIS_LBMAP_ALTBANK 0x04 214 #define QIXIS_RST_CTL_RESET 0x31 215 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 216 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 217 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 218 #define QIXIS_RST_FORCE_MEM 0x01 219 220 #define CONFIG_SYS_CSPR3_EXT (0xf) 221 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 222 | CSPR_PORT_SIZE_8 \ 223 | CSPR_MSEL_GPCM \ 224 | CSPR_V) 225 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 226 #define CONFIG_SYS_CSOR3 0x0 227 /* QIXIS Timing parameters for IFC CS3 */ 228 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 229 FTIM0_GPCM_TEADC(0x0e) | \ 230 FTIM0_GPCM_TEAHC(0x0e)) 231 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 232 FTIM1_GPCM_TRAD(0x3f)) 233 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 234 FTIM2_GPCM_TCH(0x8) | \ 235 FTIM2_GPCM_TWP(0x1f)) 236 #define CONFIG_SYS_CS3_FTIM3 0x0 237 238 #define CONFIG_NAND_FSL_IFC 239 #define CONFIG_SYS_NAND_BASE 0xff800000 240 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 241 242 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 243 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 244 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 245 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 246 | CSPR_V) 247 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 248 249 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 250 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 251 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 252 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 253 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 254 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 255 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 256 257 #define CONFIG_SYS_NAND_ONFI_DETECTION 258 259 /* ONFI NAND Flash mode0 Timing Params */ 260 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 261 FTIM0_NAND_TWP(0x18) | \ 262 FTIM0_NAND_TWCHT(0x07) | \ 263 FTIM0_NAND_TWH(0x0a)) 264 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 265 FTIM1_NAND_TWBE(0x39) | \ 266 FTIM1_NAND_TRR(0x0e) | \ 267 FTIM1_NAND_TRP(0x18)) 268 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 269 FTIM2_NAND_TREH(0x0a) | \ 270 FTIM2_NAND_TWHRE(0x1e)) 271 #define CONFIG_SYS_NAND_FTIM3 0x0 272 273 #define CONFIG_SYS_NAND_DDR_LAW 11 274 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 275 #define CONFIG_SYS_MAX_NAND_DEVICE 1 276 277 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 278 279 #if defined(CONFIG_NAND) 280 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 281 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 282 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 283 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 284 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 285 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 286 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 287 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 288 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 289 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 290 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 291 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 292 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 293 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 294 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 295 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 296 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 297 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 298 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 299 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 300 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 301 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 302 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 303 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 304 #else 305 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 306 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 307 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 314 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 315 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 322 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 323 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 324 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 325 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 326 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 327 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 328 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 329 #endif 330 331 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 332 333 #if defined(CONFIG_RAMBOOT_PBL) 334 #define CONFIG_SYS_RAMBOOT 335 #endif 336 337 #define CONFIG_HWCONFIG 338 339 /* define to use L1 as initial stack */ 340 #define CONFIG_L1_INIT_RAM 341 #define CONFIG_SYS_INIT_RAM_LOCK 342 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 343 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 344 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 345 /* The assembler doesn't like typecast */ 346 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 347 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 348 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 349 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 350 351 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 352 GENERATED_GBL_DATA_SIZE) 353 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 354 355 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 356 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 357 358 /* Serial Port - controlled on board with jumper J8 359 * open - index 2 360 * shorted - index 1 361 */ 362 #define CONFIG_SYS_NS16550_SERIAL 363 #define CONFIG_SYS_NS16550_REG_SIZE 1 364 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 365 366 #define CONFIG_SYS_BAUDRATE_TABLE \ 367 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 368 369 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 370 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 371 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 372 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 373 374 /* Video */ 375 #define CONFIG_FSL_DIU_FB 376 #ifdef CONFIG_FSL_DIU_FB 377 #define CONFIG_FSL_DIU_CH7301 378 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 379 #define CONFIG_VIDEO_LOGO 380 #define CONFIG_VIDEO_BMP_LOGO 381 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 382 /* 383 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 384 * disable empty flash sector detection, which is I/O-intensive. 385 */ 386 #undef CONFIG_SYS_FLASH_EMPTY_INFO 387 #endif 388 389 /* I2C */ 390 #define CONFIG_SYS_I2C 391 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 392 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 393 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 394 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 395 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 396 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 397 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 398 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 399 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 400 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 401 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 402 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 403 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 404 405 #define I2C_MUX_PCA_ADDR 0x77 406 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 407 408 /* I2C bus multiplexer */ 409 #define I2C_MUX_CH_DEFAULT 0x8 410 #define I2C_MUX_CH_DIU 0xC 411 412 /* LDI/DVI Encoder for display */ 413 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 414 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 415 416 /* 417 * RTC configuration 418 */ 419 #define RTC 420 #define CONFIG_RTC_DS3231 1 421 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 422 423 /* 424 * eSPI - Enhanced SPI 425 */ 426 #define CONFIG_SF_DEFAULT_SPEED 10000000 427 #define CONFIG_SF_DEFAULT_MODE 0 428 429 /* 430 * General PCI 431 * Memory space is mapped 1-1, but I/O space must start from 0. 432 */ 433 434 #ifdef CONFIG_PCI 435 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 436 #ifdef CONFIG_PCIE1 437 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 438 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 439 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 440 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 441 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 442 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 443 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 444 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 445 #endif 446 447 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 448 #ifdef CONFIG_PCIE2 449 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 452 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 453 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 454 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 455 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 456 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 457 #endif 458 459 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 460 #ifdef CONFIG_PCIE3 461 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 462 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 463 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 464 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 465 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 466 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 467 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 468 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 469 #endif 470 471 /* controller 4, Base address 203000 */ 472 #ifdef CONFIG_PCIE4 473 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 474 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 475 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 476 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 477 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 478 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 479 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 480 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 481 #endif 482 483 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 484 #endif /* CONFIG_PCI */ 485 486 /* SATA */ 487 #define CONFIG_FSL_SATA_V2 488 #ifdef CONFIG_FSL_SATA_V2 489 #define CONFIG_SYS_SATA_MAX_DEVICE 2 490 #define CONFIG_SATA1 491 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 492 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 493 #define CONFIG_SATA2 494 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 495 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 496 497 #define CONFIG_LBA48 498 #endif 499 500 /* 501 * USB 502 */ 503 #define CONFIG_HAS_FSL_DR_USB 504 505 #ifdef CONFIG_HAS_FSL_DR_USB 506 #ifdef CONFIG_USB_EHCI_HCD 507 #define CONFIG_USB_EHCI_FSL 508 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 509 #endif 510 #endif 511 512 #ifdef CONFIG_MMC 513 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 514 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 515 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 516 #endif 517 518 /* Qman/Bman */ 519 #ifndef CONFIG_NOBQFMAN 520 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 521 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 522 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 523 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 524 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 525 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 526 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 527 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 528 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 529 CONFIG_SYS_BMAN_CENA_SIZE) 530 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 531 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 532 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 533 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 534 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 535 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 536 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 537 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 538 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 539 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 540 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 541 CONFIG_SYS_QMAN_CENA_SIZE) 542 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 543 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 544 545 #define CONFIG_SYS_DPAA_FMAN 546 #define CONFIG_SYS_DPAA_PME 547 548 #define CONFIG_QE 549 /* Default address of microcode for the Linux Fman driver */ 550 #if defined(CONFIG_SPIFLASH) 551 /* 552 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 553 * env, so we got 0x110000. 554 */ 555 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 556 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 557 #elif defined(CONFIG_SDCARD) 558 /* 559 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 560 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 561 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 562 */ 563 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 564 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 565 #elif defined(CONFIG_NAND) 566 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 567 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 568 #else 569 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 570 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 571 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 572 #endif 573 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 574 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 575 #endif /* CONFIG_NOBQFMAN */ 576 577 #ifdef CONFIG_SYS_DPAA_FMAN 578 #define CONFIG_FMAN_ENET 579 #define CONFIG_PHYLIB_10G 580 #define CONFIG_PHY_VITESSE 581 #define CONFIG_PHY_REALTEK 582 #define CONFIG_PHY_TERANETICS 583 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 584 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 585 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 586 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 587 #endif 588 589 #ifdef CONFIG_FMAN_ENET 590 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 591 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 592 593 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 594 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 595 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 596 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 597 598 #define CONFIG_ETHPRIME "FM1@DTSEC1" 599 #endif 600 601 /* Enable VSC9953 L2 Switch driver */ 602 #define CONFIG_VSC9953 603 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 604 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 605 606 /* 607 * Dynamic MTD Partition support with mtdparts 608 */ 609 #ifdef CONFIG_MTD_NOR_FLASH 610 #define CONFIG_FLASH_CFI_MTD 611 #endif 612 613 /* 614 * Environment 615 */ 616 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 617 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 618 619 /* 620 * Miscellaneous configurable options 621 */ 622 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 623 624 /* 625 * For booting Linux, the board info and command line data 626 * have to be in the first 64 MB of memory, since this is 627 * the maximum mapped by the Linux kernel during initialization. 628 */ 629 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 630 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 631 632 #ifdef CONFIG_CMD_KGDB 633 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 634 #endif 635 636 /* 637 * Environment Configuration 638 */ 639 #define CONFIG_ROOTPATH "/opt/nfsroot" 640 #define CONFIG_BOOTFILE "uImage" 641 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 642 643 /* default location for tftp and bootm */ 644 #define CONFIG_LOADADDR 1000000 645 646 #define __USB_PHY_TYPE utmi 647 648 #define CONFIG_EXTRA_ENV_SETTINGS \ 649 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 650 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 651 "netdev=eth0\0" \ 652 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 653 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 654 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 655 "tftpflash=tftpboot $loadaddr $uboot && " \ 656 "protect off $ubootaddr +$filesize && " \ 657 "erase $ubootaddr +$filesize && " \ 658 "cp.b $loadaddr $ubootaddr $filesize && " \ 659 "protect on $ubootaddr +$filesize && " \ 660 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 661 "consoledev=ttyS0\0" \ 662 "ramdiskaddr=2000000\0" \ 663 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 664 "fdtaddr=1e00000\0" \ 665 "fdtfile=t1040qds/t1040qds.dtb\0" \ 666 "bdev=sda3\0" 667 668 #define CONFIG_LINUX \ 669 "setenv bootargs root=/dev/ram rw " \ 670 "console=$consoledev,$baudrate $othbootargs;" \ 671 "setenv ramdiskaddr 0x02000000;" \ 672 "setenv fdtaddr 0x00c00000;" \ 673 "setenv loadaddr 0x1000000;" \ 674 "bootm $loadaddr $ramdiskaddr $fdtaddr" 675 676 #define CONFIG_HDBOOT \ 677 "setenv bootargs root=/dev/$bdev rw " \ 678 "console=$consoledev,$baudrate $othbootargs;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr - $fdtaddr" 682 683 #define CONFIG_NFSBOOTCOMMAND \ 684 "setenv bootargs root=/dev/nfs rw " \ 685 "nfsroot=$serverip:$rootpath " \ 686 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 687 "console=$consoledev,$baudrate $othbootargs;" \ 688 "tftp $loadaddr $bootfile;" \ 689 "tftp $fdtaddr $fdtfile;" \ 690 "bootm $loadaddr - $fdtaddr" 691 692 #define CONFIG_RAMBOOTCOMMAND \ 693 "setenv bootargs root=/dev/ram rw " \ 694 "console=$consoledev,$baudrate $othbootargs;" \ 695 "tftp $ramdiskaddr $ramdiskfile;" \ 696 "tftp $loadaddr $bootfile;" \ 697 "tftp $fdtaddr $fdtfile;" \ 698 "bootm $loadaddr $ramdiskaddr $fdtaddr" 699 700 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 701 702 #include <asm/fsl_secure_boot.h> 703 704 #endif /* __CONFIG_H */ 705