1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 40 /* support deep sleep */ 41 #define CONFIG_DEEP_SLEEP 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 49 #define CONFIG_PCI_INDIRECT_BRIDGE 50 #define CONFIG_PCIE1 /* PCIE controller 1 */ 51 #define CONFIG_PCIE2 /* PCIE controller 2 */ 52 #define CONFIG_PCIE3 /* PCIE controller 3 */ 53 #define CONFIG_PCIE4 /* PCIE controller 4 */ 54 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #ifndef CONFIG_MTD_NOR_FLASH 61 #else 62 #define CONFIG_FLASH_CFI_DRIVER 63 #define CONFIG_SYS_FLASH_CFI 64 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 65 #endif 66 67 #ifdef CONFIG_MTD_NOR_FLASH 68 #if defined(CONFIG_SPIFLASH) 69 #define CONFIG_SYS_EXTRA_ENV_RELOC 70 #define CONFIG_ENV_SPI_BUS 0 71 #define CONFIG_ENV_SPI_CS 0 72 #define CONFIG_ENV_SPI_MAX_HZ 10000000 73 #define CONFIG_ENV_SPI_MODE 0 74 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 75 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 76 #define CONFIG_ENV_SECT_SIZE 0x10000 77 #elif defined(CONFIG_SDCARD) 78 #define CONFIG_SYS_EXTRA_ENV_RELOC 79 #define CONFIG_SYS_MMC_ENV_DEV 0 80 #define CONFIG_ENV_SIZE 0x2000 81 #define CONFIG_ENV_OFFSET (512 * 1658) 82 #elif defined(CONFIG_NAND) 83 #define CONFIG_SYS_EXTRA_ENV_RELOC 84 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 85 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 86 #else 87 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 88 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 90 #endif 91 #else /* CONFIG_MTD_NOR_FLASH */ 92 #define CONFIG_ENV_SIZE 0x2000 93 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 94 #endif 95 96 #ifndef __ASSEMBLY__ 97 unsigned long get_board_sys_clk(void); 98 unsigned long get_board_ddr_clk(void); 99 #endif 100 101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 102 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 103 104 /* 105 * These can be toggled for performance analysis, otherwise use default. 106 */ 107 #define CONFIG_SYS_CACHE_STASHING 108 #define CONFIG_BACKSIDE_L2_CACHE 109 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 110 #define CONFIG_BTB /* toggle branch predition */ 111 #define CONFIG_DDR_ECC 112 #ifdef CONFIG_DDR_ECC 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 114 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 115 #endif 116 117 #define CONFIG_ENABLE_36BIT_PHYS 118 119 #define CONFIG_ADDR_MAP 120 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 121 122 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 123 #define CONFIG_SYS_MEMTEST_END 0x00400000 124 125 /* 126 * Config the L3 Cache as L3 SRAM 127 */ 128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 129 130 #define CONFIG_SYS_DCSRBAR 0xf0000000 131 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 132 133 /* EEPROM */ 134 #define CONFIG_ID_EEPROM 135 #define CONFIG_SYS_I2C_EEPROM_NXID 136 #define CONFIG_SYS_EEPROM_BUS_NUM 0 137 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 139 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 140 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 141 142 /* 143 * DDR Setup 144 */ 145 #define CONFIG_VERY_BIG_RAM 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 148 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 150 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 151 152 #define CONFIG_DDR_SPD 153 #define CONFIG_FSL_DDR_INTERACTIVE 154 155 #define CONFIG_SYS_SPD_BUS_NUM 0 156 #define SPD_EEPROM_ADDRESS 0x51 157 158 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 159 160 /* 161 * IFC Definitions 162 */ 163 #define CONFIG_SYS_FLASH_BASE 0xe0000000 164 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 165 166 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 167 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 168 + 0x8000000) | \ 169 CSPR_PORT_SIZE_16 | \ 170 CSPR_MSEL_NOR | \ 171 CSPR_V) 172 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 173 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 174 CSPR_PORT_SIZE_16 | \ 175 CSPR_MSEL_NOR | \ 176 CSPR_V) 177 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 178 179 /* 180 * TDM Definition 181 */ 182 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 183 184 /* NOR Flash Timing Params */ 185 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 186 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 187 FTIM0_NOR_TEADC(0x5) | \ 188 FTIM0_NOR_TEAHC(0x5)) 189 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 190 FTIM1_NOR_TRAD_NOR(0x1A) |\ 191 FTIM1_NOR_TSEQRAD_NOR(0x13)) 192 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 193 FTIM2_NOR_TCH(0x4) | \ 194 FTIM2_NOR_TWPH(0x0E) | \ 195 FTIM2_NOR_TWP(0x1c)) 196 #define CONFIG_SYS_NOR_FTIM3 0x0 197 198 #define CONFIG_SYS_FLASH_QUIET_TEST 199 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 200 201 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 202 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 203 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 204 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 205 206 #define CONFIG_SYS_FLASH_EMPTY_INFO 207 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 208 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 209 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 210 #define QIXIS_BASE 0xffdf0000 211 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 212 #define QIXIS_LBMAP_SWITCH 0x06 213 #define QIXIS_LBMAP_MASK 0x0f 214 #define QIXIS_LBMAP_SHIFT 0 215 #define QIXIS_LBMAP_DFLTBANK 0x00 216 #define QIXIS_LBMAP_ALTBANK 0x04 217 #define QIXIS_RST_CTL_RESET 0x31 218 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 219 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 220 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 221 #define QIXIS_RST_FORCE_MEM 0x01 222 223 #define CONFIG_SYS_CSPR3_EXT (0xf) 224 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 225 | CSPR_PORT_SIZE_8 \ 226 | CSPR_MSEL_GPCM \ 227 | CSPR_V) 228 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 229 #define CONFIG_SYS_CSOR3 0x0 230 /* QIXIS Timing parameters for IFC CS3 */ 231 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 232 FTIM0_GPCM_TEADC(0x0e) | \ 233 FTIM0_GPCM_TEAHC(0x0e)) 234 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 235 FTIM1_GPCM_TRAD(0x3f)) 236 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 237 FTIM2_GPCM_TCH(0x8) | \ 238 FTIM2_GPCM_TWP(0x1f)) 239 #define CONFIG_SYS_CS3_FTIM3 0x0 240 241 #define CONFIG_NAND_FSL_IFC 242 #define CONFIG_SYS_NAND_BASE 0xff800000 243 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 244 245 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 246 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 247 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 248 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 249 | CSPR_V) 250 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 251 252 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 253 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 254 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 255 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 256 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 257 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 258 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 259 260 #define CONFIG_SYS_NAND_ONFI_DETECTION 261 262 /* ONFI NAND Flash mode0 Timing Params */ 263 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 264 FTIM0_NAND_TWP(0x18) | \ 265 FTIM0_NAND_TWCHT(0x07) | \ 266 FTIM0_NAND_TWH(0x0a)) 267 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 268 FTIM1_NAND_TWBE(0x39) | \ 269 FTIM1_NAND_TRR(0x0e) | \ 270 FTIM1_NAND_TRP(0x18)) 271 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 272 FTIM2_NAND_TREH(0x0a) | \ 273 FTIM2_NAND_TWHRE(0x1e)) 274 #define CONFIG_SYS_NAND_FTIM3 0x0 275 276 #define CONFIG_SYS_NAND_DDR_LAW 11 277 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 278 #define CONFIG_SYS_MAX_NAND_DEVICE 1 279 280 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 281 282 #if defined(CONFIG_NAND) 283 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 284 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 285 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 286 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 287 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 288 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 289 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 290 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 291 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 292 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 293 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 294 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 295 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 296 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 297 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 298 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 299 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 300 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 301 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 302 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 303 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 304 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 305 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 306 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 307 #else 308 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 309 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 310 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 311 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 312 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 313 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 314 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 315 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 316 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 317 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 318 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 319 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 320 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 321 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 322 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 323 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 324 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 325 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 326 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 327 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 328 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 329 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 330 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 331 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 332 #endif 333 334 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 335 336 #if defined(CONFIG_RAMBOOT_PBL) 337 #define CONFIG_SYS_RAMBOOT 338 #endif 339 340 #define CONFIG_MISC_INIT_R 341 342 #define CONFIG_HWCONFIG 343 344 /* define to use L1 as initial stack */ 345 #define CONFIG_L1_INIT_RAM 346 #define CONFIG_SYS_INIT_RAM_LOCK 347 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 348 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 350 /* The assembler doesn't like typecast */ 351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 352 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 353 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 354 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 355 356 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 357 GENERATED_GBL_DATA_SIZE) 358 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 359 360 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 361 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 362 363 /* Serial Port - controlled on board with jumper J8 364 * open - index 2 365 * shorted - index 1 366 */ 367 #define CONFIG_SYS_NS16550_SERIAL 368 #define CONFIG_SYS_NS16550_REG_SIZE 1 369 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 370 371 #define CONFIG_SYS_BAUDRATE_TABLE \ 372 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 373 374 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 375 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 376 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 377 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 378 379 /* Video */ 380 #define CONFIG_FSL_DIU_FB 381 #ifdef CONFIG_FSL_DIU_FB 382 #define CONFIG_FSL_DIU_CH7301 383 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 384 #define CONFIG_VIDEO_LOGO 385 #define CONFIG_VIDEO_BMP_LOGO 386 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 387 /* 388 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 389 * disable empty flash sector detection, which is I/O-intensive. 390 */ 391 #undef CONFIG_SYS_FLASH_EMPTY_INFO 392 #endif 393 394 /* I2C */ 395 #define CONFIG_SYS_I2C 396 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 397 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 398 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 399 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 400 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 401 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 402 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 404 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 406 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 407 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 408 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 409 410 #define I2C_MUX_PCA_ADDR 0x77 411 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 412 413 /* I2C bus multiplexer */ 414 #define I2C_MUX_CH_DEFAULT 0x8 415 #define I2C_MUX_CH_DIU 0xC 416 417 /* LDI/DVI Encoder for display */ 418 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 419 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 420 421 /* 422 * RTC configuration 423 */ 424 #define RTC 425 #define CONFIG_RTC_DS3231 1 426 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 427 428 /* 429 * eSPI - Enhanced SPI 430 */ 431 #define CONFIG_SF_DEFAULT_SPEED 10000000 432 #define CONFIG_SF_DEFAULT_MODE 0 433 434 /* 435 * General PCI 436 * Memory space is mapped 1-1, but I/O space must start from 0. 437 */ 438 439 #ifdef CONFIG_PCI 440 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 441 #ifdef CONFIG_PCIE1 442 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 443 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 446 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 449 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 450 #endif 451 452 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 453 #ifdef CONFIG_PCIE2 454 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 456 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 457 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 458 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 459 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 460 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 461 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 462 #endif 463 464 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 465 #ifdef CONFIG_PCIE3 466 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 469 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 470 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 471 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 472 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 473 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 474 #endif 475 476 /* controller 4, Base address 203000 */ 477 #ifdef CONFIG_PCIE4 478 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 479 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 480 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 481 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 482 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 483 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 484 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 485 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 486 #endif 487 488 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 489 #endif /* CONFIG_PCI */ 490 491 /* SATA */ 492 #define CONFIG_FSL_SATA_V2 493 #ifdef CONFIG_FSL_SATA_V2 494 #define CONFIG_SYS_SATA_MAX_DEVICE 2 495 #define CONFIG_SATA1 496 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 497 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 498 #define CONFIG_SATA2 499 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 500 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 501 502 #define CONFIG_LBA48 503 #endif 504 505 /* 506 * USB 507 */ 508 #define CONFIG_HAS_FSL_DR_USB 509 510 #ifdef CONFIG_HAS_FSL_DR_USB 511 #ifdef CONFIG_USB_EHCI_HCD 512 #define CONFIG_USB_EHCI_FSL 513 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 514 #endif 515 #endif 516 517 #ifdef CONFIG_MMC 518 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 519 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 520 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 521 #endif 522 523 /* Qman/Bman */ 524 #ifndef CONFIG_NOBQFMAN 525 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 526 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 527 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 528 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 529 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 530 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 531 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 532 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 533 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 534 CONFIG_SYS_BMAN_CENA_SIZE) 535 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 536 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 537 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 538 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 539 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 540 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 541 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 542 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 543 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 544 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 545 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 546 CONFIG_SYS_QMAN_CENA_SIZE) 547 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 548 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 549 550 #define CONFIG_SYS_DPAA_FMAN 551 #define CONFIG_SYS_DPAA_PME 552 553 #define CONFIG_QE 554 #define CONFIG_U_QE 555 /* Default address of microcode for the Linux Fman driver */ 556 #if defined(CONFIG_SPIFLASH) 557 /* 558 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 559 * env, so we got 0x110000. 560 */ 561 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 562 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 563 #elif defined(CONFIG_SDCARD) 564 /* 565 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 566 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 567 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 568 */ 569 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 570 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 571 #elif defined(CONFIG_NAND) 572 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 573 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 574 #else 575 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 576 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 577 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 578 #endif 579 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 580 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 581 #endif /* CONFIG_NOBQFMAN */ 582 583 #ifdef CONFIG_SYS_DPAA_FMAN 584 #define CONFIG_FMAN_ENET 585 #define CONFIG_PHYLIB_10G 586 #define CONFIG_PHY_VITESSE 587 #define CONFIG_PHY_REALTEK 588 #define CONFIG_PHY_TERANETICS 589 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 590 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 591 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 592 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 593 #endif 594 595 #ifdef CONFIG_FMAN_ENET 596 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 597 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 598 599 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 600 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 601 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 602 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 603 604 #define CONFIG_MII /* MII PHY management */ 605 #define CONFIG_ETHPRIME "FM1@DTSEC1" 606 #endif 607 608 /* Enable VSC9953 L2 Switch driver */ 609 #define CONFIG_VSC9953 610 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 611 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 612 613 /* 614 * Dynamic MTD Partition support with mtdparts 615 */ 616 #ifdef CONFIG_MTD_NOR_FLASH 617 #define CONFIG_MTD_DEVICE 618 #define CONFIG_MTD_PARTITIONS 619 #define CONFIG_FLASH_CFI_MTD 620 #endif 621 622 /* 623 * Environment 624 */ 625 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 626 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 627 628 /* 629 * Miscellaneous configurable options 630 */ 631 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 632 633 /* 634 * For booting Linux, the board info and command line data 635 * have to be in the first 64 MB of memory, since this is 636 * the maximum mapped by the Linux kernel during initialization. 637 */ 638 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 639 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 640 641 #ifdef CONFIG_CMD_KGDB 642 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 643 #endif 644 645 /* 646 * Environment Configuration 647 */ 648 #define CONFIG_ROOTPATH "/opt/nfsroot" 649 #define CONFIG_BOOTFILE "uImage" 650 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 651 652 /* default location for tftp and bootm */ 653 #define CONFIG_LOADADDR 1000000 654 655 #define __USB_PHY_TYPE utmi 656 657 #define CONFIG_EXTRA_ENV_SETTINGS \ 658 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 659 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 660 "netdev=eth0\0" \ 661 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 662 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 663 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 664 "tftpflash=tftpboot $loadaddr $uboot && " \ 665 "protect off $ubootaddr +$filesize && " \ 666 "erase $ubootaddr +$filesize && " \ 667 "cp.b $loadaddr $ubootaddr $filesize && " \ 668 "protect on $ubootaddr +$filesize && " \ 669 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 670 "consoledev=ttyS0\0" \ 671 "ramdiskaddr=2000000\0" \ 672 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 673 "fdtaddr=1e00000\0" \ 674 "fdtfile=t1040qds/t1040qds.dtb\0" \ 675 "bdev=sda3\0" 676 677 #define CONFIG_LINUX \ 678 "setenv bootargs root=/dev/ram rw " \ 679 "console=$consoledev,$baudrate $othbootargs;" \ 680 "setenv ramdiskaddr 0x02000000;" \ 681 "setenv fdtaddr 0x00c00000;" \ 682 "setenv loadaddr 0x1000000;" \ 683 "bootm $loadaddr $ramdiskaddr $fdtaddr" 684 685 #define CONFIG_HDBOOT \ 686 "setenv bootargs root=/dev/$bdev rw " \ 687 "console=$consoledev,$baudrate $othbootargs;" \ 688 "tftp $loadaddr $bootfile;" \ 689 "tftp $fdtaddr $fdtfile;" \ 690 "bootm $loadaddr - $fdtaddr" 691 692 #define CONFIG_NFSBOOTCOMMAND \ 693 "setenv bootargs root=/dev/nfs rw " \ 694 "nfsroot=$serverip:$rootpath " \ 695 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 696 "console=$consoledev,$baudrate $othbootargs;" \ 697 "tftp $loadaddr $bootfile;" \ 698 "tftp $fdtaddr $fdtfile;" \ 699 "bootm $loadaddr - $fdtaddr" 700 701 #define CONFIG_RAMBOOTCOMMAND \ 702 "setenv bootargs root=/dev/ram rw " \ 703 "console=$consoledev,$baudrate $othbootargs;" \ 704 "tftp $ramdiskaddr $ramdiskfile;" \ 705 "tftp $loadaddr $bootfile;" \ 706 "tftp $fdtaddr $fdtfile;" \ 707 "bootm $loadaddr $ramdiskaddr $fdtaddr" 708 709 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 710 711 #include <asm/fsl_secure_boot.h> 712 713 #endif /* __CONFIG_H */ 714