1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 /* support deep sleep */ 42 #define CONFIG_DEEP_SLEEP 43 44 #ifndef CONFIG_SYS_TEXT_BASE 45 #define CONFIG_SYS_TEXT_BASE 0xeff40000 46 #endif 47 48 #ifndef CONFIG_RESET_VECTOR_ADDRESS 49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #endif 51 52 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 53 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 54 #define CONFIG_FSL_IFC /* Enable IFC Support */ 55 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 56 #define CONFIG_PCI_INDIRECT_BRIDGE 57 #define CONFIG_PCIE1 /* PCIE controller 1 */ 58 #define CONFIG_PCIE2 /* PCIE controller 2 */ 59 #define CONFIG_PCIE3 /* PCIE controller 3 */ 60 #define CONFIG_PCIE4 /* PCIE controller 4 */ 61 62 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 63 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 64 65 #define CONFIG_ENV_OVERWRITE 66 67 #ifdef CONFIG_SYS_NO_FLASH 68 #define CONFIG_ENV_IS_NOWHERE 69 #else 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 #endif 74 75 #ifndef CONFIG_SYS_NO_FLASH 76 #if defined(CONFIG_SPIFLASH) 77 #define CONFIG_SYS_EXTRA_ENV_RELOC 78 #define CONFIG_ENV_IS_IN_SPI_FLASH 79 #define CONFIG_ENV_SPI_BUS 0 80 #define CONFIG_ENV_SPI_CS 0 81 #define CONFIG_ENV_SPI_MAX_HZ 10000000 82 #define CONFIG_ENV_SPI_MODE 0 83 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 84 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 85 #define CONFIG_ENV_SECT_SIZE 0x10000 86 #elif defined(CONFIG_SDCARD) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_MMC 89 #define CONFIG_SYS_MMC_ENV_DEV 0 90 #define CONFIG_ENV_SIZE 0x2000 91 #define CONFIG_ENV_OFFSET (512 * 1658) 92 #elif defined(CONFIG_NAND) 93 #define CONFIG_SYS_EXTRA_ENV_RELOC 94 #define CONFIG_ENV_IS_IN_NAND 95 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 96 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 97 #else 98 #define CONFIG_ENV_IS_IN_FLASH 99 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 102 #endif 103 #else /* CONFIG_SYS_NO_FLASH */ 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 106 #endif 107 108 #ifndef __ASSEMBLY__ 109 unsigned long get_board_sys_clk(void); 110 unsigned long get_board_ddr_clk(void); 111 #endif 112 113 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 114 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 115 116 /* 117 * These can be toggled for performance analysis, otherwise use default. 118 */ 119 #define CONFIG_SYS_CACHE_STASHING 120 #define CONFIG_BACKSIDE_L2_CACHE 121 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 122 #define CONFIG_BTB /* toggle branch predition */ 123 #define CONFIG_DDR_ECC 124 #ifdef CONFIG_DDR_ECC 125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 126 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 127 #endif 128 129 #define CONFIG_ENABLE_36BIT_PHYS 130 131 #define CONFIG_ADDR_MAP 132 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 133 134 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 135 #define CONFIG_SYS_MEMTEST_END 0x00400000 136 #define CONFIG_SYS_ALT_MEMTEST 137 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 138 139 /* 140 * Config the L3 Cache as L3 SRAM 141 */ 142 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 143 144 #define CONFIG_SYS_DCSRBAR 0xf0000000 145 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 146 147 /* EEPROM */ 148 #define CONFIG_ID_EEPROM 149 #define CONFIG_SYS_I2C_EEPROM_NXID 150 #define CONFIG_SYS_EEPROM_BUS_NUM 0 151 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 155 156 /* 157 * DDR Setup 158 */ 159 #define CONFIG_VERY_BIG_RAM 160 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 162 163 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 164 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 165 166 #define CONFIG_DDR_SPD 167 #define CONFIG_FSL_DDR_INTERACTIVE 168 169 #define CONFIG_SYS_SPD_BUS_NUM 0 170 #define SPD_EEPROM_ADDRESS 0x51 171 172 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 173 174 /* 175 * IFC Definitions 176 */ 177 #define CONFIG_SYS_FLASH_BASE 0xe0000000 178 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 179 180 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 181 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 182 + 0x8000000) | \ 183 CSPR_PORT_SIZE_16 | \ 184 CSPR_MSEL_NOR | \ 185 CSPR_V) 186 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 187 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 188 CSPR_PORT_SIZE_16 | \ 189 CSPR_MSEL_NOR | \ 190 CSPR_V) 191 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 192 193 /* 194 * TDM Definition 195 */ 196 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 197 198 /* NOR Flash Timing Params */ 199 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 201 FTIM0_NOR_TEADC(0x5) | \ 202 FTIM0_NOR_TEAHC(0x5)) 203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 204 FTIM1_NOR_TRAD_NOR(0x1A) |\ 205 FTIM1_NOR_TSEQRAD_NOR(0x13)) 206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 207 FTIM2_NOR_TCH(0x4) | \ 208 FTIM2_NOR_TWPH(0x0E) | \ 209 FTIM2_NOR_TWP(0x1c)) 210 #define CONFIG_SYS_NOR_FTIM3 0x0 211 212 #define CONFIG_SYS_FLASH_QUIET_TEST 213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 214 215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 216 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 219 220 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 222 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 223 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 224 #define QIXIS_BASE 0xffdf0000 225 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 226 #define QIXIS_LBMAP_SWITCH 0x06 227 #define QIXIS_LBMAP_MASK 0x0f 228 #define QIXIS_LBMAP_SHIFT 0 229 #define QIXIS_LBMAP_DFLTBANK 0x00 230 #define QIXIS_LBMAP_ALTBANK 0x04 231 #define QIXIS_RST_CTL_RESET 0x31 232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 235 #define QIXIS_RST_FORCE_MEM 0x01 236 237 #define CONFIG_SYS_CSPR3_EXT (0xf) 238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 239 | CSPR_PORT_SIZE_8 \ 240 | CSPR_MSEL_GPCM \ 241 | CSPR_V) 242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 243 #define CONFIG_SYS_CSOR3 0x0 244 /* QIXIS Timing parameters for IFC CS3 */ 245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 246 FTIM0_GPCM_TEADC(0x0e) | \ 247 FTIM0_GPCM_TEAHC(0x0e)) 248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 249 FTIM1_GPCM_TRAD(0x3f)) 250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 251 FTIM2_GPCM_TCH(0x8) | \ 252 FTIM2_GPCM_TWP(0x1f)) 253 #define CONFIG_SYS_CS3_FTIM3 0x0 254 255 #define CONFIG_NAND_FSL_IFC 256 #define CONFIG_SYS_NAND_BASE 0xff800000 257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 258 259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 262 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 263 | CSPR_V) 264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 265 266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 273 274 #define CONFIG_SYS_NAND_ONFI_DETECTION 275 276 /* ONFI NAND Flash mode0 Timing Params */ 277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 278 FTIM0_NAND_TWP(0x18) | \ 279 FTIM0_NAND_TWCHT(0x07) | \ 280 FTIM0_NAND_TWH(0x0a)) 281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 282 FTIM1_NAND_TWBE(0x39) | \ 283 FTIM1_NAND_TRR(0x0e) | \ 284 FTIM1_NAND_TRP(0x18)) 285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 286 FTIM2_NAND_TREH(0x0a) | \ 287 FTIM2_NAND_TWHRE(0x1e)) 288 #define CONFIG_SYS_NAND_FTIM3 0x0 289 290 #define CONFIG_SYS_NAND_DDR_LAW 11 291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 293 #define CONFIG_CMD_NAND 294 295 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 296 297 #if defined(CONFIG_NAND) 298 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 299 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 300 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 301 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 302 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 303 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 304 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 305 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 306 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 315 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 316 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #else 323 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 324 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 325 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 332 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 333 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 340 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 341 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 342 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 343 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 344 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 345 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 346 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 347 #endif 348 349 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 350 351 #if defined(CONFIG_RAMBOOT_PBL) 352 #define CONFIG_SYS_RAMBOOT 353 #endif 354 355 #define CONFIG_BOARD_EARLY_INIT_R 356 #define CONFIG_MISC_INIT_R 357 358 #define CONFIG_HWCONFIG 359 360 /* define to use L1 as initial stack */ 361 #define CONFIG_L1_INIT_RAM 362 #define CONFIG_SYS_INIT_RAM_LOCK 363 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 364 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 366 /* The assembler doesn't like typecast */ 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 368 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 369 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 370 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 371 372 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 373 GENERATED_GBL_DATA_SIZE) 374 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 375 376 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 377 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 378 379 /* Serial Port - controlled on board with jumper J8 380 * open - index 2 381 * shorted - index 1 382 */ 383 #define CONFIG_CONS_INDEX 1 384 #define CONFIG_SYS_NS16550_SERIAL 385 #define CONFIG_SYS_NS16550_REG_SIZE 1 386 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 387 388 #define CONFIG_SYS_BAUDRATE_TABLE \ 389 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 390 391 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 392 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 393 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 394 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 395 396 /* Video */ 397 #define CONFIG_FSL_DIU_FB 398 #ifdef CONFIG_FSL_DIU_FB 399 #define CONFIG_FSL_DIU_CH7301 400 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 401 #define CONFIG_CMD_BMP 402 #define CONFIG_VIDEO_LOGO 403 #define CONFIG_VIDEO_BMP_LOGO 404 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 405 /* 406 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 407 * disable empty flash sector detection, which is I/O-intensive. 408 */ 409 #undef CONFIG_SYS_FLASH_EMPTY_INFO 410 #endif 411 412 /* I2C */ 413 #define CONFIG_SYS_I2C 414 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 415 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 416 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 417 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 418 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 419 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 421 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 422 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 424 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 425 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 426 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 427 428 #define I2C_MUX_PCA_ADDR 0x77 429 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 430 431 /* I2C bus multiplexer */ 432 #define I2C_MUX_CH_DEFAULT 0x8 433 #define I2C_MUX_CH_DIU 0xC 434 435 /* LDI/DVI Encoder for display */ 436 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 437 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 438 439 /* 440 * RTC configuration 441 */ 442 #define RTC 443 #define CONFIG_RTC_DS3231 1 444 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 445 446 /* 447 * eSPI - Enhanced SPI 448 */ 449 #define CONFIG_SF_DEFAULT_SPEED 10000000 450 #define CONFIG_SF_DEFAULT_MODE 0 451 452 /* 453 * General PCI 454 * Memory space is mapped 1-1, but I/O space must start from 0. 455 */ 456 457 #ifdef CONFIG_PCI 458 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 459 #ifdef CONFIG_PCIE1 460 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 461 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 462 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 463 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 464 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 465 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 466 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 467 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 468 #endif 469 470 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 471 #ifdef CONFIG_PCIE2 472 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 473 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 474 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 475 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 476 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 477 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 478 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 479 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 480 #endif 481 482 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 483 #ifdef CONFIG_PCIE3 484 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 485 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 486 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 487 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 488 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 489 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 490 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 491 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 492 #endif 493 494 /* controller 4, Base address 203000 */ 495 #ifdef CONFIG_PCIE4 496 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 497 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 498 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 499 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 500 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 501 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 502 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 503 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 504 #endif 505 506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 507 #endif /* CONFIG_PCI */ 508 509 /* SATA */ 510 #define CONFIG_FSL_SATA_V2 511 #ifdef CONFIG_FSL_SATA_V2 512 #define CONFIG_LIBATA 513 #define CONFIG_FSL_SATA 514 515 #define CONFIG_SYS_SATA_MAX_DEVICE 2 516 #define CONFIG_SATA1 517 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 518 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 519 #define CONFIG_SATA2 520 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 521 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 522 523 #define CONFIG_LBA48 524 #define CONFIG_CMD_SATA 525 #endif 526 527 /* 528 * USB 529 */ 530 #define CONFIG_HAS_FSL_DR_USB 531 532 #ifdef CONFIG_HAS_FSL_DR_USB 533 #define CONFIG_USB_EHCI 534 535 #ifdef CONFIG_USB_EHCI 536 #define CONFIG_USB_EHCI_FSL 537 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 538 #endif 539 #endif 540 541 #ifdef CONFIG_MMC 542 #define CONFIG_FSL_ESDHC 543 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 544 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 545 #define CONFIG_GENERIC_MMC 546 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 547 #endif 548 549 /* Qman/Bman */ 550 #ifndef CONFIG_NOBQFMAN 551 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 552 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 553 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 554 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 555 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 556 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 557 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 558 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 559 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 560 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 561 CONFIG_SYS_BMAN_CENA_SIZE) 562 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 563 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 564 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 565 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 566 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 567 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 568 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 569 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 570 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 571 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 573 CONFIG_SYS_QMAN_CENA_SIZE) 574 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 575 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 576 577 #define CONFIG_SYS_DPAA_FMAN 578 #define CONFIG_SYS_DPAA_PME 579 580 #define CONFIG_QE 581 #define CONFIG_U_QE 582 /* Default address of microcode for the Linux Fman driver */ 583 #if defined(CONFIG_SPIFLASH) 584 /* 585 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 586 * env, so we got 0x110000. 587 */ 588 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 589 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 590 #elif defined(CONFIG_SDCARD) 591 /* 592 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 593 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 594 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 595 */ 596 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 597 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 598 #elif defined(CONFIG_NAND) 599 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 600 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 601 #else 602 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 603 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 604 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 605 #endif 606 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 607 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 608 #endif /* CONFIG_NOBQFMAN */ 609 610 #ifdef CONFIG_SYS_DPAA_FMAN 611 #define CONFIG_FMAN_ENET 612 #define CONFIG_PHYLIB_10G 613 #define CONFIG_PHY_VITESSE 614 #define CONFIG_PHY_REALTEK 615 #define CONFIG_PHY_TERANETICS 616 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 617 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 618 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 619 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 620 #endif 621 622 #ifdef CONFIG_FMAN_ENET 623 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 624 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 625 626 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 627 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 628 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 629 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 630 631 #define CONFIG_MII /* MII PHY management */ 632 #define CONFIG_ETHPRIME "FM1@DTSEC1" 633 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 634 #endif 635 636 /* Enable VSC9953 L2 Switch driver */ 637 #define CONFIG_VSC9953 638 #define CONFIG_CMD_ETHSW 639 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 640 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 641 642 /* 643 * Dynamic MTD Partition support with mtdparts 644 */ 645 #ifndef CONFIG_SYS_NO_FLASH 646 #define CONFIG_MTD_DEVICE 647 #define CONFIG_MTD_PARTITIONS 648 #define CONFIG_CMD_MTDPARTS 649 #define CONFIG_FLASH_CFI_MTD 650 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 651 "spi0=spife110000.0" 652 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 653 "128k(dtb),96m(fs),-(user);"\ 654 "fff800000.flash:2m(uboot),9m(kernel),"\ 655 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 656 "2m(uboot),9m(kernel),128k(dtb),-(user)" 657 #endif 658 659 /* 660 * Environment 661 */ 662 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 663 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 664 665 /* 666 * Command line configuration. 667 */ 668 #define CONFIG_CMD_DATE 669 #define CONFIG_CMD_EEPROM 670 #define CONFIG_CMD_ERRATA 671 #define CONFIG_CMD_IRQ 672 #define CONFIG_CMD_REGINFO 673 674 #ifdef CONFIG_PCI 675 #define CONFIG_CMD_PCI 676 #endif 677 678 /* Hash command with SHA acceleration supported in hardware */ 679 #ifdef CONFIG_FSL_CAAM 680 #define CONFIG_CMD_HASH 681 #define CONFIG_SHA_HW_ACCEL 682 #endif 683 684 /* 685 * Miscellaneous configurable options 686 */ 687 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 688 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 689 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 690 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 691 #ifdef CONFIG_CMD_KGDB 692 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 693 #else 694 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 695 #endif 696 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 697 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 698 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 699 700 /* 701 * For booting Linux, the board info and command line data 702 * have to be in the first 64 MB of memory, since this is 703 * the maximum mapped by the Linux kernel during initialization. 704 */ 705 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 706 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 707 708 #ifdef CONFIG_CMD_KGDB 709 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 710 #endif 711 712 /* 713 * Environment Configuration 714 */ 715 #define CONFIG_ROOTPATH "/opt/nfsroot" 716 #define CONFIG_BOOTFILE "uImage" 717 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 718 719 /* default location for tftp and bootm */ 720 #define CONFIG_LOADADDR 1000000 721 722 723 #define CONFIG_BAUDRATE 115200 724 725 #define __USB_PHY_TYPE utmi 726 727 #define CONFIG_EXTRA_ENV_SETTINGS \ 728 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 729 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 730 "netdev=eth0\0" \ 731 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 732 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 733 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 734 "tftpflash=tftpboot $loadaddr $uboot && " \ 735 "protect off $ubootaddr +$filesize && " \ 736 "erase $ubootaddr +$filesize && " \ 737 "cp.b $loadaddr $ubootaddr $filesize && " \ 738 "protect on $ubootaddr +$filesize && " \ 739 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 740 "consoledev=ttyS0\0" \ 741 "ramdiskaddr=2000000\0" \ 742 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 743 "fdtaddr=1e00000\0" \ 744 "fdtfile=t1040qds/t1040qds.dtb\0" \ 745 "bdev=sda3\0" 746 747 #define CONFIG_LINUX \ 748 "setenv bootargs root=/dev/ram rw " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "setenv ramdiskaddr 0x02000000;" \ 751 "setenv fdtaddr 0x00c00000;" \ 752 "setenv loadaddr 0x1000000;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_HDBOOT \ 756 "setenv bootargs root=/dev/$bdev rw " \ 757 "console=$consoledev,$baudrate $othbootargs;" \ 758 "tftp $loadaddr $bootfile;" \ 759 "tftp $fdtaddr $fdtfile;" \ 760 "bootm $loadaddr - $fdtaddr" 761 762 #define CONFIG_NFSBOOTCOMMAND \ 763 "setenv bootargs root=/dev/nfs rw " \ 764 "nfsroot=$serverip:$rootpath " \ 765 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 766 "console=$consoledev,$baudrate $othbootargs;" \ 767 "tftp $loadaddr $bootfile;" \ 768 "tftp $fdtaddr $fdtfile;" \ 769 "bootm $loadaddr - $fdtaddr" 770 771 #define CONFIG_RAMBOOTCOMMAND \ 772 "setenv bootargs root=/dev/ram rw " \ 773 "console=$consoledev,$baudrate $othbootargs;" \ 774 "tftp $ramdiskaddr $ramdiskfile;" \ 775 "tftp $loadaddr $bootfile;" \ 776 "tftp $fdtaddr $fdtfile;" \ 777 "bootm $loadaddr $ramdiskaddr $fdtaddr" 778 779 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 780 781 #include <asm/fsl_secure_boot.h> 782 783 #endif /* __CONFIG_H */ 784