1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 /* support deep sleep */ 42 #define CONFIG_DEEP_SLEEP 43 44 #ifndef CONFIG_SYS_TEXT_BASE 45 #define CONFIG_SYS_TEXT_BASE 0xeff40000 46 #endif 47 48 #ifndef CONFIG_RESET_VECTOR_ADDRESS 49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #endif 51 52 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 53 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 54 #define CONFIG_PCI_INDIRECT_BRIDGE 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_PCIE2 /* PCIE controller 2 */ 57 #define CONFIG_PCIE3 /* PCIE controller 3 */ 58 #define CONFIG_PCIE4 /* PCIE controller 4 */ 59 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_ENV_OVERWRITE 64 65 #ifndef CONFIG_MTD_NOR_FLASH 66 #else 67 #define CONFIG_FLASH_CFI_DRIVER 68 #define CONFIG_SYS_FLASH_CFI 69 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 70 #endif 71 72 #ifdef CONFIG_MTD_NOR_FLASH 73 #if defined(CONFIG_SPIFLASH) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_ENV_SPI_BUS 0 76 #define CONFIG_ENV_SPI_CS 0 77 #define CONFIG_ENV_SPI_MAX_HZ 10000000 78 #define CONFIG_ENV_SPI_MODE 0 79 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 80 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 81 #define CONFIG_ENV_SECT_SIZE 0x10000 82 #elif defined(CONFIG_SDCARD) 83 #define CONFIG_SYS_EXTRA_ENV_RELOC 84 #define CONFIG_SYS_MMC_ENV_DEV 0 85 #define CONFIG_ENV_SIZE 0x2000 86 #define CONFIG_ENV_OFFSET (512 * 1658) 87 #elif defined(CONFIG_NAND) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 90 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 91 #else 92 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 95 #endif 96 #else /* CONFIG_MTD_NOR_FLASH */ 97 #define CONFIG_ENV_SIZE 0x2000 98 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 99 #endif 100 101 #ifndef __ASSEMBLY__ 102 unsigned long get_board_sys_clk(void); 103 unsigned long get_board_ddr_clk(void); 104 #endif 105 106 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 107 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_BACKSIDE_L2_CACHE 114 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 115 #define CONFIG_BTB /* toggle branch predition */ 116 #define CONFIG_DDR_ECC 117 #ifdef CONFIG_DDR_ECC 118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 120 #endif 121 122 #define CONFIG_ENABLE_36BIT_PHYS 123 124 #define CONFIG_ADDR_MAP 125 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 126 127 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_END 0x00400000 129 #define CONFIG_SYS_ALT_MEMTEST 130 131 /* 132 * Config the L3 Cache as L3 SRAM 133 */ 134 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 135 136 #define CONFIG_SYS_DCSRBAR 0xf0000000 137 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 138 139 /* EEPROM */ 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_SYS_EEPROM_BUS_NUM 0 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 146 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 147 148 /* 149 * DDR Setup 150 */ 151 #define CONFIG_VERY_BIG_RAM 152 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 153 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 154 155 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 156 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 157 158 #define CONFIG_DDR_SPD 159 #define CONFIG_FSL_DDR_INTERACTIVE 160 161 #define CONFIG_SYS_SPD_BUS_NUM 0 162 #define SPD_EEPROM_ADDRESS 0x51 163 164 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 165 166 /* 167 * IFC Definitions 168 */ 169 #define CONFIG_SYS_FLASH_BASE 0xe0000000 170 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 171 172 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 173 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 174 + 0x8000000) | \ 175 CSPR_PORT_SIZE_16 | \ 176 CSPR_MSEL_NOR | \ 177 CSPR_V) 178 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 179 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 180 CSPR_PORT_SIZE_16 | \ 181 CSPR_MSEL_NOR | \ 182 CSPR_V) 183 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 184 185 /* 186 * TDM Definition 187 */ 188 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 189 190 /* NOR Flash Timing Params */ 191 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 192 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 193 FTIM0_NOR_TEADC(0x5) | \ 194 FTIM0_NOR_TEAHC(0x5)) 195 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 196 FTIM1_NOR_TRAD_NOR(0x1A) |\ 197 FTIM1_NOR_TSEQRAD_NOR(0x13)) 198 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 199 FTIM2_NOR_TCH(0x4) | \ 200 FTIM2_NOR_TWPH(0x0E) | \ 201 FTIM2_NOR_TWP(0x1c)) 202 #define CONFIG_SYS_NOR_FTIM3 0x0 203 204 #define CONFIG_SYS_FLASH_QUIET_TEST 205 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 206 207 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 209 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 210 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 211 212 #define CONFIG_SYS_FLASH_EMPTY_INFO 213 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 214 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 215 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 216 #define QIXIS_BASE 0xffdf0000 217 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 218 #define QIXIS_LBMAP_SWITCH 0x06 219 #define QIXIS_LBMAP_MASK 0x0f 220 #define QIXIS_LBMAP_SHIFT 0 221 #define QIXIS_LBMAP_DFLTBANK 0x00 222 #define QIXIS_LBMAP_ALTBANK 0x04 223 #define QIXIS_RST_CTL_RESET 0x31 224 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 225 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 226 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 227 #define QIXIS_RST_FORCE_MEM 0x01 228 229 #define CONFIG_SYS_CSPR3_EXT (0xf) 230 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 231 | CSPR_PORT_SIZE_8 \ 232 | CSPR_MSEL_GPCM \ 233 | CSPR_V) 234 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 235 #define CONFIG_SYS_CSOR3 0x0 236 /* QIXIS Timing parameters for IFC CS3 */ 237 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 238 FTIM0_GPCM_TEADC(0x0e) | \ 239 FTIM0_GPCM_TEAHC(0x0e)) 240 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 241 FTIM1_GPCM_TRAD(0x3f)) 242 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 243 FTIM2_GPCM_TCH(0x8) | \ 244 FTIM2_GPCM_TWP(0x1f)) 245 #define CONFIG_SYS_CS3_FTIM3 0x0 246 247 #define CONFIG_NAND_FSL_IFC 248 #define CONFIG_SYS_NAND_BASE 0xff800000 249 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 250 251 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 252 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 253 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 254 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 255 | CSPR_V) 256 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 257 258 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 259 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 260 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 261 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 262 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 263 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 264 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 265 266 #define CONFIG_SYS_NAND_ONFI_DETECTION 267 268 /* ONFI NAND Flash mode0 Timing Params */ 269 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 270 FTIM0_NAND_TWP(0x18) | \ 271 FTIM0_NAND_TWCHT(0x07) | \ 272 FTIM0_NAND_TWH(0x0a)) 273 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 274 FTIM1_NAND_TWBE(0x39) | \ 275 FTIM1_NAND_TRR(0x0e) | \ 276 FTIM1_NAND_TRP(0x18)) 277 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 278 FTIM2_NAND_TREH(0x0a) | \ 279 FTIM2_NAND_TWHRE(0x1e)) 280 #define CONFIG_SYS_NAND_FTIM3 0x0 281 282 #define CONFIG_SYS_NAND_DDR_LAW 11 283 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 284 #define CONFIG_SYS_MAX_NAND_DEVICE 1 285 286 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 287 288 #if defined(CONFIG_NAND) 289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #else 314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 331 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 332 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 333 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 334 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 335 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 336 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 337 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 338 #endif 339 340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 341 342 #if defined(CONFIG_RAMBOOT_PBL) 343 #define CONFIG_SYS_RAMBOOT 344 #endif 345 346 #define CONFIG_BOARD_EARLY_INIT_R 347 #define CONFIG_MISC_INIT_R 348 349 #define CONFIG_HWCONFIG 350 351 /* define to use L1 as initial stack */ 352 #define CONFIG_L1_INIT_RAM 353 #define CONFIG_SYS_INIT_RAM_LOCK 354 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 357 /* The assembler doesn't like typecast */ 358 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 359 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 360 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 361 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 362 363 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 364 GENERATED_GBL_DATA_SIZE) 365 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 366 367 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 368 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 369 370 /* Serial Port - controlled on board with jumper J8 371 * open - index 2 372 * shorted - index 1 373 */ 374 #define CONFIG_CONS_INDEX 1 375 #define CONFIG_SYS_NS16550_SERIAL 376 #define CONFIG_SYS_NS16550_REG_SIZE 1 377 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 378 379 #define CONFIG_SYS_BAUDRATE_TABLE \ 380 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 381 382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 383 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 384 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 385 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 386 387 /* Video */ 388 #define CONFIG_FSL_DIU_FB 389 #ifdef CONFIG_FSL_DIU_FB 390 #define CONFIG_FSL_DIU_CH7301 391 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 392 #define CONFIG_VIDEO_LOGO 393 #define CONFIG_VIDEO_BMP_LOGO 394 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 395 /* 396 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 397 * disable empty flash sector detection, which is I/O-intensive. 398 */ 399 #undef CONFIG_SYS_FLASH_EMPTY_INFO 400 #endif 401 402 /* I2C */ 403 #define CONFIG_SYS_I2C 404 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 405 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 406 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 407 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 408 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 409 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 410 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 411 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 412 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 413 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 414 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 415 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 416 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 417 418 #define I2C_MUX_PCA_ADDR 0x77 419 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 420 421 /* I2C bus multiplexer */ 422 #define I2C_MUX_CH_DEFAULT 0x8 423 #define I2C_MUX_CH_DIU 0xC 424 425 /* LDI/DVI Encoder for display */ 426 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 427 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 428 429 /* 430 * RTC configuration 431 */ 432 #define RTC 433 #define CONFIG_RTC_DS3231 1 434 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 435 436 /* 437 * eSPI - Enhanced SPI 438 */ 439 #define CONFIG_SF_DEFAULT_SPEED 10000000 440 #define CONFIG_SF_DEFAULT_MODE 0 441 442 /* 443 * General PCI 444 * Memory space is mapped 1-1, but I/O space must start from 0. 445 */ 446 447 #ifdef CONFIG_PCI 448 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 449 #ifdef CONFIG_PCIE1 450 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 451 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 452 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 453 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 454 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 455 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 456 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 457 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 458 #endif 459 460 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 461 #ifdef CONFIG_PCIE2 462 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 463 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 464 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 465 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 466 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 467 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 469 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 470 #endif 471 472 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 473 #ifdef CONFIG_PCIE3 474 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 475 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 476 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 477 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 478 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 479 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 480 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 481 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 482 #endif 483 484 /* controller 4, Base address 203000 */ 485 #ifdef CONFIG_PCIE4 486 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 487 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 488 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 489 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 490 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 491 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 492 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 493 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 494 #endif 495 496 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 497 #endif /* CONFIG_PCI */ 498 499 /* SATA */ 500 #define CONFIG_FSL_SATA_V2 501 #ifdef CONFIG_FSL_SATA_V2 502 #define CONFIG_SYS_SATA_MAX_DEVICE 2 503 #define CONFIG_SATA1 504 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 505 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 506 #define CONFIG_SATA2 507 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 508 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 509 510 #define CONFIG_LBA48 511 #endif 512 513 /* 514 * USB 515 */ 516 #define CONFIG_HAS_FSL_DR_USB 517 518 #ifdef CONFIG_HAS_FSL_DR_USB 519 #ifdef CONFIG_USB_EHCI_HCD 520 #define CONFIG_USB_EHCI_FSL 521 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 522 #endif 523 #endif 524 525 #ifdef CONFIG_MMC 526 #define CONFIG_FSL_ESDHC 527 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 528 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 529 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 530 #endif 531 532 /* Qman/Bman */ 533 #ifndef CONFIG_NOBQFMAN 534 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 535 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 536 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 537 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 538 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 539 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 540 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 541 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 542 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 543 CONFIG_SYS_BMAN_CENA_SIZE) 544 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 545 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 546 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 547 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 548 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 549 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 550 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 551 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 552 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 553 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 554 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 555 CONFIG_SYS_QMAN_CENA_SIZE) 556 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 557 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 558 559 #define CONFIG_SYS_DPAA_FMAN 560 #define CONFIG_SYS_DPAA_PME 561 562 #define CONFIG_QE 563 #define CONFIG_U_QE 564 /* Default address of microcode for the Linux Fman driver */ 565 #if defined(CONFIG_SPIFLASH) 566 /* 567 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 568 * env, so we got 0x110000. 569 */ 570 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 571 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 572 #elif defined(CONFIG_SDCARD) 573 /* 574 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 575 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 576 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 577 */ 578 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 579 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 580 #elif defined(CONFIG_NAND) 581 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 582 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 583 #else 584 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 585 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 586 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 587 #endif 588 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 589 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 590 #endif /* CONFIG_NOBQFMAN */ 591 592 #ifdef CONFIG_SYS_DPAA_FMAN 593 #define CONFIG_FMAN_ENET 594 #define CONFIG_PHYLIB_10G 595 #define CONFIG_PHY_VITESSE 596 #define CONFIG_PHY_REALTEK 597 #define CONFIG_PHY_TERANETICS 598 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 599 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 600 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 601 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 602 #endif 603 604 #ifdef CONFIG_FMAN_ENET 605 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 606 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 607 608 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 609 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 610 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 611 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 612 613 #define CONFIG_MII /* MII PHY management */ 614 #define CONFIG_ETHPRIME "FM1@DTSEC1" 615 #endif 616 617 /* Enable VSC9953 L2 Switch driver */ 618 #define CONFIG_VSC9953 619 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 620 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 621 622 /* 623 * Dynamic MTD Partition support with mtdparts 624 */ 625 #ifdef CONFIG_MTD_NOR_FLASH 626 #define CONFIG_MTD_DEVICE 627 #define CONFIG_MTD_PARTITIONS 628 #define CONFIG_FLASH_CFI_MTD 629 #endif 630 631 /* 632 * Environment 633 */ 634 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 635 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 636 637 /* 638 * Miscellaneous configurable options 639 */ 640 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 641 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 642 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 643 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 644 645 /* 646 * For booting Linux, the board info and command line data 647 * have to be in the first 64 MB of memory, since this is 648 * the maximum mapped by the Linux kernel during initialization. 649 */ 650 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 651 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 652 653 #ifdef CONFIG_CMD_KGDB 654 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 655 #endif 656 657 /* 658 * Environment Configuration 659 */ 660 #define CONFIG_ROOTPATH "/opt/nfsroot" 661 #define CONFIG_BOOTFILE "uImage" 662 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 663 664 /* default location for tftp and bootm */ 665 #define CONFIG_LOADADDR 1000000 666 667 #define __USB_PHY_TYPE utmi 668 669 #define CONFIG_EXTRA_ENV_SETTINGS \ 670 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 671 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 672 "netdev=eth0\0" \ 673 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 674 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 675 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 676 "tftpflash=tftpboot $loadaddr $uboot && " \ 677 "protect off $ubootaddr +$filesize && " \ 678 "erase $ubootaddr +$filesize && " \ 679 "cp.b $loadaddr $ubootaddr $filesize && " \ 680 "protect on $ubootaddr +$filesize && " \ 681 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 682 "consoledev=ttyS0\0" \ 683 "ramdiskaddr=2000000\0" \ 684 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 685 "fdtaddr=1e00000\0" \ 686 "fdtfile=t1040qds/t1040qds.dtb\0" \ 687 "bdev=sda3\0" 688 689 #define CONFIG_LINUX \ 690 "setenv bootargs root=/dev/ram rw " \ 691 "console=$consoledev,$baudrate $othbootargs;" \ 692 "setenv ramdiskaddr 0x02000000;" \ 693 "setenv fdtaddr 0x00c00000;" \ 694 "setenv loadaddr 0x1000000;" \ 695 "bootm $loadaddr $ramdiskaddr $fdtaddr" 696 697 #define CONFIG_HDBOOT \ 698 "setenv bootargs root=/dev/$bdev rw " \ 699 "console=$consoledev,$baudrate $othbootargs;" \ 700 "tftp $loadaddr $bootfile;" \ 701 "tftp $fdtaddr $fdtfile;" \ 702 "bootm $loadaddr - $fdtaddr" 703 704 #define CONFIG_NFSBOOTCOMMAND \ 705 "setenv bootargs root=/dev/nfs rw " \ 706 "nfsroot=$serverip:$rootpath " \ 707 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 708 "console=$consoledev,$baudrate $othbootargs;" \ 709 "tftp $loadaddr $bootfile;" \ 710 "tftp $fdtaddr $fdtfile;" \ 711 "bootm $loadaddr - $fdtaddr" 712 713 #define CONFIG_RAMBOOTCOMMAND \ 714 "setenv bootargs root=/dev/ram rw " \ 715 "console=$consoledev,$baudrate $othbootargs;" \ 716 "tftp $ramdiskaddr $ramdiskfile;" \ 717 "tftp $loadaddr $bootfile;" \ 718 "tftp $fdtaddr $fdtfile;" \ 719 "bootm $loadaddr $ramdiskaddr $fdtaddr" 720 721 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 722 723 #include <asm/fsl_secure_boot.h> 724 725 #endif /* __CONFIG_H */ 726