1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg 36 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_PCI /* Enable PCI/PCIE */ 59 #define CONFIG_PCI_INDIRECT_BRIDGE 60 #define CONFIG_PCIE1 /* PCIE controler 1 */ 61 #define CONFIG_PCIE2 /* PCIE controler 2 */ 62 #define CONFIG_PCIE3 /* PCIE controler 3 */ 63 #define CONFIG_PCIE4 /* PCIE controler 4 */ 64 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 69 70 #define CONFIG_ENV_OVERWRITE 71 72 #ifdef CONFIG_SYS_NO_FLASH 73 #define CONFIG_ENV_IS_NOWHERE 74 #else 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 78 #endif 79 80 #ifndef CONFIG_SYS_NO_FLASH 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1105) 97 #elif defined(CONFIG_NAND) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_NAND 100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 101 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 102 #else 103 #define CONFIG_ENV_IS_IN_FLASH 104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 105 #define CONFIG_ENV_SIZE 0x2000 106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 107 #endif 108 #else /* CONFIG_SYS_NO_FLASH */ 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 111 #endif 112 113 #ifndef __ASSEMBLY__ 114 unsigned long get_board_sys_clk(void); 115 unsigned long get_board_ddr_clk(void); 116 #endif 117 118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 119 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 120 121 /* 122 * These can be toggled for performance analysis, otherwise use default. 123 */ 124 #define CONFIG_SYS_CACHE_STASHING 125 #define CONFIG_BACKSIDE_L2_CACHE 126 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 127 #define CONFIG_BTB /* toggle branch predition */ 128 #define CONFIG_DDR_ECC 129 #ifdef CONFIG_DDR_ECC 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 132 #endif 133 134 #define CONFIG_ENABLE_36BIT_PHYS 135 136 #define CONFIG_ADDR_MAP 137 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 138 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x00400000 141 #define CONFIG_SYS_ALT_MEMTEST 142 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 143 144 /* 145 * Config the L3 Cache as L3 SRAM 146 */ 147 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 148 149 #define CONFIG_SYS_DCSRBAR 0xf0000000 150 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 151 152 /* EEPROM */ 153 #define CONFIG_ID_EEPROM 154 #define CONFIG_SYS_I2C_EEPROM_NXID 155 #define CONFIG_SYS_EEPROM_BUS_NUM 0 156 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 160 161 /* 162 * DDR Setup 163 */ 164 #define CONFIG_VERY_BIG_RAM 165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 167 168 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 169 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 170 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 171 172 #define CONFIG_DDR_SPD 173 #define CONFIG_SYS_FSL_DDR3 174 #define CONFIG_FSL_DDR_INTERACTIVE 175 176 #define CONFIG_SYS_SPD_BUS_NUM 0 177 #define SPD_EEPROM_ADDRESS 0x51 178 179 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 180 181 /* 182 * IFC Definitions 183 */ 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 186 187 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 188 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 189 + 0x8000000) | \ 190 CSPR_PORT_SIZE_16 | \ 191 CSPR_MSEL_NOR | \ 192 CSPR_V) 193 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 194 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 195 CSPR_PORT_SIZE_16 | \ 196 CSPR_MSEL_NOR | \ 197 CSPR_V) 198 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 199 /* NOR Flash Timing Params */ 200 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 201 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 202 FTIM0_NOR_TEADC(0x5) | \ 203 FTIM0_NOR_TEAHC(0x5)) 204 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 205 FTIM1_NOR_TRAD_NOR(0x1A) |\ 206 FTIM1_NOR_TSEQRAD_NOR(0x13)) 207 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 208 FTIM2_NOR_TCH(0x4) | \ 209 FTIM2_NOR_TWPH(0x0E) | \ 210 FTIM2_NOR_TWP(0x1c)) 211 #define CONFIG_SYS_NOR_FTIM3 0x0 212 213 #define CONFIG_SYS_FLASH_QUIET_TEST 214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 215 216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 220 221 #define CONFIG_SYS_FLASH_EMPTY_INFO 222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 223 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 224 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 225 #define QIXIS_BASE 0xffdf0000 226 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 227 #define QIXIS_LBMAP_SWITCH 0x06 228 #define QIXIS_LBMAP_MASK 0x0f 229 #define QIXIS_LBMAP_SHIFT 0 230 #define QIXIS_LBMAP_DFLTBANK 0x00 231 #define QIXIS_LBMAP_ALTBANK 0x04 232 #define QIXIS_RST_CTL_RESET 0x31 233 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 234 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 235 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 236 237 #define CONFIG_SYS_CSPR3_EXT (0xf) 238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 239 | CSPR_PORT_SIZE_8 \ 240 | CSPR_MSEL_GPCM \ 241 | CSPR_V) 242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 243 #define CONFIG_SYS_CSOR3 0x0 244 /* QIXIS Timing parameters for IFC CS3 */ 245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 246 FTIM0_GPCM_TEADC(0x0e) | \ 247 FTIM0_GPCM_TEAHC(0x0e)) 248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 249 FTIM1_GPCM_TRAD(0x3f)) 250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 251 FTIM2_GPCM_TCH(0x0) | \ 252 FTIM2_GPCM_TWP(0x1f)) 253 #define CONFIG_SYS_CS3_FTIM3 0x0 254 255 #define CONFIG_NAND_FSL_IFC 256 #define CONFIG_SYS_NAND_BASE 0xff800000 257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 258 259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 262 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 263 | CSPR_V) 264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 265 266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 273 274 #define CONFIG_SYS_NAND_ONFI_DETECTION 275 276 /* ONFI NAND Flash mode0 Timing Params */ 277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 278 FTIM0_NAND_TWP(0x18) | \ 279 FTIM0_NAND_TWCHT(0x07) | \ 280 FTIM0_NAND_TWH(0x0a)) 281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 282 FTIM1_NAND_TWBE(0x39) | \ 283 FTIM1_NAND_TRR(0x0e) | \ 284 FTIM1_NAND_TRP(0x18)) 285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 286 FTIM2_NAND_TREH(0x0a) | \ 287 FTIM2_NAND_TWHRE(0x1e)) 288 #define CONFIG_SYS_NAND_FTIM3 0x0 289 290 #define CONFIG_SYS_NAND_DDR_LAW 11 291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 293 #define CONFIG_MTD_NAND_VERIFY_WRITE 294 #define CONFIG_CMD_NAND 295 296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 297 298 #if defined(CONFIG_NAND) 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #else 324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 348 #endif 349 350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 351 352 #if defined(CONFIG_RAMBOOT_PBL) 353 #define CONFIG_SYS_RAMBOOT 354 #endif 355 356 #define CONFIG_BOARD_EARLY_INIT_R 357 #define CONFIG_MISC_INIT_R 358 359 #define CONFIG_HWCONFIG 360 361 /* define to use L1 as initial stack */ 362 #define CONFIG_L1_INIT_RAM 363 #define CONFIG_SYS_INIT_RAM_LOCK 364 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 367 /* The assembler doesn't like typecast */ 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 369 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 370 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 372 373 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 374 GENERATED_GBL_DATA_SIZE) 375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 376 377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 378 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 379 380 /* Serial Port - controlled on board with jumper J8 381 * open - index 2 382 * shorted - index 1 383 */ 384 #define CONFIG_CONS_INDEX 1 385 #define CONFIG_SYS_NS16550 386 #define CONFIG_SYS_NS16550_SERIAL 387 #define CONFIG_SYS_NS16550_REG_SIZE 1 388 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 389 390 #define CONFIG_SYS_BAUDRATE_TABLE \ 391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 392 393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 399 400 /* Use the HUSH parser */ 401 #define CONFIG_SYS_HUSH_PARSER 402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 403 404 /* pass open firmware flat tree */ 405 #define CONFIG_OF_LIBFDT 406 #define CONFIG_OF_BOARD_SETUP 407 #define CONFIG_OF_STDOUT_VIA_ALIAS 408 409 /* new uImage format support */ 410 #define CONFIG_FIT 411 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 412 413 /* I2C */ 414 #define CONFIG_SYS_I2C 415 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 416 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 419 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 422 423 #define I2C_MUX_PCA_ADDR 0x77 424 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 425 426 427 /* I2C bus multiplexer */ 428 #define I2C_MUX_CH_DEFAULT 0x8 429 430 /* 431 * RTC configuration 432 */ 433 #define RTC 434 #define CONFIG_RTC_DS3231 1 435 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 436 437 /* 438 * eSPI - Enhanced SPI 439 */ 440 #define CONFIG_FSL_ESPI 441 #define CONFIG_SPI_FLASH 442 #define CONFIG_SPI_FLASH_STMICRO 443 #define CONFIG_SPI_FLASH_SST 444 #define CONFIG_SPI_FLASH_EON 445 #define CONFIG_CMD_SF 446 #define CONFIG_SF_DEFAULT_SPEED 10000000 447 #define CONFIG_SF_DEFAULT_MODE 0 448 449 /* 450 * General PCI 451 * Memory space is mapped 1-1, but I/O space must start from 0. 452 */ 453 454 #ifdef CONFIG_PCI 455 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 456 #ifdef CONFIG_PCIE1 457 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 458 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 460 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 461 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 462 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 464 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 465 #endif 466 467 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 468 #ifdef CONFIG_PCIE2 469 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 470 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 472 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 473 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 474 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 475 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 476 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 477 #endif 478 479 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 480 #ifdef CONFIG_PCIE3 481 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 484 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 485 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 486 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 488 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 489 #endif 490 491 /* controller 4, Base address 203000 */ 492 #ifdef CONFIG_PCIE4 493 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 494 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 495 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 496 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 497 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 498 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 499 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 500 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 501 #endif 502 503 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 504 #define CONFIG_E1000 505 506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 507 #define CONFIG_DOS_PARTITION 508 #endif /* CONFIG_PCI */ 509 510 /* SATA */ 511 #define CONFIG_FSL_SATA_V2 512 #ifdef CONFIG_FSL_SATA_V2 513 #define CONFIG_LIBATA 514 #define CONFIG_FSL_SATA 515 516 #define CONFIG_SYS_SATA_MAX_DEVICE 2 517 #define CONFIG_SATA1 518 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 519 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 520 #define CONFIG_SATA2 521 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 522 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 523 524 #define CONFIG_LBA48 525 #define CONFIG_CMD_SATA 526 #define CONFIG_DOS_PARTITION 527 #define CONFIG_CMD_EXT2 528 #endif 529 530 /* 531 * USB 532 */ 533 #define CONFIG_HAS_FSL_DR_USB 534 535 #ifdef CONFIG_HAS_FSL_DR_USB 536 #define CONFIG_USB_EHCI 537 538 #ifdef CONFIG_USB_EHCI 539 #define CONFIG_CMD_USB 540 #define CONFIG_USB_STORAGE 541 #define CONFIG_USB_EHCI_FSL 542 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 543 #define CONFIG_CMD_EXT2 544 #endif 545 #endif 546 547 #define CONFIG_MMC 548 549 #ifdef CONFIG_MMC 550 #define CONFIG_FSL_ESDHC 551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 552 #define CONFIG_CMD_MMC 553 #define CONFIG_GENERIC_MMC 554 #define CONFIG_CMD_EXT2 555 #define CONFIG_CMD_FAT 556 #define CONFIG_DOS_PARTITION 557 #endif 558 559 /* Qman/Bman */ 560 #ifndef CONFIG_NOBQFMAN 561 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 562 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 563 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 564 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 565 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 566 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 567 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 568 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 569 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 570 571 #define CONFIG_SYS_DPAA_FMAN 572 #define CONFIG_SYS_DPAA_PME 573 574 /* Default address of microcode for the Linux Fman driver */ 575 #if defined(CONFIG_SPIFLASH) 576 /* 577 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 578 * env, so we got 0x110000. 579 */ 580 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 581 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 582 #elif defined(CONFIG_SDCARD) 583 /* 584 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 585 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 586 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 587 */ 588 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 589 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 590 #elif defined(CONFIG_NAND) 591 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 592 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 593 #else 594 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 595 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 596 #endif 597 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 598 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 599 #endif /* CONFIG_NOBQFMAN */ 600 601 #ifdef CONFIG_SYS_DPAA_FMAN 602 #define CONFIG_FMAN_ENET 603 #define CONFIG_PHYLIB_10G 604 #define CONFIG_PHY_VITESSE 605 #define CONFIG_PHY_REALTEK 606 #define CONFIG_PHY_TERANETICS 607 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 608 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 609 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 610 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 611 #endif 612 613 #ifdef CONFIG_FMAN_ENET 614 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 615 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 616 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 617 618 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 619 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 620 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 621 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 622 623 #define CONFIG_MII /* MII PHY management */ 624 #define CONFIG_ETHPRIME "FM1@DTSEC1" 625 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 626 #endif 627 628 /* 629 * Environment 630 */ 631 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 632 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 633 634 /* 635 * Command line configuration. 636 */ 637 #include <config_cmd_default.h> 638 639 #define CONFIG_CMD_DATE 640 #define CONFIG_CMD_DHCP 641 #define CONFIG_CMD_EEPROM 642 #define CONFIG_CMD_ELF 643 #define CONFIG_CMD_ERRATA 644 #define CONFIG_CMD_GREPENV 645 #define CONFIG_CMD_IRQ 646 #define CONFIG_CMD_I2C 647 #define CONFIG_CMD_MII 648 #define CONFIG_CMD_PING 649 #define CONFIG_CMD_REGINFO 650 #define CONFIG_CMD_SETEXPR 651 652 #ifdef CONFIG_PCI 653 #define CONFIG_CMD_PCI 654 #define CONFIG_CMD_NET 655 #endif 656 657 /* 658 * Miscellaneous configurable options 659 */ 660 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 661 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 662 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 663 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 664 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 665 #ifdef CONFIG_CMD_KGDB 666 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 667 #else 668 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 669 #endif 670 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 671 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 672 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 673 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 674 675 /* 676 * For booting Linux, the board info and command line data 677 * have to be in the first 64 MB of memory, since this is 678 * the maximum mapped by the Linux kernel during initialization. 679 */ 680 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 681 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 682 683 #ifdef CONFIG_CMD_KGDB 684 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 685 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 686 #endif 687 688 /* 689 * Environment Configuration 690 */ 691 #define CONFIG_ROOTPATH "/opt/nfsroot" 692 #define CONFIG_BOOTFILE "uImage" 693 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 694 695 /* default location for tftp and bootm */ 696 #define CONFIG_LOADADDR 1000000 697 698 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 699 700 #define CONFIG_BAUDRATE 115200 701 702 #define __USB_PHY_TYPE utmi 703 704 #define CONFIG_EXTRA_ENV_SETTINGS \ 705 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 706 "bank_intlv=cs0_cs1;" \ 707 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 708 "netdev=eth0\0" \ 709 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 710 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 711 "tftpflash=tftpboot $loadaddr $uboot && " \ 712 "protect off $ubootaddr +$filesize && " \ 713 "erase $ubootaddr +$filesize && " \ 714 "cp.b $loadaddr $ubootaddr $filesize && " \ 715 "protect on $ubootaddr +$filesize && " \ 716 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 717 "consoledev=ttyS0\0" \ 718 "ramdiskaddr=2000000\0" \ 719 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 720 "fdtaddr=c00000\0" \ 721 "fdtfile=t1040qds/t1040qds.dtb\0" \ 722 "bdev=sda3\0" \ 723 "c=ffe\0" 724 725 #define CONFIG_LINUX \ 726 "setenv bootargs root=/dev/ram rw " \ 727 "console=$consoledev,$baudrate $othbootargs;" \ 728 "setenv ramdiskaddr 0x02000000;" \ 729 "setenv fdtaddr 0x00c00000;" \ 730 "setenv loadaddr 0x1000000;" \ 731 "bootm $loadaddr $ramdiskaddr $fdtaddr" 732 733 #define CONFIG_HDBOOT \ 734 "setenv bootargs root=/dev/$bdev rw " \ 735 "console=$consoledev,$baudrate $othbootargs;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr - $fdtaddr" 739 740 #define CONFIG_NFSBOOTCOMMAND \ 741 "setenv bootargs root=/dev/nfs rw " \ 742 "nfsroot=$serverip:$rootpath " \ 743 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 744 "console=$consoledev,$baudrate $othbootargs;" \ 745 "tftp $loadaddr $bootfile;" \ 746 "tftp $fdtaddr $fdtfile;" \ 747 "bootm $loadaddr - $fdtaddr" 748 749 #define CONFIG_RAMBOOTCOMMAND \ 750 "setenv bootargs root=/dev/ram rw " \ 751 "console=$consoledev,$baudrate $othbootargs;" \ 752 "tftp $ramdiskaddr $ramdiskfile;" \ 753 "tftp $loadaddr $bootfile;" \ 754 "tftp $fdtaddr $fdtfile;" \ 755 "bootm $loadaddr $ramdiskaddr $fdtaddr" 756 757 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 758 759 #ifdef CONFIG_SECURE_BOOT 760 #include <asm/fsl_secure_boot.h> 761 #endif 762 763 #endif /* __CONFIG_H */ 764