1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 /* support deep sleep */ 42 #define CONFIG_DEEP_SLEEP 43 #if defined(CONFIG_DEEP_SLEEP) 44 #define CONFIG_BOARD_EARLY_INIT_F 45 #endif 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff40000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 59 #define CONFIG_PCI_INDIRECT_BRIDGE 60 #define CONFIG_PCIE1 /* PCIE controller 1 */ 61 #define CONFIG_PCIE2 /* PCIE controller 2 */ 62 #define CONFIG_PCIE3 /* PCIE controller 3 */ 63 #define CONFIG_PCIE4 /* PCIE controller 4 */ 64 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #define CONFIG_ENV_IS_NOWHERE 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #ifndef CONFIG_SYS_NO_FLASH 79 #if defined(CONFIG_SPIFLASH) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #elif defined(CONFIG_SDCARD) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #else 101 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #endif 106 #else /* CONFIG_SYS_NO_FLASH */ 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #endif 110 111 #ifndef __ASSEMBLY__ 112 unsigned long get_board_sys_clk(void); 113 unsigned long get_board_ddr_clk(void); 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #define CONFIG_ENABLE_36BIT_PHYS 133 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 142 /* 143 * Config the L3 Cache as L3 SRAM 144 */ 145 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 147 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 167 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 168 169 #define CONFIG_DDR_SPD 170 #define CONFIG_FSL_DDR_INTERACTIVE 171 172 #define CONFIG_SYS_SPD_BUS_NUM 0 173 #define SPD_EEPROM_ADDRESS 0x51 174 175 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 176 177 /* 178 * IFC Definitions 179 */ 180 #define CONFIG_SYS_FLASH_BASE 0xe0000000 181 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 182 183 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 184 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 185 + 0x8000000) | \ 186 CSPR_PORT_SIZE_16 | \ 187 CSPR_MSEL_NOR | \ 188 CSPR_V) 189 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 190 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 191 CSPR_PORT_SIZE_16 | \ 192 CSPR_MSEL_NOR | \ 193 CSPR_V) 194 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 195 196 /* 197 * TDM Definition 198 */ 199 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 200 201 /* NOR Flash Timing Params */ 202 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 203 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 204 FTIM0_NOR_TEADC(0x5) | \ 205 FTIM0_NOR_TEAHC(0x5)) 206 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 207 FTIM1_NOR_TRAD_NOR(0x1A) |\ 208 FTIM1_NOR_TSEQRAD_NOR(0x13)) 209 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 210 FTIM2_NOR_TCH(0x4) | \ 211 FTIM2_NOR_TWPH(0x0E) | \ 212 FTIM2_NOR_TWP(0x1c)) 213 #define CONFIG_SYS_NOR_FTIM3 0x0 214 215 #define CONFIG_SYS_FLASH_QUIET_TEST 216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 222 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 225 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 226 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 227 #define QIXIS_BASE 0xffdf0000 228 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 229 #define QIXIS_LBMAP_SWITCH 0x06 230 #define QIXIS_LBMAP_MASK 0x0f 231 #define QIXIS_LBMAP_SHIFT 0 232 #define QIXIS_LBMAP_DFLTBANK 0x00 233 #define QIXIS_LBMAP_ALTBANK 0x04 234 #define QIXIS_RST_CTL_RESET 0x31 235 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 236 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 237 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 238 #define QIXIS_RST_FORCE_MEM 0x01 239 240 #define CONFIG_SYS_CSPR3_EXT (0xf) 241 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 242 | CSPR_PORT_SIZE_8 \ 243 | CSPR_MSEL_GPCM \ 244 | CSPR_V) 245 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 246 #define CONFIG_SYS_CSOR3 0x0 247 /* QIXIS Timing parameters for IFC CS3 */ 248 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 249 FTIM0_GPCM_TEADC(0x0e) | \ 250 FTIM0_GPCM_TEAHC(0x0e)) 251 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 252 FTIM1_GPCM_TRAD(0x3f)) 253 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 254 FTIM2_GPCM_TCH(0x8) | \ 255 FTIM2_GPCM_TWP(0x1f)) 256 #define CONFIG_SYS_CS3_FTIM3 0x0 257 258 #define CONFIG_NAND_FSL_IFC 259 #define CONFIG_SYS_NAND_BASE 0xff800000 260 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 261 262 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 263 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 264 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 265 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 266 | CSPR_V) 267 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 268 269 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 270 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 271 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 272 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 273 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 274 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 275 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 276 277 #define CONFIG_SYS_NAND_ONFI_DETECTION 278 279 /* ONFI NAND Flash mode0 Timing Params */ 280 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 281 FTIM0_NAND_TWP(0x18) | \ 282 FTIM0_NAND_TWCHT(0x07) | \ 283 FTIM0_NAND_TWH(0x0a)) 284 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 285 FTIM1_NAND_TWBE(0x39) | \ 286 FTIM1_NAND_TRR(0x0e) | \ 287 FTIM1_NAND_TRP(0x18)) 288 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 289 FTIM2_NAND_TREH(0x0a) | \ 290 FTIM2_NAND_TWHRE(0x1e)) 291 #define CONFIG_SYS_NAND_FTIM3 0x0 292 293 #define CONFIG_SYS_NAND_DDR_LAW 11 294 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 295 #define CONFIG_SYS_MAX_NAND_DEVICE 1 296 #define CONFIG_CMD_NAND 297 298 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 299 300 #if defined(CONFIG_NAND) 301 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 309 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 310 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 311 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 318 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 319 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 320 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 321 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 322 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 323 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 324 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 325 #else 326 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 327 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 328 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 335 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 336 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 343 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 344 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 345 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 346 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 347 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 348 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 349 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 350 #endif 351 352 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 353 354 #if defined(CONFIG_RAMBOOT_PBL) 355 #define CONFIG_SYS_RAMBOOT 356 #endif 357 358 #define CONFIG_BOARD_EARLY_INIT_R 359 #define CONFIG_MISC_INIT_R 360 361 #define CONFIG_HWCONFIG 362 363 /* define to use L1 as initial stack */ 364 #define CONFIG_L1_INIT_RAM 365 #define CONFIG_SYS_INIT_RAM_LOCK 366 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 369 /* The assembler doesn't like typecast */ 370 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 371 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 372 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 373 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 374 375 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 376 GENERATED_GBL_DATA_SIZE) 377 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 378 379 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 380 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 381 382 /* Serial Port - controlled on board with jumper J8 383 * open - index 2 384 * shorted - index 1 385 */ 386 #define CONFIG_CONS_INDEX 1 387 #define CONFIG_SYS_NS16550_SERIAL 388 #define CONFIG_SYS_NS16550_REG_SIZE 1 389 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 390 391 #define CONFIG_SYS_BAUDRATE_TABLE \ 392 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 393 394 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 395 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 396 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 397 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 398 399 /* Video */ 400 #define CONFIG_FSL_DIU_FB 401 #ifdef CONFIG_FSL_DIU_FB 402 #define CONFIG_FSL_DIU_CH7301 403 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 404 #define CONFIG_CMD_BMP 405 #define CONFIG_VIDEO_LOGO 406 #define CONFIG_VIDEO_BMP_LOGO 407 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 408 /* 409 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 410 * disable empty flash sector detection, which is I/O-intensive. 411 */ 412 #undef CONFIG_SYS_FLASH_EMPTY_INFO 413 #endif 414 415 /* I2C */ 416 #define CONFIG_SYS_I2C 417 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 418 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 419 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 420 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 421 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 422 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 425 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 427 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 428 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 429 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 430 431 #define I2C_MUX_PCA_ADDR 0x77 432 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 433 434 /* I2C bus multiplexer */ 435 #define I2C_MUX_CH_DEFAULT 0x8 436 #define I2C_MUX_CH_DIU 0xC 437 438 /* LDI/DVI Encoder for display */ 439 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 440 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 441 442 /* 443 * RTC configuration 444 */ 445 #define RTC 446 #define CONFIG_RTC_DS3231 1 447 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 448 449 /* 450 * eSPI - Enhanced SPI 451 */ 452 #define CONFIG_SF_DEFAULT_SPEED 10000000 453 #define CONFIG_SF_DEFAULT_MODE 0 454 455 /* 456 * General PCI 457 * Memory space is mapped 1-1, but I/O space must start from 0. 458 */ 459 460 #ifdef CONFIG_PCI 461 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 462 #ifdef CONFIG_PCIE1 463 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 464 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 465 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 466 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 467 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 468 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 469 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 470 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 471 #endif 472 473 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 474 #ifdef CONFIG_PCIE2 475 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 476 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 477 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 478 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 479 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 480 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 481 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 482 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 483 #endif 484 485 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 486 #ifdef CONFIG_PCIE3 487 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 488 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 489 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 490 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 491 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 492 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 493 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 494 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 495 #endif 496 497 /* controller 4, Base address 203000 */ 498 #ifdef CONFIG_PCIE4 499 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 500 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 502 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 503 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 504 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 506 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 507 #endif 508 509 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 510 #define CONFIG_DOS_PARTITION 511 #endif /* CONFIG_PCI */ 512 513 /* SATA */ 514 #define CONFIG_FSL_SATA_V2 515 #ifdef CONFIG_FSL_SATA_V2 516 #define CONFIG_LIBATA 517 #define CONFIG_FSL_SATA 518 519 #define CONFIG_SYS_SATA_MAX_DEVICE 2 520 #define CONFIG_SATA1 521 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 522 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 523 #define CONFIG_SATA2 524 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 525 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 526 527 #define CONFIG_LBA48 528 #define CONFIG_CMD_SATA 529 #define CONFIG_DOS_PARTITION 530 #endif 531 532 /* 533 * USB 534 */ 535 #define CONFIG_HAS_FSL_DR_USB 536 537 #ifdef CONFIG_HAS_FSL_DR_USB 538 #define CONFIG_USB_EHCI 539 540 #ifdef CONFIG_USB_EHCI 541 #define CONFIG_USB_EHCI_FSL 542 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 543 #endif 544 #endif 545 546 #ifdef CONFIG_MMC 547 #define CONFIG_FSL_ESDHC 548 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 549 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 550 #define CONFIG_GENERIC_MMC 551 #define CONFIG_DOS_PARTITION 552 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 553 #endif 554 555 /* Qman/Bman */ 556 #ifndef CONFIG_NOBQFMAN 557 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 558 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 559 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 560 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 561 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 562 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 563 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 564 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 565 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 566 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 567 CONFIG_SYS_BMAN_CENA_SIZE) 568 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 569 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 570 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 571 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 572 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 573 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 574 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 575 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 576 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 577 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 578 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 579 CONFIG_SYS_QMAN_CENA_SIZE) 580 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 582 583 #define CONFIG_SYS_DPAA_FMAN 584 #define CONFIG_SYS_DPAA_PME 585 586 #define CONFIG_QE 587 #define CONFIG_U_QE 588 /* Default address of microcode for the Linux Fman driver */ 589 #if defined(CONFIG_SPIFLASH) 590 /* 591 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 592 * env, so we got 0x110000. 593 */ 594 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 595 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 596 #elif defined(CONFIG_SDCARD) 597 /* 598 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 599 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 600 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 601 */ 602 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 603 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 604 #elif defined(CONFIG_NAND) 605 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 606 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 607 #else 608 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 609 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 610 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 611 #endif 612 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 613 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 614 #endif /* CONFIG_NOBQFMAN */ 615 616 #ifdef CONFIG_SYS_DPAA_FMAN 617 #define CONFIG_FMAN_ENET 618 #define CONFIG_PHYLIB_10G 619 #define CONFIG_PHY_VITESSE 620 #define CONFIG_PHY_REALTEK 621 #define CONFIG_PHY_TERANETICS 622 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 623 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 624 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 625 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 626 #endif 627 628 #ifdef CONFIG_FMAN_ENET 629 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 630 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 631 632 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 633 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 634 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 635 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 636 637 #define CONFIG_MII /* MII PHY management */ 638 #define CONFIG_ETHPRIME "FM1@DTSEC1" 639 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 640 #endif 641 642 /* Enable VSC9953 L2 Switch driver */ 643 #define CONFIG_VSC9953 644 #define CONFIG_CMD_ETHSW 645 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 646 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 647 648 /* 649 * Dynamic MTD Partition support with mtdparts 650 */ 651 #ifndef CONFIG_SYS_NO_FLASH 652 #define CONFIG_MTD_DEVICE 653 #define CONFIG_MTD_PARTITIONS 654 #define CONFIG_CMD_MTDPARTS 655 #define CONFIG_FLASH_CFI_MTD 656 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 657 "spi0=spife110000.0" 658 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 659 "128k(dtb),96m(fs),-(user);"\ 660 "fff800000.flash:2m(uboot),9m(kernel),"\ 661 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 662 "2m(uboot),9m(kernel),128k(dtb),-(user)" 663 #endif 664 665 /* 666 * Environment 667 */ 668 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 669 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 670 671 /* 672 * Command line configuration. 673 */ 674 #define CONFIG_CMD_DATE 675 #define CONFIG_CMD_EEPROM 676 #define CONFIG_CMD_ERRATA 677 #define CONFIG_CMD_IRQ 678 #define CONFIG_CMD_REGINFO 679 680 #ifdef CONFIG_PCI 681 #define CONFIG_CMD_PCI 682 #endif 683 684 /* Hash command with SHA acceleration supported in hardware */ 685 #ifdef CONFIG_FSL_CAAM 686 #define CONFIG_CMD_HASH 687 #define CONFIG_SHA_HW_ACCEL 688 #endif 689 690 /* 691 * Miscellaneous configurable options 692 */ 693 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 694 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 695 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 696 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 697 #ifdef CONFIG_CMD_KGDB 698 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 699 #else 700 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 701 #endif 702 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 703 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 704 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 705 706 /* 707 * For booting Linux, the board info and command line data 708 * have to be in the first 64 MB of memory, since this is 709 * the maximum mapped by the Linux kernel during initialization. 710 */ 711 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 712 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 713 714 #ifdef CONFIG_CMD_KGDB 715 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 716 #endif 717 718 /* 719 * Environment Configuration 720 */ 721 #define CONFIG_ROOTPATH "/opt/nfsroot" 722 #define CONFIG_BOOTFILE "uImage" 723 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 724 725 /* default location for tftp and bootm */ 726 #define CONFIG_LOADADDR 1000000 727 728 729 #define CONFIG_BAUDRATE 115200 730 731 #define __USB_PHY_TYPE utmi 732 733 #define CONFIG_EXTRA_ENV_SETTINGS \ 734 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 735 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 736 "netdev=eth0\0" \ 737 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 738 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 739 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 740 "tftpflash=tftpboot $loadaddr $uboot && " \ 741 "protect off $ubootaddr +$filesize && " \ 742 "erase $ubootaddr +$filesize && " \ 743 "cp.b $loadaddr $ubootaddr $filesize && " \ 744 "protect on $ubootaddr +$filesize && " \ 745 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 746 "consoledev=ttyS0\0" \ 747 "ramdiskaddr=2000000\0" \ 748 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 749 "fdtaddr=1e00000\0" \ 750 "fdtfile=t1040qds/t1040qds.dtb\0" \ 751 "bdev=sda3\0" 752 753 #define CONFIG_LINUX \ 754 "setenv bootargs root=/dev/ram rw " \ 755 "console=$consoledev,$baudrate $othbootargs;" \ 756 "setenv ramdiskaddr 0x02000000;" \ 757 "setenv fdtaddr 0x00c00000;" \ 758 "setenv loadaddr 0x1000000;" \ 759 "bootm $loadaddr $ramdiskaddr $fdtaddr" 760 761 #define CONFIG_HDBOOT \ 762 "setenv bootargs root=/dev/$bdev rw " \ 763 "console=$consoledev,$baudrate $othbootargs;" \ 764 "tftp $loadaddr $bootfile;" \ 765 "tftp $fdtaddr $fdtfile;" \ 766 "bootm $loadaddr - $fdtaddr" 767 768 #define CONFIG_NFSBOOTCOMMAND \ 769 "setenv bootargs root=/dev/nfs rw " \ 770 "nfsroot=$serverip:$rootpath " \ 771 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 772 "console=$consoledev,$baudrate $othbootargs;" \ 773 "tftp $loadaddr $bootfile;" \ 774 "tftp $fdtaddr $fdtfile;" \ 775 "bootm $loadaddr - $fdtaddr" 776 777 #define CONFIG_RAMBOOTCOMMAND \ 778 "setenv bootargs root=/dev/ram rw " \ 779 "console=$consoledev,$baudrate $othbootargs;" \ 780 "tftp $ramdiskaddr $ramdiskfile;" \ 781 "tftp $loadaddr $bootfile;" \ 782 "tftp $fdtaddr $fdtfile;" \ 783 "bootm $loadaddr $ramdiskaddr $fdtaddr" 784 785 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 786 787 #include <asm/fsl_secure_boot.h> 788 789 #endif /* __CONFIG_H */ 790