1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 /* support deep sleep */ 46 #define CONFIG_DEEP_SLEEP 47 #if defined(CONFIG_DEEP_SLEEP) 48 #define CONFIG_BOARD_EARLY_INIT_F 49 #endif 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 61 #define CONFIG_FSL_IFC /* Enable IFC Support */ 62 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 63 #define CONFIG_PCI_INDIRECT_BRIDGE 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_PCIE3 /* PCIE controller 3 */ 67 #define CONFIG_PCIE4 /* PCIE controller 4 */ 68 69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 71 72 #define CONFIG_FSL_LAW /* Use common FSL init code */ 73 74 #define CONFIG_ENV_OVERWRITE 75 76 #ifdef CONFIG_SYS_NO_FLASH 77 #define CONFIG_ENV_IS_NOWHERE 78 #else 79 #define CONFIG_FLASH_CFI_DRIVER 80 #define CONFIG_SYS_FLASH_CFI 81 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 82 #endif 83 84 #ifndef CONFIG_SYS_NO_FLASH 85 #if defined(CONFIG_SPIFLASH) 86 #define CONFIG_SYS_EXTRA_ENV_RELOC 87 #define CONFIG_ENV_IS_IN_SPI_FLASH 88 #define CONFIG_ENV_SPI_BUS 0 89 #define CONFIG_ENV_SPI_CS 0 90 #define CONFIG_ENV_SPI_MAX_HZ 10000000 91 #define CONFIG_ENV_SPI_MODE 0 92 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 93 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 94 #define CONFIG_ENV_SECT_SIZE 0x10000 95 #elif defined(CONFIG_SDCARD) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_MMC 98 #define CONFIG_SYS_MMC_ENV_DEV 0 99 #define CONFIG_ENV_SIZE 0x2000 100 #define CONFIG_ENV_OFFSET (512 * 1658) 101 #elif defined(CONFIG_NAND) 102 #define CONFIG_SYS_EXTRA_ENV_RELOC 103 #define CONFIG_ENV_IS_IN_NAND 104 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 105 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 106 #else 107 #define CONFIG_ENV_IS_IN_FLASH 108 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 111 #endif 112 #else /* CONFIG_SYS_NO_FLASH */ 113 #define CONFIG_ENV_SIZE 0x2000 114 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 115 #endif 116 117 #ifndef __ASSEMBLY__ 118 unsigned long get_board_sys_clk(void); 119 unsigned long get_board_ddr_clk(void); 120 #endif 121 122 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 123 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 124 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_SYS_CACHE_STASHING 129 #define CONFIG_BACKSIDE_L2_CACHE 130 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 131 #define CONFIG_BTB /* toggle branch predition */ 132 #define CONFIG_DDR_ECC 133 #ifdef CONFIG_DDR_ECC 134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 135 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 136 #endif 137 138 #define CONFIG_ENABLE_36BIT_PHYS 139 140 #define CONFIG_ADDR_MAP 141 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 142 143 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 144 #define CONFIG_SYS_MEMTEST_END 0x00400000 145 #define CONFIG_SYS_ALT_MEMTEST 146 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 147 148 /* 149 * Config the L3 Cache as L3 SRAM 150 */ 151 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 152 153 #define CONFIG_SYS_DCSRBAR 0xf0000000 154 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 155 156 /* EEPROM */ 157 #define CONFIG_ID_EEPROM 158 #define CONFIG_SYS_I2C_EEPROM_NXID 159 #define CONFIG_SYS_EEPROM_BUS_NUM 0 160 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 161 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 164 165 /* 166 * DDR Setup 167 */ 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 172 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 173 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 174 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 175 176 #define CONFIG_DDR_SPD 177 #ifndef CONFIG_SYS_FSL_DDR4 178 #define CONFIG_SYS_FSL_DDR3 179 #endif 180 #define CONFIG_FSL_DDR_INTERACTIVE 181 182 #define CONFIG_SYS_SPD_BUS_NUM 0 183 #define SPD_EEPROM_ADDRESS 0x51 184 185 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 186 187 /* 188 * IFC Definitions 189 */ 190 #define CONFIG_SYS_FLASH_BASE 0xe0000000 191 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 192 193 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 194 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 195 + 0x8000000) | \ 196 CSPR_PORT_SIZE_16 | \ 197 CSPR_MSEL_NOR | \ 198 CSPR_V) 199 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 200 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 201 CSPR_PORT_SIZE_16 | \ 202 CSPR_MSEL_NOR | \ 203 CSPR_V) 204 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 205 206 /* 207 * TDM Definition 208 */ 209 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 210 211 /* NOR Flash Timing Params */ 212 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 213 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 214 FTIM0_NOR_TEADC(0x5) | \ 215 FTIM0_NOR_TEAHC(0x5)) 216 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 217 FTIM1_NOR_TRAD_NOR(0x1A) |\ 218 FTIM1_NOR_TSEQRAD_NOR(0x13)) 219 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 220 FTIM2_NOR_TCH(0x4) | \ 221 FTIM2_NOR_TWPH(0x0E) | \ 222 FTIM2_NOR_TWP(0x1c)) 223 #define CONFIG_SYS_NOR_FTIM3 0x0 224 225 #define CONFIG_SYS_FLASH_QUIET_TEST 226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 227 228 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 232 233 #define CONFIG_SYS_FLASH_EMPTY_INFO 234 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 235 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 236 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 237 #define QIXIS_BASE 0xffdf0000 238 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 239 #define QIXIS_LBMAP_SWITCH 0x06 240 #define QIXIS_LBMAP_MASK 0x0f 241 #define QIXIS_LBMAP_SHIFT 0 242 #define QIXIS_LBMAP_DFLTBANK 0x00 243 #define QIXIS_LBMAP_ALTBANK 0x04 244 #define QIXIS_RST_CTL_RESET 0x31 245 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 246 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 247 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 248 #define QIXIS_RST_FORCE_MEM 0x01 249 250 #define CONFIG_SYS_CSPR3_EXT (0xf) 251 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 252 | CSPR_PORT_SIZE_8 \ 253 | CSPR_MSEL_GPCM \ 254 | CSPR_V) 255 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 256 #define CONFIG_SYS_CSOR3 0x0 257 /* QIXIS Timing parameters for IFC CS3 */ 258 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 259 FTIM0_GPCM_TEADC(0x0e) | \ 260 FTIM0_GPCM_TEAHC(0x0e)) 261 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 262 FTIM1_GPCM_TRAD(0x3f)) 263 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 264 FTIM2_GPCM_TCH(0x8) | \ 265 FTIM2_GPCM_TWP(0x1f)) 266 #define CONFIG_SYS_CS3_FTIM3 0x0 267 268 #define CONFIG_NAND_FSL_IFC 269 #define CONFIG_SYS_NAND_BASE 0xff800000 270 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 271 272 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 273 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 274 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 275 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 276 | CSPR_V) 277 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 278 279 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 280 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 281 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 282 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 283 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 284 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 285 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 286 287 #define CONFIG_SYS_NAND_ONFI_DETECTION 288 289 /* ONFI NAND Flash mode0 Timing Params */ 290 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 291 FTIM0_NAND_TWP(0x18) | \ 292 FTIM0_NAND_TWCHT(0x07) | \ 293 FTIM0_NAND_TWH(0x0a)) 294 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 295 FTIM1_NAND_TWBE(0x39) | \ 296 FTIM1_NAND_TRR(0x0e) | \ 297 FTIM1_NAND_TRP(0x18)) 298 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 299 FTIM2_NAND_TREH(0x0a) | \ 300 FTIM2_NAND_TWHRE(0x1e)) 301 #define CONFIG_SYS_NAND_FTIM3 0x0 302 303 #define CONFIG_SYS_NAND_DDR_LAW 11 304 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 305 #define CONFIG_SYS_MAX_NAND_DEVICE 1 306 #define CONFIG_CMD_NAND 307 308 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 309 310 #if defined(CONFIG_NAND) 311 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 312 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 313 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 314 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 315 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 316 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 317 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 318 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 319 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 327 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 328 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 329 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 330 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 331 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 332 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 333 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 334 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 335 #else 336 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 344 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 345 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 346 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 347 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 348 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 349 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 350 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 351 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 352 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 353 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 354 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 355 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 356 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 357 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 358 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 359 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 360 #endif 361 362 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 363 364 #if defined(CONFIG_RAMBOOT_PBL) 365 #define CONFIG_SYS_RAMBOOT 366 #endif 367 368 #define CONFIG_BOARD_EARLY_INIT_R 369 #define CONFIG_MISC_INIT_R 370 371 #define CONFIG_HWCONFIG 372 373 /* define to use L1 as initial stack */ 374 #define CONFIG_L1_INIT_RAM 375 #define CONFIG_SYS_INIT_RAM_LOCK 376 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 379 /* The assembler doesn't like typecast */ 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 381 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 382 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 383 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 384 385 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 386 GENERATED_GBL_DATA_SIZE) 387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 388 389 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 390 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 391 392 /* Serial Port - controlled on board with jumper J8 393 * open - index 2 394 * shorted - index 1 395 */ 396 #define CONFIG_CONS_INDEX 1 397 #define CONFIG_SYS_NS16550_SERIAL 398 #define CONFIG_SYS_NS16550_REG_SIZE 1 399 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 400 401 #define CONFIG_SYS_BAUDRATE_TABLE \ 402 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 403 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 406 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 407 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 408 409 /* Video */ 410 #define CONFIG_FSL_DIU_FB 411 #ifdef CONFIG_FSL_DIU_FB 412 #define CONFIG_FSL_DIU_CH7301 413 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 414 #define CONFIG_CMD_BMP 415 #define CONFIG_VIDEO_LOGO 416 #define CONFIG_VIDEO_BMP_LOGO 417 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 418 /* 419 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 420 * disable empty flash sector detection, which is I/O-intensive. 421 */ 422 #undef CONFIG_SYS_FLASH_EMPTY_INFO 423 #endif 424 425 /* I2C */ 426 #define CONFIG_SYS_I2C 427 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 428 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 429 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 430 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 431 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 432 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 433 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 434 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 437 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 438 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 439 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 440 441 #define I2C_MUX_PCA_ADDR 0x77 442 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 443 444 /* I2C bus multiplexer */ 445 #define I2C_MUX_CH_DEFAULT 0x8 446 #define I2C_MUX_CH_DIU 0xC 447 448 /* LDI/DVI Encoder for display */ 449 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 450 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 451 452 /* 453 * RTC configuration 454 */ 455 #define RTC 456 #define CONFIG_RTC_DS3231 1 457 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 458 459 /* 460 * eSPI - Enhanced SPI 461 */ 462 #define CONFIG_SF_DEFAULT_SPEED 10000000 463 #define CONFIG_SF_DEFAULT_MODE 0 464 465 /* 466 * General PCI 467 * Memory space is mapped 1-1, but I/O space must start from 0. 468 */ 469 470 #ifdef CONFIG_PCI 471 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 472 #ifdef CONFIG_PCIE1 473 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 474 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 475 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 476 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 477 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 478 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 479 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 480 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 481 #endif 482 483 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 484 #ifdef CONFIG_PCIE2 485 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 486 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 487 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 488 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 489 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 490 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 491 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 492 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 493 #endif 494 495 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 496 #ifdef CONFIG_PCIE3 497 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 498 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 499 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 500 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 501 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 502 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 503 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 504 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 505 #endif 506 507 /* controller 4, Base address 203000 */ 508 #ifdef CONFIG_PCIE4 509 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 510 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 512 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 513 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 514 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 516 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 517 #endif 518 519 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 520 #define CONFIG_DOS_PARTITION 521 #endif /* CONFIG_PCI */ 522 523 /* SATA */ 524 #define CONFIG_FSL_SATA_V2 525 #ifdef CONFIG_FSL_SATA_V2 526 #define CONFIG_LIBATA 527 #define CONFIG_FSL_SATA 528 529 #define CONFIG_SYS_SATA_MAX_DEVICE 2 530 #define CONFIG_SATA1 531 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 532 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 533 #define CONFIG_SATA2 534 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 535 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 536 537 #define CONFIG_LBA48 538 #define CONFIG_CMD_SATA 539 #define CONFIG_DOS_PARTITION 540 #endif 541 542 /* 543 * USB 544 */ 545 #define CONFIG_HAS_FSL_DR_USB 546 547 #ifdef CONFIG_HAS_FSL_DR_USB 548 #define CONFIG_USB_EHCI 549 550 #ifdef CONFIG_USB_EHCI 551 #define CONFIG_USB_EHCI_FSL 552 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 553 #endif 554 #endif 555 556 #define CONFIG_MMC 557 558 #ifdef CONFIG_MMC 559 #define CONFIG_FSL_ESDHC 560 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 561 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 562 #define CONFIG_GENERIC_MMC 563 #define CONFIG_DOS_PARTITION 564 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 565 #endif 566 567 /* Qman/Bman */ 568 #ifndef CONFIG_NOBQFMAN 569 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 570 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 571 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 572 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 573 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 574 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 575 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 576 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 577 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 578 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 579 CONFIG_SYS_BMAN_CENA_SIZE) 580 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 582 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 583 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 584 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 585 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 586 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 587 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 588 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 589 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 590 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 591 CONFIG_SYS_QMAN_CENA_SIZE) 592 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 593 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 594 595 #define CONFIG_SYS_DPAA_FMAN 596 #define CONFIG_SYS_DPAA_PME 597 598 #define CONFIG_QE 599 #define CONFIG_U_QE 600 /* Default address of microcode for the Linux Fman driver */ 601 #if defined(CONFIG_SPIFLASH) 602 /* 603 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 604 * env, so we got 0x110000. 605 */ 606 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 607 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 608 #elif defined(CONFIG_SDCARD) 609 /* 610 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 611 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 612 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 613 */ 614 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 615 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 616 #elif defined(CONFIG_NAND) 617 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 618 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 619 #else 620 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 621 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 622 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 623 #endif 624 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 625 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 626 #endif /* CONFIG_NOBQFMAN */ 627 628 #ifdef CONFIG_SYS_DPAA_FMAN 629 #define CONFIG_FMAN_ENET 630 #define CONFIG_PHYLIB_10G 631 #define CONFIG_PHY_VITESSE 632 #define CONFIG_PHY_REALTEK 633 #define CONFIG_PHY_TERANETICS 634 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 635 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 636 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 637 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 638 #endif 639 640 #ifdef CONFIG_FMAN_ENET 641 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 642 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 643 644 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 645 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 646 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 647 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 648 649 #define CONFIG_MII /* MII PHY management */ 650 #define CONFIG_ETHPRIME "FM1@DTSEC1" 651 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 652 #endif 653 654 /* Enable VSC9953 L2 Switch driver */ 655 #define CONFIG_VSC9953 656 #define CONFIG_CMD_ETHSW 657 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 658 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 659 660 /* 661 * Dynamic MTD Partition support with mtdparts 662 */ 663 #ifndef CONFIG_SYS_NO_FLASH 664 #define CONFIG_MTD_DEVICE 665 #define CONFIG_MTD_PARTITIONS 666 #define CONFIG_CMD_MTDPARTS 667 #define CONFIG_FLASH_CFI_MTD 668 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 669 "spi0=spife110000.0" 670 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 671 "128k(dtb),96m(fs),-(user);"\ 672 "fff800000.flash:2m(uboot),9m(kernel),"\ 673 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 674 "2m(uboot),9m(kernel),128k(dtb),-(user)" 675 #endif 676 677 /* 678 * Environment 679 */ 680 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 682 683 /* 684 * Command line configuration. 685 */ 686 #define CONFIG_CMD_DATE 687 #define CONFIG_CMD_EEPROM 688 #define CONFIG_CMD_ERRATA 689 #define CONFIG_CMD_IRQ 690 #define CONFIG_CMD_REGINFO 691 692 #ifdef CONFIG_PCI 693 #define CONFIG_CMD_PCI 694 #endif 695 696 /* Hash command with SHA acceleration supported in hardware */ 697 #ifdef CONFIG_FSL_CAAM 698 #define CONFIG_CMD_HASH 699 #define CONFIG_SHA_HW_ACCEL 700 #endif 701 702 /* 703 * Miscellaneous configurable options 704 */ 705 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 706 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 707 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 708 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 709 #ifdef CONFIG_CMD_KGDB 710 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 711 #else 712 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 713 #endif 714 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 715 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 716 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 717 718 /* 719 * For booting Linux, the board info and command line data 720 * have to be in the first 64 MB of memory, since this is 721 * the maximum mapped by the Linux kernel during initialization. 722 */ 723 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 724 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 725 726 #ifdef CONFIG_CMD_KGDB 727 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 728 #endif 729 730 /* 731 * Environment Configuration 732 */ 733 #define CONFIG_ROOTPATH "/opt/nfsroot" 734 #define CONFIG_BOOTFILE "uImage" 735 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 736 737 /* default location for tftp and bootm */ 738 #define CONFIG_LOADADDR 1000000 739 740 741 #define CONFIG_BAUDRATE 115200 742 743 #define __USB_PHY_TYPE utmi 744 745 #define CONFIG_EXTRA_ENV_SETTINGS \ 746 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 747 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 748 "netdev=eth0\0" \ 749 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 750 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 751 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 752 "tftpflash=tftpboot $loadaddr $uboot && " \ 753 "protect off $ubootaddr +$filesize && " \ 754 "erase $ubootaddr +$filesize && " \ 755 "cp.b $loadaddr $ubootaddr $filesize && " \ 756 "protect on $ubootaddr +$filesize && " \ 757 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 758 "consoledev=ttyS0\0" \ 759 "ramdiskaddr=2000000\0" \ 760 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 761 "fdtaddr=1e00000\0" \ 762 "fdtfile=t1040qds/t1040qds.dtb\0" \ 763 "bdev=sda3\0" 764 765 #define CONFIG_LINUX \ 766 "setenv bootargs root=/dev/ram rw " \ 767 "console=$consoledev,$baudrate $othbootargs;" \ 768 "setenv ramdiskaddr 0x02000000;" \ 769 "setenv fdtaddr 0x00c00000;" \ 770 "setenv loadaddr 0x1000000;" \ 771 "bootm $loadaddr $ramdiskaddr $fdtaddr" 772 773 #define CONFIG_HDBOOT \ 774 "setenv bootargs root=/dev/$bdev rw " \ 775 "console=$consoledev,$baudrate $othbootargs;" \ 776 "tftp $loadaddr $bootfile;" \ 777 "tftp $fdtaddr $fdtfile;" \ 778 "bootm $loadaddr - $fdtaddr" 779 780 #define CONFIG_NFSBOOTCOMMAND \ 781 "setenv bootargs root=/dev/nfs rw " \ 782 "nfsroot=$serverip:$rootpath " \ 783 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr - $fdtaddr" 788 789 #define CONFIG_RAMBOOTCOMMAND \ 790 "setenv bootargs root=/dev/ram rw " \ 791 "console=$consoledev,$baudrate $othbootargs;" \ 792 "tftp $ramdiskaddr $ramdiskfile;" \ 793 "tftp $loadaddr $bootfile;" \ 794 "tftp $fdtaddr $fdtfile;" \ 795 "bootm $loadaddr $ramdiskaddr $fdtaddr" 796 797 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 798 799 #include <asm/fsl_secure_boot.h> 800 801 #endif /* __CONFIG_H */ 802