1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 40 /* support deep sleep */ 41 #define CONFIG_DEEP_SLEEP 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 49 #define CONFIG_PCI_INDIRECT_BRIDGE 50 #define CONFIG_PCIE1 /* PCIE controller 1 */ 51 #define CONFIG_PCIE2 /* PCIE controller 2 */ 52 #define CONFIG_PCIE3 /* PCIE controller 3 */ 53 #define CONFIG_PCIE4 /* PCIE controller 4 */ 54 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #ifdef CONFIG_MTD_NOR_FLASH 61 #if defined(CONFIG_SPIFLASH) 62 #define CONFIG_ENV_SPI_BUS 0 63 #define CONFIG_ENV_SPI_CS 0 64 #define CONFIG_ENV_SPI_MAX_HZ 10000000 65 #define CONFIG_ENV_SPI_MODE 0 66 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 67 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 68 #define CONFIG_ENV_SECT_SIZE 0x10000 69 #elif defined(CONFIG_SDCARD) 70 #define CONFIG_SYS_MMC_ENV_DEV 0 71 #define CONFIG_ENV_SIZE 0x2000 72 #define CONFIG_ENV_OFFSET (512 * 1658) 73 #elif defined(CONFIG_NAND) 74 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 75 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 76 #else 77 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 78 #define CONFIG_ENV_SIZE 0x2000 79 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 80 #endif 81 #else /* CONFIG_MTD_NOR_FLASH */ 82 #define CONFIG_ENV_SIZE 0x2000 83 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 84 #endif 85 86 #ifndef __ASSEMBLY__ 87 unsigned long get_board_sys_clk(void); 88 unsigned long get_board_ddr_clk(void); 89 #endif 90 91 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 92 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 93 94 /* 95 * These can be toggled for performance analysis, otherwise use default. 96 */ 97 #define CONFIG_SYS_CACHE_STASHING 98 #define CONFIG_BACKSIDE_L2_CACHE 99 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 100 #define CONFIG_BTB /* toggle branch predition */ 101 #define CONFIG_DDR_ECC 102 #ifdef CONFIG_DDR_ECC 103 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 104 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 105 #endif 106 107 #define CONFIG_ENABLE_36BIT_PHYS 108 109 #define CONFIG_ADDR_MAP 110 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 111 112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_END 0x00400000 114 115 /* 116 * Config the L3 Cache as L3 SRAM 117 */ 118 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 119 120 #define CONFIG_SYS_DCSRBAR 0xf0000000 121 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 122 123 /* EEPROM */ 124 #define CONFIG_ID_EEPROM 125 #define CONFIG_SYS_I2C_EEPROM_NXID 126 #define CONFIG_SYS_EEPROM_BUS_NUM 0 127 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 128 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 129 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 130 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 131 132 /* 133 * DDR Setup 134 */ 135 #define CONFIG_VERY_BIG_RAM 136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 138 139 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 140 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 141 142 #define CONFIG_DDR_SPD 143 144 #define CONFIG_SYS_SPD_BUS_NUM 0 145 #define SPD_EEPROM_ADDRESS 0x51 146 147 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 148 149 /* 150 * IFC Definitions 151 */ 152 #define CONFIG_SYS_FLASH_BASE 0xe0000000 153 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 154 155 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 156 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 157 + 0x8000000) | \ 158 CSPR_PORT_SIZE_16 | \ 159 CSPR_MSEL_NOR | \ 160 CSPR_V) 161 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 162 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 163 CSPR_PORT_SIZE_16 | \ 164 CSPR_MSEL_NOR | \ 165 CSPR_V) 166 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 167 168 /* 169 * TDM Definition 170 */ 171 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 172 173 /* NOR Flash Timing Params */ 174 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 176 FTIM0_NOR_TEADC(0x5) | \ 177 FTIM0_NOR_TEAHC(0x5)) 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 179 FTIM1_NOR_TRAD_NOR(0x1A) |\ 180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \ 183 FTIM2_NOR_TWPH(0x0E) | \ 184 FTIM2_NOR_TWP(0x1c)) 185 #define CONFIG_SYS_NOR_FTIM3 0x0 186 187 #define CONFIG_SYS_FLASH_QUIET_TEST 188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 189 190 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 194 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 197 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 198 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 199 #define QIXIS_BASE 0xffdf0000 200 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 201 #define QIXIS_LBMAP_SWITCH 0x06 202 #define QIXIS_LBMAP_MASK 0x0f 203 #define QIXIS_LBMAP_SHIFT 0 204 #define QIXIS_LBMAP_DFLTBANK 0x00 205 #define QIXIS_LBMAP_ALTBANK 0x04 206 #define QIXIS_RST_CTL_RESET 0x31 207 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 208 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 209 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 210 #define QIXIS_RST_FORCE_MEM 0x01 211 212 #define CONFIG_SYS_CSPR3_EXT (0xf) 213 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 214 | CSPR_PORT_SIZE_8 \ 215 | CSPR_MSEL_GPCM \ 216 | CSPR_V) 217 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 218 #define CONFIG_SYS_CSOR3 0x0 219 /* QIXIS Timing parameters for IFC CS3 */ 220 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 221 FTIM0_GPCM_TEADC(0x0e) | \ 222 FTIM0_GPCM_TEAHC(0x0e)) 223 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 224 FTIM1_GPCM_TRAD(0x3f)) 225 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 226 FTIM2_GPCM_TCH(0x8) | \ 227 FTIM2_GPCM_TWP(0x1f)) 228 #define CONFIG_SYS_CS3_FTIM3 0x0 229 230 #define CONFIG_NAND_FSL_IFC 231 #define CONFIG_SYS_NAND_BASE 0xff800000 232 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 233 234 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 235 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 236 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 237 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 238 | CSPR_V) 239 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 240 241 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 242 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 243 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 244 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 245 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 246 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 247 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 248 249 #define CONFIG_SYS_NAND_ONFI_DETECTION 250 251 /* ONFI NAND Flash mode0 Timing Params */ 252 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 253 FTIM0_NAND_TWP(0x18) | \ 254 FTIM0_NAND_TWCHT(0x07) | \ 255 FTIM0_NAND_TWH(0x0a)) 256 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 257 FTIM1_NAND_TWBE(0x39) | \ 258 FTIM1_NAND_TRR(0x0e) | \ 259 FTIM1_NAND_TRP(0x18)) 260 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 261 FTIM2_NAND_TREH(0x0a) | \ 262 FTIM2_NAND_TWHRE(0x1e)) 263 #define CONFIG_SYS_NAND_FTIM3 0x0 264 265 #define CONFIG_SYS_NAND_DDR_LAW 11 266 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 267 #define CONFIG_SYS_MAX_NAND_DEVICE 1 268 269 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 270 271 #if defined(CONFIG_NAND) 272 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 273 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 274 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 275 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 276 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 277 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 278 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 279 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 280 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 281 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 282 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 283 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 284 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 285 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 286 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 287 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 288 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 289 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 290 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 291 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 292 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 293 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 294 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 295 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 296 #else 297 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 298 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 299 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 300 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 301 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 302 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 303 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 304 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 305 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 306 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 307 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 314 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 315 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 316 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 317 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 318 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 319 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 320 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 321 #endif 322 323 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 324 325 #if defined(CONFIG_RAMBOOT_PBL) 326 #define CONFIG_SYS_RAMBOOT 327 #endif 328 329 #define CONFIG_HWCONFIG 330 331 /* define to use L1 as initial stack */ 332 #define CONFIG_L1_INIT_RAM 333 #define CONFIG_SYS_INIT_RAM_LOCK 334 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 335 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 336 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 337 /* The assembler doesn't like typecast */ 338 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 339 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 340 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 341 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 342 343 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 344 GENERATED_GBL_DATA_SIZE) 345 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 346 347 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 348 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 349 350 /* Serial Port - controlled on board with jumper J8 351 * open - index 2 352 * shorted - index 1 353 */ 354 #define CONFIG_SYS_NS16550_SERIAL 355 #define CONFIG_SYS_NS16550_REG_SIZE 1 356 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 357 358 #define CONFIG_SYS_BAUDRATE_TABLE \ 359 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 360 361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 363 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 364 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 365 366 /* Video */ 367 #define CONFIG_FSL_DIU_FB 368 #ifdef CONFIG_FSL_DIU_FB 369 #define CONFIG_FSL_DIU_CH7301 370 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 371 #define CONFIG_VIDEO_LOGO 372 #define CONFIG_VIDEO_BMP_LOGO 373 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 374 /* 375 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 376 * disable empty flash sector detection, which is I/O-intensive. 377 */ 378 #undef CONFIG_SYS_FLASH_EMPTY_INFO 379 #endif 380 381 /* I2C */ 382 #define CONFIG_SYS_I2C 383 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 384 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 385 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 386 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 387 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 388 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 389 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 390 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 391 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 392 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 393 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 394 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 395 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 396 397 #define I2C_MUX_PCA_ADDR 0x77 398 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 399 400 /* I2C bus multiplexer */ 401 #define I2C_MUX_CH_DEFAULT 0x8 402 #define I2C_MUX_CH_DIU 0xC 403 404 /* LDI/DVI Encoder for display */ 405 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 406 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 407 408 /* 409 * RTC configuration 410 */ 411 #define RTC 412 #define CONFIG_RTC_DS3231 1 413 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 414 415 /* 416 * eSPI - Enhanced SPI 417 */ 418 #define CONFIG_SF_DEFAULT_SPEED 10000000 419 #define CONFIG_SF_DEFAULT_MODE 0 420 421 /* 422 * General PCI 423 * Memory space is mapped 1-1, but I/O space must start from 0. 424 */ 425 426 #ifdef CONFIG_PCI 427 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 428 #ifdef CONFIG_PCIE1 429 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 430 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 432 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 433 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 434 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 435 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 436 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 437 #endif 438 439 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 440 #ifdef CONFIG_PCIE2 441 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 442 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 443 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 444 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 445 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 446 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 447 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 448 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 449 #endif 450 451 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 452 #ifdef CONFIG_PCIE3 453 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 454 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 455 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 456 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 457 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 458 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 459 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 460 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 461 #endif 462 463 /* controller 4, Base address 203000 */ 464 #ifdef CONFIG_PCIE4 465 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 466 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 467 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 468 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 469 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 470 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 471 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 472 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 473 #endif 474 475 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 476 #endif /* CONFIG_PCI */ 477 478 /* SATA */ 479 #define CONFIG_FSL_SATA_V2 480 #ifdef CONFIG_FSL_SATA_V2 481 #define CONFIG_SYS_SATA_MAX_DEVICE 2 482 #define CONFIG_SATA1 483 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 484 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 485 #define CONFIG_SATA2 486 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 487 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 488 489 #define CONFIG_LBA48 490 #endif 491 492 /* 493 * USB 494 */ 495 #define CONFIG_HAS_FSL_DR_USB 496 497 #ifdef CONFIG_HAS_FSL_DR_USB 498 #ifdef CONFIG_USB_EHCI_HCD 499 #define CONFIG_USB_EHCI_FSL 500 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 501 #endif 502 #endif 503 504 #ifdef CONFIG_MMC 505 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 506 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 507 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 508 #endif 509 510 /* Qman/Bman */ 511 #ifndef CONFIG_NOBQFMAN 512 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 513 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 514 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 515 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 516 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 517 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 518 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 519 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 520 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 521 CONFIG_SYS_BMAN_CENA_SIZE) 522 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 523 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 524 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 525 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 526 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 527 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 528 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 529 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 530 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 531 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 532 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 533 CONFIG_SYS_QMAN_CENA_SIZE) 534 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 535 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 536 537 #define CONFIG_SYS_DPAA_FMAN 538 #define CONFIG_SYS_DPAA_PME 539 540 #define CONFIG_QE 541 /* Default address of microcode for the Linux Fman driver */ 542 #if defined(CONFIG_SPIFLASH) 543 /* 544 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 545 * env, so we got 0x110000. 546 */ 547 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 548 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 549 #elif defined(CONFIG_SDCARD) 550 /* 551 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 552 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 553 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 554 */ 555 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 556 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 557 #elif defined(CONFIG_NAND) 558 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 559 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 560 #else 561 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 562 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 563 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 564 #endif 565 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 566 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 567 #endif /* CONFIG_NOBQFMAN */ 568 569 #ifdef CONFIG_SYS_DPAA_FMAN 570 #define CONFIG_FMAN_ENET 571 #define CONFIG_PHYLIB_10G 572 #define CONFIG_PHY_VITESSE 573 #define CONFIG_PHY_REALTEK 574 #define CONFIG_PHY_TERANETICS 575 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 576 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 577 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 578 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 579 #endif 580 581 #ifdef CONFIG_FMAN_ENET 582 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 583 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 584 585 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 586 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 587 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 588 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 589 590 #define CONFIG_ETHPRIME "FM1@DTSEC1" 591 #endif 592 593 /* Enable VSC9953 L2 Switch driver */ 594 #define CONFIG_VSC9953 595 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 596 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 597 598 /* 599 * Dynamic MTD Partition support with mtdparts 600 */ 601 602 /* 603 * Environment 604 */ 605 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 606 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 607 608 /* 609 * Miscellaneous configurable options 610 */ 611 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 612 613 /* 614 * For booting Linux, the board info and command line data 615 * have to be in the first 64 MB of memory, since this is 616 * the maximum mapped by the Linux kernel during initialization. 617 */ 618 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 619 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 620 621 #ifdef CONFIG_CMD_KGDB 622 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 623 #endif 624 625 /* 626 * Environment Configuration 627 */ 628 #define CONFIG_ROOTPATH "/opt/nfsroot" 629 #define CONFIG_BOOTFILE "uImage" 630 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 631 632 /* default location for tftp and bootm */ 633 #define CONFIG_LOADADDR 1000000 634 635 #define __USB_PHY_TYPE utmi 636 637 #define CONFIG_EXTRA_ENV_SETTINGS \ 638 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 639 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 640 "netdev=eth0\0" \ 641 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 642 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 643 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 644 "tftpflash=tftpboot $loadaddr $uboot && " \ 645 "protect off $ubootaddr +$filesize && " \ 646 "erase $ubootaddr +$filesize && " \ 647 "cp.b $loadaddr $ubootaddr $filesize && " \ 648 "protect on $ubootaddr +$filesize && " \ 649 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 650 "consoledev=ttyS0\0" \ 651 "ramdiskaddr=2000000\0" \ 652 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 653 "fdtaddr=1e00000\0" \ 654 "fdtfile=t1040qds/t1040qds.dtb\0" \ 655 "bdev=sda3\0" 656 657 #define CONFIG_LINUX \ 658 "setenv bootargs root=/dev/ram rw " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "setenv ramdiskaddr 0x02000000;" \ 661 "setenv fdtaddr 0x00c00000;" \ 662 "setenv loadaddr 0x1000000;" \ 663 "bootm $loadaddr $ramdiskaddr $fdtaddr" 664 665 #define CONFIG_HDBOOT \ 666 "setenv bootargs root=/dev/$bdev rw " \ 667 "console=$consoledev,$baudrate $othbootargs;" \ 668 "tftp $loadaddr $bootfile;" \ 669 "tftp $fdtaddr $fdtfile;" \ 670 "bootm $loadaddr - $fdtaddr" 671 672 #define CONFIG_NFSBOOTCOMMAND \ 673 "setenv bootargs root=/dev/nfs rw " \ 674 "nfsroot=$serverip:$rootpath " \ 675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 676 "console=$consoledev,$baudrate $othbootargs;" \ 677 "tftp $loadaddr $bootfile;" \ 678 "tftp $fdtaddr $fdtfile;" \ 679 "bootm $loadaddr - $fdtaddr" 680 681 #define CONFIG_RAMBOOTCOMMAND \ 682 "setenv bootargs root=/dev/ram rw " \ 683 "console=$consoledev,$baudrate $othbootargs;" \ 684 "tftp $ramdiskaddr $ramdiskfile;" \ 685 "tftp $loadaddr $bootfile;" \ 686 "tftp $fdtaddr $fdtfile;" \ 687 "bootm $loadaddr $ramdiskaddr $fdtaddr" 688 689 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 690 691 #include <asm/fsl_secure_boot.h> 692 693 #endif /* __CONFIG_H */ 694