1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 /* support deep sleep */ 46 #define CONFIG_DEEP_SLEEP 47 #if defined(CONFIG_DEEP_SLEEP) 48 #define CONFIG_BOARD_EARLY_INIT_F 49 #endif 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 61 #define CONFIG_FSL_IFC /* Enable IFC Support */ 62 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 63 #define CONFIG_PCI_INDIRECT_BRIDGE 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_PCIE3 /* PCIE controller 3 */ 67 #define CONFIG_PCIE4 /* PCIE controller 4 */ 68 69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 71 72 #define CONFIG_ENV_OVERWRITE 73 74 #ifdef CONFIG_SYS_NO_FLASH 75 #define CONFIG_ENV_IS_NOWHERE 76 #else 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 80 #endif 81 82 #ifndef CONFIG_SYS_NO_FLASH 83 #if defined(CONFIG_SPIFLASH) 84 #define CONFIG_SYS_EXTRA_ENV_RELOC 85 #define CONFIG_ENV_IS_IN_SPI_FLASH 86 #define CONFIG_ENV_SPI_BUS 0 87 #define CONFIG_ENV_SPI_CS 0 88 #define CONFIG_ENV_SPI_MAX_HZ 10000000 89 #define CONFIG_ENV_SPI_MODE 0 90 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 91 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 92 #define CONFIG_ENV_SECT_SIZE 0x10000 93 #elif defined(CONFIG_SDCARD) 94 #define CONFIG_SYS_EXTRA_ENV_RELOC 95 #define CONFIG_ENV_IS_IN_MMC 96 #define CONFIG_SYS_MMC_ENV_DEV 0 97 #define CONFIG_ENV_SIZE 0x2000 98 #define CONFIG_ENV_OFFSET (512 * 1658) 99 #elif defined(CONFIG_NAND) 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_ENV_IS_IN_NAND 102 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 103 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 104 #else 105 #define CONFIG_ENV_IS_IN_FLASH 106 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #endif 110 #else /* CONFIG_SYS_NO_FLASH */ 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 113 #endif 114 115 #ifndef __ASSEMBLY__ 116 unsigned long get_board_sys_clk(void); 117 unsigned long get_board_ddr_clk(void); 118 #endif 119 120 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 121 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 122 123 /* 124 * These can be toggled for performance analysis, otherwise use default. 125 */ 126 #define CONFIG_SYS_CACHE_STASHING 127 #define CONFIG_BACKSIDE_L2_CACHE 128 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #define CONFIG_ENABLE_36BIT_PHYS 137 138 #define CONFIG_ADDR_MAP 139 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 140 141 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 142 #define CONFIG_SYS_MEMTEST_END 0x00400000 143 #define CONFIG_SYS_ALT_MEMTEST 144 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 145 146 /* 147 * Config the L3 Cache as L3 SRAM 148 */ 149 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 150 151 #define CONFIG_SYS_DCSRBAR 0xf0000000 152 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 153 154 /* EEPROM */ 155 #define CONFIG_ID_EEPROM 156 #define CONFIG_SYS_I2C_EEPROM_NXID 157 #define CONFIG_SYS_EEPROM_BUS_NUM 0 158 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 160 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 162 163 /* 164 * DDR Setup 165 */ 166 #define CONFIG_VERY_BIG_RAM 167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 169 170 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 171 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 172 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 173 174 #define CONFIG_DDR_SPD 175 #ifndef CONFIG_SYS_FSL_DDR4 176 #define CONFIG_SYS_FSL_DDR3 177 #endif 178 #define CONFIG_FSL_DDR_INTERACTIVE 179 180 #define CONFIG_SYS_SPD_BUS_NUM 0 181 #define SPD_EEPROM_ADDRESS 0x51 182 183 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 184 185 /* 186 * IFC Definitions 187 */ 188 #define CONFIG_SYS_FLASH_BASE 0xe0000000 189 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 190 191 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 192 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 193 + 0x8000000) | \ 194 CSPR_PORT_SIZE_16 | \ 195 CSPR_MSEL_NOR | \ 196 CSPR_V) 197 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 198 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 199 CSPR_PORT_SIZE_16 | \ 200 CSPR_MSEL_NOR | \ 201 CSPR_V) 202 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 203 204 /* 205 * TDM Definition 206 */ 207 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 208 209 /* NOR Flash Timing Params */ 210 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 211 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 212 FTIM0_NOR_TEADC(0x5) | \ 213 FTIM0_NOR_TEAHC(0x5)) 214 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 215 FTIM1_NOR_TRAD_NOR(0x1A) |\ 216 FTIM1_NOR_TSEQRAD_NOR(0x13)) 217 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 218 FTIM2_NOR_TCH(0x4) | \ 219 FTIM2_NOR_TWPH(0x0E) | \ 220 FTIM2_NOR_TWP(0x1c)) 221 #define CONFIG_SYS_NOR_FTIM3 0x0 222 223 #define CONFIG_SYS_FLASH_QUIET_TEST 224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 225 226 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 231 #define CONFIG_SYS_FLASH_EMPTY_INFO 232 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 233 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 234 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 235 #define QIXIS_BASE 0xffdf0000 236 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 237 #define QIXIS_LBMAP_SWITCH 0x06 238 #define QIXIS_LBMAP_MASK 0x0f 239 #define QIXIS_LBMAP_SHIFT 0 240 #define QIXIS_LBMAP_DFLTBANK 0x00 241 #define QIXIS_LBMAP_ALTBANK 0x04 242 #define QIXIS_RST_CTL_RESET 0x31 243 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 244 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 245 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 246 #define QIXIS_RST_FORCE_MEM 0x01 247 248 #define CONFIG_SYS_CSPR3_EXT (0xf) 249 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 250 | CSPR_PORT_SIZE_8 \ 251 | CSPR_MSEL_GPCM \ 252 | CSPR_V) 253 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 254 #define CONFIG_SYS_CSOR3 0x0 255 /* QIXIS Timing parameters for IFC CS3 */ 256 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 257 FTIM0_GPCM_TEADC(0x0e) | \ 258 FTIM0_GPCM_TEAHC(0x0e)) 259 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 260 FTIM1_GPCM_TRAD(0x3f)) 261 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 262 FTIM2_GPCM_TCH(0x8) | \ 263 FTIM2_GPCM_TWP(0x1f)) 264 #define CONFIG_SYS_CS3_FTIM3 0x0 265 266 #define CONFIG_NAND_FSL_IFC 267 #define CONFIG_SYS_NAND_BASE 0xff800000 268 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 269 270 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 271 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 272 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 273 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 274 | CSPR_V) 275 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 276 277 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 278 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 279 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 280 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 281 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 282 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 283 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 284 285 #define CONFIG_SYS_NAND_ONFI_DETECTION 286 287 /* ONFI NAND Flash mode0 Timing Params */ 288 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 289 FTIM0_NAND_TWP(0x18) | \ 290 FTIM0_NAND_TWCHT(0x07) | \ 291 FTIM0_NAND_TWH(0x0a)) 292 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 293 FTIM1_NAND_TWBE(0x39) | \ 294 FTIM1_NAND_TRR(0x0e) | \ 295 FTIM1_NAND_TRP(0x18)) 296 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 297 FTIM2_NAND_TREH(0x0a) | \ 298 FTIM2_NAND_TWHRE(0x1e)) 299 #define CONFIG_SYS_NAND_FTIM3 0x0 300 301 #define CONFIG_SYS_NAND_DDR_LAW 11 302 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 303 #define CONFIG_SYS_MAX_NAND_DEVICE 1 304 #define CONFIG_CMD_NAND 305 306 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 307 308 #if defined(CONFIG_NAND) 309 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 310 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 311 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 312 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 313 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 314 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 315 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 316 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 317 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 318 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 319 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 320 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 321 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 322 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 323 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 324 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 325 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 326 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 327 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 328 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 329 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 330 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 331 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 332 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 333 #else 334 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 335 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 336 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 358 #endif 359 360 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 361 362 #if defined(CONFIG_RAMBOOT_PBL) 363 #define CONFIG_SYS_RAMBOOT 364 #endif 365 366 #define CONFIG_BOARD_EARLY_INIT_R 367 #define CONFIG_MISC_INIT_R 368 369 #define CONFIG_HWCONFIG 370 371 /* define to use L1 as initial stack */ 372 #define CONFIG_L1_INIT_RAM 373 #define CONFIG_SYS_INIT_RAM_LOCK 374 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 375 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 376 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 377 /* The assembler doesn't like typecast */ 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 379 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 380 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 381 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 382 383 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 384 GENERATED_GBL_DATA_SIZE) 385 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 386 387 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 388 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 389 390 /* Serial Port - controlled on board with jumper J8 391 * open - index 2 392 * shorted - index 1 393 */ 394 #define CONFIG_CONS_INDEX 1 395 #define CONFIG_SYS_NS16550_SERIAL 396 #define CONFIG_SYS_NS16550_REG_SIZE 1 397 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 398 399 #define CONFIG_SYS_BAUDRATE_TABLE \ 400 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 401 402 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 403 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 404 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 405 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 406 407 /* Video */ 408 #define CONFIG_FSL_DIU_FB 409 #ifdef CONFIG_FSL_DIU_FB 410 #define CONFIG_FSL_DIU_CH7301 411 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 412 #define CONFIG_CMD_BMP 413 #define CONFIG_VIDEO_LOGO 414 #define CONFIG_VIDEO_BMP_LOGO 415 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 416 /* 417 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 418 * disable empty flash sector detection, which is I/O-intensive. 419 */ 420 #undef CONFIG_SYS_FLASH_EMPTY_INFO 421 #endif 422 423 /* I2C */ 424 #define CONFIG_SYS_I2C 425 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 426 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 427 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 428 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 429 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 430 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 431 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 432 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 433 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 434 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 435 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 436 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 437 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 438 439 #define I2C_MUX_PCA_ADDR 0x77 440 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 441 442 /* I2C bus multiplexer */ 443 #define I2C_MUX_CH_DEFAULT 0x8 444 #define I2C_MUX_CH_DIU 0xC 445 446 /* LDI/DVI Encoder for display */ 447 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 448 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 449 450 /* 451 * RTC configuration 452 */ 453 #define RTC 454 #define CONFIG_RTC_DS3231 1 455 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 456 457 /* 458 * eSPI - Enhanced SPI 459 */ 460 #define CONFIG_SF_DEFAULT_SPEED 10000000 461 #define CONFIG_SF_DEFAULT_MODE 0 462 463 /* 464 * General PCI 465 * Memory space is mapped 1-1, but I/O space must start from 0. 466 */ 467 468 #ifdef CONFIG_PCI 469 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 470 #ifdef CONFIG_PCIE1 471 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 472 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 473 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 474 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 475 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 476 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 478 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 479 #endif 480 481 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 482 #ifdef CONFIG_PCIE2 483 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 484 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 485 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 486 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 487 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 488 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 489 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 490 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 491 #endif 492 493 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 494 #ifdef CONFIG_PCIE3 495 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 496 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 497 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 498 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 499 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 500 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 501 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 502 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 503 #endif 504 505 /* controller 4, Base address 203000 */ 506 #ifdef CONFIG_PCIE4 507 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 508 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 509 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 510 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 511 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 512 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 513 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 514 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 515 #endif 516 517 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 518 #define CONFIG_DOS_PARTITION 519 #endif /* CONFIG_PCI */ 520 521 /* SATA */ 522 #define CONFIG_FSL_SATA_V2 523 #ifdef CONFIG_FSL_SATA_V2 524 #define CONFIG_LIBATA 525 #define CONFIG_FSL_SATA 526 527 #define CONFIG_SYS_SATA_MAX_DEVICE 2 528 #define CONFIG_SATA1 529 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 530 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 531 #define CONFIG_SATA2 532 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 533 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 534 535 #define CONFIG_LBA48 536 #define CONFIG_CMD_SATA 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 /* 541 * USB 542 */ 543 #define CONFIG_HAS_FSL_DR_USB 544 545 #ifdef CONFIG_HAS_FSL_DR_USB 546 #define CONFIG_USB_EHCI 547 548 #ifdef CONFIG_USB_EHCI 549 #define CONFIG_USB_EHCI_FSL 550 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 551 #endif 552 #endif 553 554 #define CONFIG_MMC 555 556 #ifdef CONFIG_MMC 557 #define CONFIG_FSL_ESDHC 558 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 559 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 560 #define CONFIG_GENERIC_MMC 561 #define CONFIG_DOS_PARTITION 562 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 563 #endif 564 565 /* Qman/Bman */ 566 #ifndef CONFIG_NOBQFMAN 567 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 568 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 569 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 570 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 571 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 572 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 573 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 574 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 575 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 576 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 577 CONFIG_SYS_BMAN_CENA_SIZE) 578 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 579 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 580 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 581 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 582 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 583 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 584 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 585 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 586 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 587 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 588 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 589 CONFIG_SYS_QMAN_CENA_SIZE) 590 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 591 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 592 593 #define CONFIG_SYS_DPAA_FMAN 594 #define CONFIG_SYS_DPAA_PME 595 596 #define CONFIG_QE 597 #define CONFIG_U_QE 598 /* Default address of microcode for the Linux Fman driver */ 599 #if defined(CONFIG_SPIFLASH) 600 /* 601 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 602 * env, so we got 0x110000. 603 */ 604 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 605 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 606 #elif defined(CONFIG_SDCARD) 607 /* 608 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 609 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 610 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 611 */ 612 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 613 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 614 #elif defined(CONFIG_NAND) 615 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 616 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 617 #else 618 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 619 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 620 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 621 #endif 622 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 623 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 624 #endif /* CONFIG_NOBQFMAN */ 625 626 #ifdef CONFIG_SYS_DPAA_FMAN 627 #define CONFIG_FMAN_ENET 628 #define CONFIG_PHYLIB_10G 629 #define CONFIG_PHY_VITESSE 630 #define CONFIG_PHY_REALTEK 631 #define CONFIG_PHY_TERANETICS 632 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 633 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 634 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 635 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 636 #endif 637 638 #ifdef CONFIG_FMAN_ENET 639 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 640 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 641 642 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 643 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 644 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 645 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 646 647 #define CONFIG_MII /* MII PHY management */ 648 #define CONFIG_ETHPRIME "FM1@DTSEC1" 649 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 650 #endif 651 652 /* Enable VSC9953 L2 Switch driver */ 653 #define CONFIG_VSC9953 654 #define CONFIG_CMD_ETHSW 655 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 656 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 657 658 /* 659 * Dynamic MTD Partition support with mtdparts 660 */ 661 #ifndef CONFIG_SYS_NO_FLASH 662 #define CONFIG_MTD_DEVICE 663 #define CONFIG_MTD_PARTITIONS 664 #define CONFIG_CMD_MTDPARTS 665 #define CONFIG_FLASH_CFI_MTD 666 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 667 "spi0=spife110000.0" 668 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 669 "128k(dtb),96m(fs),-(user);"\ 670 "fff800000.flash:2m(uboot),9m(kernel),"\ 671 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 672 "2m(uboot),9m(kernel),128k(dtb),-(user)" 673 #endif 674 675 /* 676 * Environment 677 */ 678 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 679 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 680 681 /* 682 * Command line configuration. 683 */ 684 #define CONFIG_CMD_DATE 685 #define CONFIG_CMD_EEPROM 686 #define CONFIG_CMD_ERRATA 687 #define CONFIG_CMD_IRQ 688 #define CONFIG_CMD_REGINFO 689 690 #ifdef CONFIG_PCI 691 #define CONFIG_CMD_PCI 692 #endif 693 694 /* Hash command with SHA acceleration supported in hardware */ 695 #ifdef CONFIG_FSL_CAAM 696 #define CONFIG_CMD_HASH 697 #define CONFIG_SHA_HW_ACCEL 698 #endif 699 700 /* 701 * Miscellaneous configurable options 702 */ 703 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 704 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 705 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 706 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 707 #ifdef CONFIG_CMD_KGDB 708 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 709 #else 710 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 711 #endif 712 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 713 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 714 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 715 716 /* 717 * For booting Linux, the board info and command line data 718 * have to be in the first 64 MB of memory, since this is 719 * the maximum mapped by the Linux kernel during initialization. 720 */ 721 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 722 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 723 724 #ifdef CONFIG_CMD_KGDB 725 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 726 #endif 727 728 /* 729 * Environment Configuration 730 */ 731 #define CONFIG_ROOTPATH "/opt/nfsroot" 732 #define CONFIG_BOOTFILE "uImage" 733 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 734 735 /* default location for tftp and bootm */ 736 #define CONFIG_LOADADDR 1000000 737 738 739 #define CONFIG_BAUDRATE 115200 740 741 #define __USB_PHY_TYPE utmi 742 743 #define CONFIG_EXTRA_ENV_SETTINGS \ 744 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 745 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 746 "netdev=eth0\0" \ 747 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 748 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 749 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 750 "tftpflash=tftpboot $loadaddr $uboot && " \ 751 "protect off $ubootaddr +$filesize && " \ 752 "erase $ubootaddr +$filesize && " \ 753 "cp.b $loadaddr $ubootaddr $filesize && " \ 754 "protect on $ubootaddr +$filesize && " \ 755 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 756 "consoledev=ttyS0\0" \ 757 "ramdiskaddr=2000000\0" \ 758 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 759 "fdtaddr=1e00000\0" \ 760 "fdtfile=t1040qds/t1040qds.dtb\0" \ 761 "bdev=sda3\0" 762 763 #define CONFIG_LINUX \ 764 "setenv bootargs root=/dev/ram rw " \ 765 "console=$consoledev,$baudrate $othbootargs;" \ 766 "setenv ramdiskaddr 0x02000000;" \ 767 "setenv fdtaddr 0x00c00000;" \ 768 "setenv loadaddr 0x1000000;" \ 769 "bootm $loadaddr $ramdiskaddr $fdtaddr" 770 771 #define CONFIG_HDBOOT \ 772 "setenv bootargs root=/dev/$bdev rw " \ 773 "console=$consoledev,$baudrate $othbootargs;" \ 774 "tftp $loadaddr $bootfile;" \ 775 "tftp $fdtaddr $fdtfile;" \ 776 "bootm $loadaddr - $fdtaddr" 777 778 #define CONFIG_NFSBOOTCOMMAND \ 779 "setenv bootargs root=/dev/nfs rw " \ 780 "nfsroot=$serverip:$rootpath " \ 781 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "tftp $loadaddr $bootfile;" \ 784 "tftp $fdtaddr $fdtfile;" \ 785 "bootm $loadaddr - $fdtaddr" 786 787 #define CONFIG_RAMBOOTCOMMAND \ 788 "setenv bootargs root=/dev/ram rw " \ 789 "console=$consoledev,$baudrate $othbootargs;" \ 790 "tftp $ramdiskaddr $ramdiskfile;" \ 791 "tftp $loadaddr $bootfile;" \ 792 "tftp $fdtaddr $fdtfile;" \ 793 "bootm $loadaddr $ramdiskaddr $fdtaddr" 794 795 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 796 797 #include <asm/fsl_secure_boot.h> 798 799 #endif /* __CONFIG_H */ 800