1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 39 #define CONFIG_E500 /* BOOKE e500 family */ 40 #define CONFIG_E500MC /* BOOKE e500mc family */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 #ifndef CONFIG_SYS_TEXT_BASE 46 #define CONFIG_SYS_TEXT_BASE 0xeff80000 47 #endif 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_FSL_IFC /* Enable IFC Support */ 56 #define CONFIG_PCI /* Enable PCI/PCIE */ 57 #define CONFIG_PCI_INDIRECT_BRIDGE 58 #define CONFIG_PCIE1 /* PCIE controler 1 */ 59 #define CONFIG_PCIE2 /* PCIE controler 2 */ 60 #define CONFIG_PCIE3 /* PCIE controler 3 */ 61 #define CONFIG_PCIE4 /* PCIE controler 4 */ 62 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_FSL_LAW /* Use common FSL init code */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #define CONFIG_ENV_IS_NOWHERE 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #ifndef CONFIG_SYS_NO_FLASH 79 #if defined(CONFIG_SPIFLASH) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #elif defined(CONFIG_SDCARD) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1105) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #else 101 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #endif 106 #else /* CONFIG_SYS_NO_FLASH */ 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #endif 110 111 #ifndef __ASSEMBLY__ 112 unsigned long get_board_sys_clk(void); 113 unsigned long get_board_ddr_clk(void); 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #define CONFIG_ENABLE_36BIT_PHYS 133 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 142 /* 143 * Config the L3 Cache as L3 SRAM 144 */ 145 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 147 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 170 #define CONFIG_DDR_SPD 171 #define CONFIG_FSL_DDR3 172 #define CONFIG_FSL_DDR_INTERACTIVE 173 174 #define CONFIG_SYS_SPD_BUS_NUM 0 175 #define SPD_EEPROM_ADDRESS 0x51 176 177 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 178 179 /* 180 * IFC Definitions 181 */ 182 #define CONFIG_SYS_FLASH_BASE 0xe0000000 183 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 184 185 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 186 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 187 + 0x8000000) | \ 188 CSPR_PORT_SIZE_16 | \ 189 CSPR_MSEL_NOR | \ 190 CSPR_V) 191 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 192 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 193 CSPR_PORT_SIZE_16 | \ 194 CSPR_MSEL_NOR | \ 195 CSPR_V) 196 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 197 /* NOR Flash Timing Params */ 198 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 199 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 200 FTIM0_NOR_TEADC(0x5) | \ 201 FTIM0_NOR_TEAHC(0x5)) 202 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 203 FTIM1_NOR_TRAD_NOR(0x1A) |\ 204 FTIM1_NOR_TSEQRAD_NOR(0x13)) 205 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 206 FTIM2_NOR_TCH(0x4) | \ 207 FTIM2_NOR_TWPH(0x0E) | \ 208 FTIM2_NOR_TWP(0x1c)) 209 #define CONFIG_SYS_NOR_FTIM3 0x0 210 211 #define CONFIG_SYS_FLASH_QUIET_TEST 212 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 221 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 222 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 223 #define QIXIS_BASE 0xffdf0000 224 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 225 #define QIXIS_LBMAP_SWITCH 0x06 226 #define QIXIS_LBMAP_MASK 0x0f 227 #define QIXIS_LBMAP_SHIFT 0 228 #define QIXIS_LBMAP_DFLTBANK 0x00 229 #define QIXIS_LBMAP_ALTBANK 0x04 230 #define QIXIS_RST_CTL_RESET 0x31 231 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 232 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 233 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 234 235 #define CONFIG_SYS_CSPR3_EXT (0xf) 236 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 237 | CSPR_PORT_SIZE_8 \ 238 | CSPR_MSEL_GPCM \ 239 | CSPR_V) 240 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 241 #define CONFIG_SYS_CSOR3 0x0 242 /* QIXIS Timing parameters for IFC CS3 */ 243 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 244 FTIM0_GPCM_TEADC(0x0e) | \ 245 FTIM0_GPCM_TEAHC(0x0e)) 246 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 247 FTIM1_GPCM_TRAD(0x3f)) 248 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 249 FTIM2_GPCM_TCH(0x0) | \ 250 FTIM2_GPCM_TWP(0x1f)) 251 #define CONFIG_SYS_CS3_FTIM3 0x0 252 253 #define CONFIG_NAND_FSL_IFC 254 #define CONFIG_SYS_NAND_BASE 0xff800000 255 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 256 257 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 258 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 259 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 260 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 261 | CSPR_V) 262 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 263 264 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 265 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 266 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 267 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 268 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 269 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 270 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 271 272 #define CONFIG_SYS_NAND_ONFI_DETECTION 273 274 /* ONFI NAND Flash mode0 Timing Params */ 275 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 276 FTIM0_NAND_TWP(0x18) | \ 277 FTIM0_NAND_TWCHT(0x07) | \ 278 FTIM0_NAND_TWH(0x0a)) 279 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 280 FTIM1_NAND_TWBE(0x39) | \ 281 FTIM1_NAND_TRR(0x0e) | \ 282 FTIM1_NAND_TRP(0x18)) 283 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 284 FTIM2_NAND_TREH(0x0a) | \ 285 FTIM2_NAND_TWHRE(0x1e)) 286 #define CONFIG_SYS_NAND_FTIM3 0x0 287 288 #define CONFIG_SYS_NAND_DDR_LAW 11 289 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 290 #define CONFIG_SYS_MAX_NAND_DEVICE 1 291 #define CONFIG_MTD_NAND_VERIFY_WRITE 292 #define CONFIG_CMD_NAND 293 294 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 295 296 #if defined(CONFIG_NAND) 297 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 298 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 299 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 300 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 301 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 302 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 303 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 304 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 305 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 306 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 307 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 314 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 315 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #else 322 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 323 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 324 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 331 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 332 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 339 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 340 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 341 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 342 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 343 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 344 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 345 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 346 #endif 347 348 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 349 350 #if defined(CONFIG_RAMBOOT_PBL) 351 #define CONFIG_SYS_RAMBOOT 352 #endif 353 354 #define CONFIG_BOARD_EARLY_INIT_R 355 #define CONFIG_MISC_INIT_R 356 357 #define CONFIG_HWCONFIG 358 359 /* define to use L1 as initial stack */ 360 #define CONFIG_L1_INIT_RAM 361 #define CONFIG_SYS_INIT_RAM_LOCK 362 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 364 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 365 /* The assembler doesn't like typecast */ 366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 367 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 368 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 369 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 370 371 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 372 GENERATED_GBL_DATA_SIZE) 373 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 374 375 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 376 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 377 378 /* Serial Port - controlled on board with jumper J8 379 * open - index 2 380 * shorted - index 1 381 */ 382 #define CONFIG_CONS_INDEX 1 383 #define CONFIG_SYS_NS16550 384 #define CONFIG_SYS_NS16550_SERIAL 385 #define CONFIG_SYS_NS16550_REG_SIZE 1 386 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 387 388 #define CONFIG_SYS_BAUDRATE_TABLE \ 389 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 390 391 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 392 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 393 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 394 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 395 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 396 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 397 398 /* Use the HUSH parser */ 399 #define CONFIG_SYS_HUSH_PARSER 400 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 401 402 /* pass open firmware flat tree */ 403 #define CONFIG_OF_LIBFDT 404 #define CONFIG_OF_BOARD_SETUP 405 #define CONFIG_OF_STDOUT_VIA_ALIAS 406 407 /* new uImage format support */ 408 #define CONFIG_FIT 409 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 410 411 /* I2C */ 412 #define CONFIG_SYS_I2C 413 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 414 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 415 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 417 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 419 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 420 421 #define I2C_MUX_PCA_ADDR 0x77 422 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 423 424 425 /* I2C bus multiplexer */ 426 #define I2C_MUX_CH_DEFAULT 0x8 427 428 /* 429 * RTC configuration 430 */ 431 #define RTC 432 #define CONFIG_RTC_DS3231 1 433 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 434 435 /* 436 * eSPI - Enhanced SPI 437 */ 438 #define CONFIG_FSL_ESPI 439 #define CONFIG_SPI_FLASH 440 #define CONFIG_SPI_FLASH_STMICRO 441 #define CONFIG_SPI_FLASH_SST 442 #define CONFIG_SPI_FLASH_EON 443 #define CONFIG_CMD_SF 444 #define CONFIG_SF_DEFAULT_SPEED 10000000 445 #define CONFIG_SF_DEFAULT_MODE 0 446 447 /* 448 * General PCI 449 * Memory space is mapped 1-1, but I/O space must start from 0. 450 */ 451 452 #ifdef CONFIG_PCI 453 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 454 #ifdef CONFIG_PCIE1 455 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 456 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 457 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 458 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 459 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 460 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 461 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 462 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 463 #endif 464 465 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 466 #ifdef CONFIG_PCIE2 467 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 468 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 469 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 470 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 471 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 472 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 473 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 474 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 475 #endif 476 477 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 478 #ifdef CONFIG_PCIE3 479 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 480 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 482 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 483 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 484 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 485 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 486 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 487 #endif 488 489 /* controller 4, Base address 203000 */ 490 #ifdef CONFIG_PCIE4 491 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 492 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 493 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 494 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 495 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 496 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 497 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 498 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 499 #endif 500 501 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 502 #define CONFIG_E1000 503 504 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 505 #define CONFIG_DOS_PARTITION 506 #endif /* CONFIG_PCI */ 507 508 /* SATA */ 509 #define CONFIG_FSL_SATA_V2 510 #ifdef CONFIG_FSL_SATA_V2 511 #define CONFIG_LIBATA 512 #define CONFIG_FSL_SATA 513 514 #define CONFIG_SYS_SATA_MAX_DEVICE 2 515 #define CONFIG_SATA1 516 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 517 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 518 #define CONFIG_SATA2 519 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 520 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 521 522 #define CONFIG_LBA48 523 #define CONFIG_CMD_SATA 524 #define CONFIG_DOS_PARTITION 525 #define CONFIG_CMD_EXT2 526 #endif 527 528 /* 529 * USB 530 */ 531 #define CONFIG_HAS_FSL_DR_USB 532 533 #ifdef CONFIG_HAS_FSL_DR_USB 534 #define CONFIG_USB_EHCI 535 536 #ifdef CONFIG_USB_EHCI 537 #define CONFIG_CMD_USB 538 #define CONFIG_USB_STORAGE 539 #define CONFIG_USB_EHCI_FSL 540 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 541 #define CONFIG_CMD_EXT2 542 #endif 543 #endif 544 545 #define CONFIG_MMC 546 547 #ifdef CONFIG_MMC 548 #define CONFIG_FSL_ESDHC 549 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 550 #define CONFIG_CMD_MMC 551 #define CONFIG_GENERIC_MMC 552 #define CONFIG_CMD_EXT2 553 #define CONFIG_CMD_FAT 554 #define CONFIG_DOS_PARTITION 555 #endif 556 557 /* Qman/Bman */ 558 #ifndef CONFIG_NOBQFMAN 559 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 560 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 561 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 562 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 563 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 564 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 565 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 566 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 567 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 568 569 #define CONFIG_SYS_DPAA_FMAN 570 #define CONFIG_SYS_DPAA_PME 571 572 /* Default address of microcode for the Linux Fman driver */ 573 #if defined(CONFIG_SPIFLASH) 574 /* 575 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 576 * env, so we got 0x110000. 577 */ 578 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 579 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 580 #elif defined(CONFIG_SDCARD) 581 /* 582 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 583 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 584 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 585 */ 586 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 587 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 588 #elif defined(CONFIG_NAND) 589 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 590 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 591 #else 592 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 593 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 594 #endif 595 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 596 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 597 #endif /* CONFIG_NOBQFMAN */ 598 599 #ifdef CONFIG_SYS_DPAA_FMAN 600 #define CONFIG_FMAN_ENET 601 #define CONFIG_PHYLIB_10G 602 #define CONFIG_PHY_VITESSE 603 #define CONFIG_PHY_REALTEK 604 #define CONFIG_PHY_TERANETICS 605 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 606 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 607 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 608 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 609 #endif 610 611 #ifdef CONFIG_FMAN_ENET 612 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 613 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 614 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 615 616 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 617 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 618 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 619 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 620 621 #define CONFIG_MII /* MII PHY management */ 622 #define CONFIG_ETHPRIME "FM1@DTSEC1" 623 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 624 #endif 625 626 /* 627 * Environment 628 */ 629 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 630 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 631 632 /* 633 * Command line configuration. 634 */ 635 #include <config_cmd_default.h> 636 637 #define CONFIG_CMD_DATE 638 #define CONFIG_CMD_DHCP 639 #define CONFIG_CMD_EEPROM 640 #define CONFIG_CMD_ELF 641 #define CONFIG_CMD_ERRATA 642 #define CONFIG_CMD_GREPENV 643 #define CONFIG_CMD_IRQ 644 #define CONFIG_CMD_I2C 645 #define CONFIG_CMD_MII 646 #define CONFIG_CMD_PING 647 #define CONFIG_CMD_REGINFO 648 #define CONFIG_CMD_SETEXPR 649 650 #ifdef CONFIG_PCI 651 #define CONFIG_CMD_PCI 652 #define CONFIG_CMD_NET 653 #endif 654 655 /* 656 * Miscellaneous configurable options 657 */ 658 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 659 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 660 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 661 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 662 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 663 #ifdef CONFIG_CMD_KGDB 664 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 665 #else 666 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 667 #endif 668 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 669 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 670 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 671 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 672 673 /* 674 * For booting Linux, the board info and command line data 675 * have to be in the first 64 MB of memory, since this is 676 * the maximum mapped by the Linux kernel during initialization. 677 */ 678 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 679 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 680 681 #ifdef CONFIG_CMD_KGDB 682 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 683 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 684 #endif 685 686 /* 687 * Environment Configuration 688 */ 689 #define CONFIG_ROOTPATH "/opt/nfsroot" 690 #define CONFIG_BOOTFILE "uImage" 691 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 692 693 /* default location for tftp and bootm */ 694 #define CONFIG_LOADADDR 1000000 695 696 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 697 698 #define CONFIG_BAUDRATE 115200 699 700 #define __USB_PHY_TYPE utmi 701 702 #define CONFIG_EXTRA_ENV_SETTINGS \ 703 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 704 "bank_intlv=cs0_cs1;" \ 705 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 706 "netdev=eth0\0" \ 707 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 708 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 709 "tftpflash=tftpboot $loadaddr $uboot && " \ 710 "protect off $ubootaddr +$filesize && " \ 711 "erase $ubootaddr +$filesize && " \ 712 "cp.b $loadaddr $ubootaddr $filesize && " \ 713 "protect on $ubootaddr +$filesize && " \ 714 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 715 "consoledev=ttyS0\0" \ 716 "ramdiskaddr=2000000\0" \ 717 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 718 "fdtaddr=c00000\0" \ 719 "fdtfile=t1040qds/t1040qds.dtb\0" \ 720 "bdev=sda3\0" \ 721 "c=ffe\0" 722 723 #define CONFIG_LINUX \ 724 "setenv bootargs root=/dev/ram rw " \ 725 "console=$consoledev,$baudrate $othbootargs;" \ 726 "setenv ramdiskaddr 0x02000000;" \ 727 "setenv fdtaddr 0x00c00000;" \ 728 "setenv loadaddr 0x1000000;" \ 729 "bootm $loadaddr $ramdiskaddr $fdtaddr" 730 731 #define CONFIG_HDBOOT \ 732 "setenv bootargs root=/dev/$bdev rw " \ 733 "console=$consoledev,$baudrate $othbootargs;" \ 734 "tftp $loadaddr $bootfile;" \ 735 "tftp $fdtaddr $fdtfile;" \ 736 "bootm $loadaddr - $fdtaddr" 737 738 #define CONFIG_NFSBOOTCOMMAND \ 739 "setenv bootargs root=/dev/nfs rw " \ 740 "nfsroot=$serverip:$rootpath " \ 741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr - $fdtaddr" 746 747 #define CONFIG_RAMBOOTCOMMAND \ 748 "setenv bootargs root=/dev/ram rw " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "tftp $ramdiskaddr $ramdiskfile;" \ 751 "tftp $loadaddr $bootfile;" \ 752 "tftp $fdtaddr $fdtfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 756 757 #ifdef CONFIG_SECURE_BOOT 758 #include <asm/fsl_secure_boot.h> 759 #endif 760 761 #endif /* __CONFIG_H */ 762