1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 RDB board configuration file 8 */ 9 10 #ifndef __T1024RDB_H 11 #define __T1024RDB_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 /* support deep sleep */ 28 #ifdef CONFIG_ARCH_T1024 29 #define CONFIG_DEEP_SLEEP 30 #endif 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 #ifdef CONFIG_SPL_BUILD 41 #define CONFIG_SPL_SKIP_RELOCATE 42 #define CONFIG_SPL_COMMON_INIT_DDR 43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 44 #endif 45 46 #ifdef CONFIG_NAND 47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 52 #if defined(CONFIG_TARGET_T1024RDB) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 54 #elif defined(CONFIG_TARGET_T1023RDB) 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 56 #endif 57 #define CONFIG_SPL_NAND_BOOT 58 #endif 59 60 #ifdef CONFIG_SPIFLASH 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #if defined(CONFIG_TARGET_T1024RDB) 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 73 #elif defined(CONFIG_TARGET_T1023RDB) 74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 75 #endif 76 #define CONFIG_SPL_SPI_BOOT 77 #endif 78 79 #ifdef CONFIG_SDCARD 80 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 81 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #if defined(CONFIG_TARGET_T1024RDB) 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 91 #elif defined(CONFIG_TARGET_T1023RDB) 92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 93 #endif 94 #define CONFIG_SPL_MMC_BOOT 95 #endif 96 97 #endif /* CONFIG_RAMBOOT_PBL */ 98 99 #ifndef CONFIG_RESET_VECTOR_ADDRESS 100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 101 #endif 102 103 #ifdef CONFIG_MTD_NOR_FLASH 104 #define CONFIG_FLASH_CFI_DRIVER 105 #define CONFIG_SYS_FLASH_CFI 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 107 #endif 108 109 /* PCIe Boot - Master */ 110 #define CONFIG_SRIO_PCIE_BOOT_MASTER 111 /* 112 * for slave u-boot IMAGE instored in master memory space, 113 * PHYS must be aligned based on the SIZE 114 */ 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 117 #ifdef CONFIG_PHYS_64BIT 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 120 #else 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 123 #endif 124 /* 125 * for slave UCODE and ENV instored in master memory space, 126 * PHYS must be aligned based on the SIZE 127 */ 128 #ifdef CONFIG_PHYS_64BIT 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 131 #else 132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 134 #endif 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 136 /* slave core release by master*/ 137 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 138 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 139 140 /* PCIe Boot - Slave */ 141 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 142 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 144 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 145 /* Set 1M boot space for PCIe boot */ 146 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 148 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 149 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 150 #endif 151 152 #if defined(CONFIG_SPIFLASH) 153 #define CONFIG_ENV_SPI_BUS 0 154 #define CONFIG_ENV_SPI_CS 0 155 #define CONFIG_ENV_SPI_MAX_HZ 10000000 156 #define CONFIG_ENV_SPI_MODE 0 157 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 158 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 159 #if defined(CONFIG_TARGET_T1024RDB) 160 #define CONFIG_ENV_SECT_SIZE 0x10000 161 #elif defined(CONFIG_TARGET_T1023RDB) 162 #define CONFIG_ENV_SECT_SIZE 0x40000 163 #endif 164 #elif defined(CONFIG_SDCARD) 165 #define CONFIG_SYS_MMC_ENV_DEV 0 166 #define CONFIG_ENV_SIZE 0x2000 167 #define CONFIG_ENV_OFFSET (512 * 0x800) 168 #elif defined(CONFIG_NAND) 169 #define CONFIG_ENV_SIZE 0x2000 170 #if defined(CONFIG_TARGET_T1024RDB) 171 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 172 #elif defined(CONFIG_TARGET_T1023RDB) 173 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 174 #endif 175 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 176 #define CONFIG_ENV_ADDR 0xffe20000 177 #define CONFIG_ENV_SIZE 0x2000 178 #elif defined(CONFIG_ENV_IS_NOWHERE) 179 #define CONFIG_ENV_SIZE 0x2000 180 #else 181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 182 #define CONFIG_ENV_SIZE 0x2000 183 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 184 #endif 185 186 #ifndef __ASSEMBLY__ 187 unsigned long get_board_sys_clk(void); 188 unsigned long get_board_ddr_clk(void); 189 #endif 190 191 #define CONFIG_SYS_CLK_FREQ 100000000 192 #define CONFIG_DDR_CLK_FREQ 100000000 193 194 /* 195 * These can be toggled for performance analysis, otherwise use default. 196 */ 197 #define CONFIG_SYS_CACHE_STASHING 198 #define CONFIG_BACKSIDE_L2_CACHE 199 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 200 #define CONFIG_BTB /* toggle branch predition */ 201 #define CONFIG_DDR_ECC 202 #ifdef CONFIG_DDR_ECC 203 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 204 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 205 #endif 206 207 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 208 #define CONFIG_SYS_MEMTEST_END 0x00400000 209 210 /* 211 * Config the L3 Cache as L3 SRAM 212 */ 213 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 214 #define CONFIG_SYS_L3_SIZE (256 << 10) 215 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 216 #ifdef CONFIG_RAMBOOT_PBL 217 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 218 #endif 219 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 220 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 221 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 222 223 #ifdef CONFIG_PHYS_64BIT 224 #define CONFIG_SYS_DCSRBAR 0xf0000000 225 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 226 #endif 227 228 /* EEPROM */ 229 #define CONFIG_ID_EEPROM 230 #define CONFIG_SYS_I2C_EEPROM_NXID 231 #define CONFIG_SYS_EEPROM_BUS_NUM 0 232 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 233 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 236 237 /* 238 * DDR Setup 239 */ 240 #define CONFIG_VERY_BIG_RAM 241 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 242 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 243 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 244 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 245 #define CONFIG_FSL_DDR_INTERACTIVE 246 #if defined(CONFIG_TARGET_T1024RDB) 247 #define CONFIG_DDR_SPD 248 #define CONFIG_SYS_SPD_BUS_NUM 0 249 #define SPD_EEPROM_ADDRESS 0x51 250 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 251 #elif defined(CONFIG_TARGET_T1023RDB) 252 #define CONFIG_SYS_DDR_RAW_TIMING 253 #define CONFIG_SYS_SDRAM_SIZE 2048 254 #endif 255 256 /* 257 * IFC Definitions 258 */ 259 #define CONFIG_SYS_FLASH_BASE 0xe8000000 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 262 #else 263 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 264 #endif 265 266 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 267 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 268 CSPR_PORT_SIZE_16 | \ 269 CSPR_MSEL_NOR | \ 270 CSPR_V) 271 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 272 273 /* NOR Flash Timing Params */ 274 #if defined(CONFIG_TARGET_T1024RDB) 275 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 276 #elif defined(CONFIG_TARGET_T1023RDB) 277 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 278 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 279 #endif 280 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 281 FTIM0_NOR_TEADC(0x5) | \ 282 FTIM0_NOR_TEAHC(0x5)) 283 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 284 FTIM1_NOR_TRAD_NOR(0x1A) |\ 285 FTIM1_NOR_TSEQRAD_NOR(0x13)) 286 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 287 FTIM2_NOR_TCH(0x4) | \ 288 FTIM2_NOR_TWPH(0x0E) | \ 289 FTIM2_NOR_TWP(0x1c)) 290 #define CONFIG_SYS_NOR_FTIM3 0x0 291 292 #define CONFIG_SYS_FLASH_QUIET_TEST 293 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 294 295 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 296 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 297 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 298 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 299 300 #define CONFIG_SYS_FLASH_EMPTY_INFO 301 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 302 303 #ifdef CONFIG_TARGET_T1024RDB 304 /* CPLD on IFC */ 305 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 306 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 307 #define CONFIG_SYS_CSPR2_EXT (0xf) 308 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 309 | CSPR_PORT_SIZE_8 \ 310 | CSPR_MSEL_GPCM \ 311 | CSPR_V) 312 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 313 #define CONFIG_SYS_CSOR2 0x0 314 315 /* CPLD Timing parameters for IFC CS2 */ 316 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 317 FTIM0_GPCM_TEADC(0x0e) | \ 318 FTIM0_GPCM_TEAHC(0x0e)) 319 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 320 FTIM1_GPCM_TRAD(0x1f)) 321 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 322 FTIM2_GPCM_TCH(0x8) | \ 323 FTIM2_GPCM_TWP(0x1f)) 324 #define CONFIG_SYS_CS2_FTIM3 0x0 325 #endif 326 327 /* NAND Flash on IFC */ 328 #define CONFIG_NAND_FSL_IFC 329 #define CONFIG_SYS_NAND_BASE 0xff800000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 332 #else 333 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 334 #endif 335 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 336 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 337 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 338 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 339 | CSPR_V) 340 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 341 342 #if defined(CONFIG_TARGET_T1024RDB) 343 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 344 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 345 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 346 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 347 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 348 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 349 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 350 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 351 #elif defined(CONFIG_TARGET_T1023RDB) 352 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 353 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 354 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 355 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 356 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 357 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 358 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 359 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 360 #endif 361 362 #define CONFIG_SYS_NAND_ONFI_DETECTION 363 /* ONFI NAND Flash mode0 Timing Params */ 364 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 365 FTIM0_NAND_TWP(0x18) | \ 366 FTIM0_NAND_TWCHT(0x07) | \ 367 FTIM0_NAND_TWH(0x0a)) 368 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 369 FTIM1_NAND_TWBE(0x39) | \ 370 FTIM1_NAND_TRR(0x0e) | \ 371 FTIM1_NAND_TRP(0x18)) 372 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 373 FTIM2_NAND_TREH(0x0a) | \ 374 FTIM2_NAND_TWHRE(0x1e)) 375 #define CONFIG_SYS_NAND_FTIM3 0x0 376 377 #define CONFIG_SYS_NAND_DDR_LAW 11 378 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 379 #define CONFIG_SYS_MAX_NAND_DEVICE 1 380 381 #if defined(CONFIG_NAND) 382 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 383 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 384 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 385 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 386 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 387 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 388 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 389 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 390 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 391 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 392 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 398 #else 399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 415 #endif 416 417 #ifdef CONFIG_SPL_BUILD 418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 419 #else 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 421 #endif 422 423 #if defined(CONFIG_RAMBOOT_PBL) 424 #define CONFIG_SYS_RAMBOOT 425 #endif 426 427 #define CONFIG_HWCONFIG 428 429 /* define to use L1 as initial stack */ 430 #define CONFIG_L1_INIT_RAM 431 #define CONFIG_SYS_INIT_RAM_LOCK 432 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 436 /* The assembler doesn't like typecast */ 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 438 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 439 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 440 #else 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 444 #endif 445 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 446 447 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 448 GENERATED_GBL_DATA_SIZE) 449 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 450 451 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 452 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 453 454 /* Serial Port */ 455 #define CONFIG_SYS_NS16550_SERIAL 456 #define CONFIG_SYS_NS16550_REG_SIZE 1 457 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 458 459 #define CONFIG_SYS_BAUDRATE_TABLE \ 460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 461 462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 464 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 465 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 466 467 /* Video */ 468 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 469 #ifdef CONFIG_FSL_DIU_FB 470 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 471 #define CONFIG_VIDEO_LOGO 472 #define CONFIG_VIDEO_BMP_LOGO 473 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 474 /* 475 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 476 * disable empty flash sector detection, which is I/O-intensive. 477 */ 478 #undef CONFIG_SYS_FLASH_EMPTY_INFO 479 #endif 480 481 /* I2C */ 482 #define CONFIG_SYS_I2C 483 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 484 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 485 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 486 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 487 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 488 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 489 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 490 491 #define I2C_PCA6408_BUS_NUM 1 492 #define I2C_PCA6408_ADDR 0x20 493 494 /* I2C bus multiplexer */ 495 #define I2C_MUX_CH_DEFAULT 0x8 496 497 /* 498 * RTC configuration 499 */ 500 #define RTC 501 #define CONFIG_RTC_DS1337 1 502 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 503 504 /* 505 * eSPI - Enhanced SPI 506 */ 507 #define CONFIG_SPI_FLASH_BAR 508 #define CONFIG_SF_DEFAULT_SPEED 10000000 509 #define CONFIG_SF_DEFAULT_MODE 0 510 511 /* 512 * General PCIe 513 * Memory space is mapped 1-1, but I/O space must start from 0. 514 */ 515 #define CONFIG_PCIE1 /* PCIE controller 1 */ 516 #define CONFIG_PCIE2 /* PCIE controller 2 */ 517 #define CONFIG_PCIE3 /* PCIE controller 3 */ 518 #ifdef CONFIG_ARCH_T1040 519 #define CONFIG_PCIE4 /* PCIE controller 4 */ 520 #endif 521 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 522 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 523 #define CONFIG_PCI_INDIRECT_BRIDGE 524 525 #ifdef CONFIG_PCI 526 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 527 #ifdef CONFIG_PCIE1 528 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 529 #ifdef CONFIG_PHYS_64BIT 530 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 531 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 532 #else 533 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 534 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 535 #endif 536 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 537 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 538 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 539 #ifdef CONFIG_PHYS_64BIT 540 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 541 #else 542 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 543 #endif 544 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 545 #endif 546 547 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 548 #ifdef CONFIG_PCIE2 549 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 550 #ifdef CONFIG_PHYS_64BIT 551 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 552 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 553 #else 554 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 555 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 556 #endif 557 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 558 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 559 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 560 #ifdef CONFIG_PHYS_64BIT 561 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 562 #else 563 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 564 #endif 565 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 566 #endif 567 568 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 569 #ifdef CONFIG_PCIE3 570 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 571 #ifdef CONFIG_PHYS_64BIT 572 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 573 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 574 #else 575 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 576 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 577 #endif 578 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 579 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 580 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 581 #ifdef CONFIG_PHYS_64BIT 582 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 583 #else 584 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 585 #endif 586 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 587 #endif 588 589 /* controller 4, Base address 203000, to be removed */ 590 #ifdef CONFIG_PCIE4 591 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 592 #ifdef CONFIG_PHYS_64BIT 593 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 594 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 595 #else 596 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 597 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 598 #endif 599 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 600 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 601 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 602 #ifdef CONFIG_PHYS_64BIT 603 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 604 #else 605 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 606 #endif 607 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 608 #endif 609 610 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 611 #endif /* CONFIG_PCI */ 612 613 /* 614 * USB 615 */ 616 #define CONFIG_HAS_FSL_DR_USB 617 618 #ifdef CONFIG_HAS_FSL_DR_USB 619 #define CONFIG_USB_EHCI_FSL 620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 621 #endif 622 623 /* 624 * SDHC 625 */ 626 #ifdef CONFIG_MMC 627 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 628 #endif 629 630 /* Qman/Bman */ 631 #ifndef CONFIG_NOBQFMAN 632 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 633 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 634 #ifdef CONFIG_PHYS_64BIT 635 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 636 #else 637 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 638 #endif 639 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 640 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 641 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 642 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 643 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 644 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 645 CONFIG_SYS_BMAN_CENA_SIZE) 646 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 647 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 648 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 649 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 650 #ifdef CONFIG_PHYS_64BIT 651 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 652 #else 653 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 654 #endif 655 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 656 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 657 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 658 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 659 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 660 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 661 CONFIG_SYS_QMAN_CENA_SIZE) 662 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 663 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 664 665 #define CONFIG_SYS_DPAA_FMAN 666 667 #ifdef CONFIG_TARGET_T1024RDB 668 #define CONFIG_QE 669 #endif 670 /* Default address of microcode for the Linux FMan driver */ 671 #if defined(CONFIG_SPIFLASH) 672 /* 673 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 674 * env, so we got 0x110000. 675 */ 676 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 677 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 678 #define CONFIG_SYS_QE_FW_ADDR 0x130000 679 #elif defined(CONFIG_SDCARD) 680 /* 681 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 682 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 683 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 684 */ 685 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 686 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 687 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 688 #elif defined(CONFIG_NAND) 689 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 690 #if defined(CONFIG_TARGET_T1024RDB) 691 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 692 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 693 #elif defined(CONFIG_TARGET_T1023RDB) 694 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 695 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 696 #endif 697 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 698 /* 699 * Slave has no ucode locally, it can fetch this from remote. When implementing 700 * in two corenet boards, slave's ucode could be stored in master's memory 701 * space, the address can be mapped from slave TLB->slave LAW-> 702 * slave SRIO or PCIE outbound window->master inbound window-> 703 * master LAW->the ucode address in master's memory space. 704 */ 705 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 706 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 707 #else 708 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 709 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 710 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 711 #endif 712 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 713 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 714 #endif /* CONFIG_NOBQFMAN */ 715 716 #ifdef CONFIG_SYS_DPAA_FMAN 717 #define CONFIG_FMAN_ENET 718 #define CONFIG_PHYLIB_10G 719 #define CONFIG_PHY_REALTEK 720 #define CONFIG_PHY_AQUANTIA 721 #if defined(CONFIG_TARGET_T1024RDB) 722 #define RGMII_PHY1_ADDR 0x2 723 #define RGMII_PHY2_ADDR 0x6 724 #define SGMII_AQR_PHY_ADDR 0x2 725 #define FM1_10GEC1_PHY_ADDR 0x1 726 #elif defined(CONFIG_TARGET_T1023RDB) 727 #define RGMII_PHY1_ADDR 0x1 728 #define SGMII_RTK_PHY_ADDR 0x3 729 #define SGMII_AQR_PHY_ADDR 0x2 730 #endif 731 #endif 732 733 #ifdef CONFIG_FMAN_ENET 734 #define CONFIG_ETHPRIME "FM1@DTSEC4" 735 #endif 736 737 /* 738 * Dynamic MTD Partition support with mtdparts 739 */ 740 #ifdef CONFIG_MTD_NOR_FLASH 741 #define CONFIG_FLASH_CFI_MTD 742 #endif 743 744 /* 745 * Environment 746 */ 747 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 748 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 749 750 /* 751 * Miscellaneous configurable options 752 */ 753 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 754 755 /* 756 * For booting Linux, the board info and command line data 757 * have to be in the first 64 MB of memory, since this is 758 * the maximum mapped by the Linux kernel during initialization. 759 */ 760 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 761 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 762 763 #ifdef CONFIG_CMD_KGDB 764 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 765 #endif 766 767 /* 768 * Environment Configuration 769 */ 770 #define CONFIG_ROOTPATH "/opt/nfsroot" 771 #define CONFIG_BOOTFILE "uImage" 772 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 773 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 774 #define __USB_PHY_TYPE utmi 775 776 #ifdef CONFIG_ARCH_T1024 777 #define CONFIG_BOARDNAME t1024rdb 778 #define BANK_INTLV cs0_cs1 779 #else 780 #define CONFIG_BOARDNAME t1023rdb 781 #define BANK_INTLV null 782 #endif 783 784 #define CONFIG_EXTRA_ENV_SETTINGS \ 785 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 786 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 787 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 788 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 789 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 790 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 791 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 792 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 793 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 794 "netdev=eth0\0" \ 795 "tftpflash=tftpboot $loadaddr $uboot && " \ 796 "protect off $ubootaddr +$filesize && " \ 797 "erase $ubootaddr +$filesize && " \ 798 "cp.b $loadaddr $ubootaddr $filesize && " \ 799 "protect on $ubootaddr +$filesize && " \ 800 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 801 "consoledev=ttyS0\0" \ 802 "ramdiskaddr=2000000\0" \ 803 "fdtaddr=1e00000\0" \ 804 "bdev=sda3\0" 805 806 #define CONFIG_LINUX \ 807 "setenv bootargs root=/dev/ram rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "setenv ramdiskaddr 0x02000000;" \ 810 "setenv fdtaddr 0x00c00000;" \ 811 "setenv loadaddr 0x1000000;" \ 812 "bootm $loadaddr $ramdiskaddr $fdtaddr" 813 814 #define CONFIG_NFSBOOTCOMMAND \ 815 "setenv bootargs root=/dev/nfs rw " \ 816 "nfsroot=$serverip:$rootpath " \ 817 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 818 "console=$consoledev,$baudrate $othbootargs;" \ 819 "tftp $loadaddr $bootfile;" \ 820 "tftp $fdtaddr $fdtfile;" \ 821 "bootm $loadaddr - $fdtaddr" 822 823 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 824 825 #include <asm/fsl_secure_boot.h> 826 827 #endif /* __T1024RDB_H */ 828