1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #define CONFIG_E500MC /* BOOKE e500mc family */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_ENV_OVERWRITE 33 34 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 35 36 /* support deep sleep */ 37 #ifdef CONFIG_PPC_T1024 38 #define CONFIG_DEEP_SLEEP 39 #endif 40 #if defined(CONFIG_DEEP_SLEEP) 41 #define CONFIG_SILENT_CONSOLE 42 #define CONFIG_BOARD_EARLY_INIT_F 43 #endif 44 45 #ifdef CONFIG_RAMBOOT_PBL 46 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x30001000 51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 52 #define CONFIG_SPL_PAD_TO 0x40000 53 #define CONFIG_SPL_MAX_SIZE 0x28000 54 #define RESET_VECTOR_OFFSET 0x27FFC 55 #define BOOT_PAGE_OFFSET 0x27000 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SPL_SKIP_RELOCATE 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #define CONFIG_SYS_NO_FLASH 61 #endif 62 63 #ifdef CONFIG_NAND 64 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 65 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 66 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 67 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 69 #if defined(CONFIG_T1024RDB) 70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 71 #elif defined(CONFIG_T1023RDB) 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 73 #endif 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #if defined(CONFIG_T1024RDB) 89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 90 #elif defined(CONFIG_T1023RDB) 91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 92 #endif 93 #define CONFIG_SPL_SPI_BOOT 94 #endif 95 96 #ifdef CONFIG_SDCARD 97 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 98 #define CONFIG_SPL_MMC_MINIMAL 99 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 100 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 101 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 102 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 103 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 104 #ifndef CONFIG_SPL_BUILD 105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 106 #endif 107 #if defined(CONFIG_T1024RDB) 108 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 109 #elif defined(CONFIG_T1023RDB) 110 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 111 #endif 112 #define CONFIG_SPL_MMC_BOOT 113 #endif 114 115 #endif /* CONFIG_RAMBOOT_PBL */ 116 117 #ifndef CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_TEXT_BASE 0xeff40000 119 #endif 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 #ifndef CONFIG_SYS_NO_FLASH 126 #define CONFIG_FLASH_CFI_DRIVER 127 #define CONFIG_SYS_FLASH_CFI 128 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 129 #endif 130 131 /* PCIe Boot - Master */ 132 #define CONFIG_SRIO_PCIE_BOOT_MASTER 133 /* 134 * for slave u-boot IMAGE instored in master memory space, 135 * PHYS must be aligned based on the SIZE 136 */ 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 142 #else 143 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 144 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 145 #endif 146 /* 147 * for slave UCODE and ENV instored in master memory space, 148 * PHYS must be aligned based on the SIZE 149 */ 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 152 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 153 #else 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 155 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 156 #endif 157 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 158 /* slave core release by master*/ 159 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 160 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 161 162 /* PCIe Boot - Slave */ 163 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 164 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 165 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 166 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 167 /* Set 1M boot space for PCIe boot */ 168 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 169 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 170 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 171 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 172 #define CONFIG_SYS_NO_FLASH 173 #endif 174 175 #if defined(CONFIG_SPIFLASH) 176 #define CONFIG_SYS_EXTRA_ENV_RELOC 177 #define CONFIG_ENV_IS_IN_SPI_FLASH 178 #define CONFIG_ENV_SPI_BUS 0 179 #define CONFIG_ENV_SPI_CS 0 180 #define CONFIG_ENV_SPI_MAX_HZ 10000000 181 #define CONFIG_ENV_SPI_MODE 0 182 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 183 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 184 #if defined(CONFIG_T1024RDB) 185 #define CONFIG_ENV_SECT_SIZE 0x10000 186 #elif defined(CONFIG_T1023RDB) 187 #define CONFIG_ENV_SECT_SIZE 0x40000 188 #endif 189 #elif defined(CONFIG_SDCARD) 190 #define CONFIG_SYS_EXTRA_ENV_RELOC 191 #define CONFIG_ENV_IS_IN_MMC 192 #define CONFIG_SYS_MMC_ENV_DEV 0 193 #define CONFIG_ENV_SIZE 0x2000 194 #define CONFIG_ENV_OFFSET (512 * 0x800) 195 #elif defined(CONFIG_NAND) 196 #define CONFIG_SYS_EXTRA_ENV_RELOC 197 #define CONFIG_ENV_IS_IN_NAND 198 #define CONFIG_ENV_SIZE 0x2000 199 #if defined(CONFIG_T1024RDB) 200 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 201 #elif defined(CONFIG_T1023RDB) 202 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 203 #endif 204 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 205 #define CONFIG_ENV_IS_IN_REMOTE 206 #define CONFIG_ENV_ADDR 0xffe20000 207 #define CONFIG_ENV_SIZE 0x2000 208 #elif defined(CONFIG_ENV_IS_NOWHERE) 209 #define CONFIG_ENV_SIZE 0x2000 210 #else 211 #define CONFIG_ENV_IS_IN_FLASH 212 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 213 #define CONFIG_ENV_SIZE 0x2000 214 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 215 #endif 216 217 #ifndef __ASSEMBLY__ 218 unsigned long get_board_sys_clk(void); 219 unsigned long get_board_ddr_clk(void); 220 #endif 221 222 #define CONFIG_SYS_CLK_FREQ 100000000 223 #define CONFIG_DDR_CLK_FREQ 100000000 224 225 /* 226 * These can be toggled for performance analysis, otherwise use default. 227 */ 228 #define CONFIG_SYS_CACHE_STASHING 229 #define CONFIG_BACKSIDE_L2_CACHE 230 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 231 #define CONFIG_BTB /* toggle branch predition */ 232 #define CONFIG_DDR_ECC 233 #ifdef CONFIG_DDR_ECC 234 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 235 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 236 #endif 237 238 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 239 #define CONFIG_SYS_MEMTEST_END 0x00400000 240 #define CONFIG_SYS_ALT_MEMTEST 241 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 242 243 /* 244 * Config the L3 Cache as L3 SRAM 245 */ 246 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 247 #define CONFIG_SYS_L3_SIZE (256 << 10) 248 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 249 #ifdef CONFIG_RAMBOOT_PBL 250 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 251 #endif 252 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 253 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 254 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 255 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 256 257 #ifdef CONFIG_PHYS_64BIT 258 #define CONFIG_SYS_DCSRBAR 0xf0000000 259 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 260 #endif 261 262 /* EEPROM */ 263 #define CONFIG_ID_EEPROM 264 #define CONFIG_SYS_I2C_EEPROM_NXID 265 #define CONFIG_SYS_EEPROM_BUS_NUM 0 266 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 267 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 268 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 270 271 /* 272 * DDR Setup 273 */ 274 #define CONFIG_VERY_BIG_RAM 275 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 276 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 277 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 278 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 279 #define CONFIG_FSL_DDR_INTERACTIVE 280 #if defined(CONFIG_T1024RDB) 281 #define CONFIG_DDR_SPD 282 #define CONFIG_SYS_FSL_DDR3 283 #define CONFIG_SYS_SPD_BUS_NUM 0 284 #define SPD_EEPROM_ADDRESS 0x51 285 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 286 #elif defined(CONFIG_T1023RDB) 287 #define CONFIG_SYS_FSL_DDR4 288 #define CONFIG_SYS_DDR_RAW_TIMING 289 #define CONFIG_SYS_SDRAM_SIZE 2048 290 #endif 291 292 /* 293 * IFC Definitions 294 */ 295 #define CONFIG_SYS_FLASH_BASE 0xe8000000 296 #ifdef CONFIG_PHYS_64BIT 297 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 298 #else 299 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 300 #endif 301 302 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 303 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 304 CSPR_PORT_SIZE_16 | \ 305 CSPR_MSEL_NOR | \ 306 CSPR_V) 307 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 308 309 /* NOR Flash Timing Params */ 310 #if defined(CONFIG_T1024RDB) 311 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 312 #elif defined(CONFIG_T1023RDB) 313 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 314 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 315 #endif 316 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 317 FTIM0_NOR_TEADC(0x5) | \ 318 FTIM0_NOR_TEAHC(0x5)) 319 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 320 FTIM1_NOR_TRAD_NOR(0x1A) |\ 321 FTIM1_NOR_TSEQRAD_NOR(0x13)) 322 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 323 FTIM2_NOR_TCH(0x4) | \ 324 FTIM2_NOR_TWPH(0x0E) | \ 325 FTIM2_NOR_TWP(0x1c)) 326 #define CONFIG_SYS_NOR_FTIM3 0x0 327 328 #define CONFIG_SYS_FLASH_QUIET_TEST 329 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 330 331 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 332 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 333 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 334 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 335 336 #define CONFIG_SYS_FLASH_EMPTY_INFO 337 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 338 339 #ifdef CONFIG_T1024RDB 340 /* CPLD on IFC */ 341 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 342 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 343 #define CONFIG_SYS_CSPR2_EXT (0xf) 344 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 345 | CSPR_PORT_SIZE_8 \ 346 | CSPR_MSEL_GPCM \ 347 | CSPR_V) 348 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 349 #define CONFIG_SYS_CSOR2 0x0 350 351 /* CPLD Timing parameters for IFC CS2 */ 352 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 353 FTIM0_GPCM_TEADC(0x0e) | \ 354 FTIM0_GPCM_TEAHC(0x0e)) 355 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 356 FTIM1_GPCM_TRAD(0x1f)) 357 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 358 FTIM2_GPCM_TCH(0x8) | \ 359 FTIM2_GPCM_TWP(0x1f)) 360 #define CONFIG_SYS_CS2_FTIM3 0x0 361 #endif 362 363 /* NAND Flash on IFC */ 364 #define CONFIG_NAND_FSL_IFC 365 #define CONFIG_SYS_NAND_BASE 0xff800000 366 #ifdef CONFIG_PHYS_64BIT 367 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 368 #else 369 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 370 #endif 371 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 372 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 373 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 374 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 375 | CSPR_V) 376 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 377 378 #if defined(CONFIG_T1024RDB) 379 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 380 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 381 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 382 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 383 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 384 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 385 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 386 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 387 #elif defined(CONFIG_T1023RDB) 388 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 389 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 390 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 391 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 392 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 393 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 394 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 395 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 396 #endif 397 398 #define CONFIG_SYS_NAND_ONFI_DETECTION 399 /* ONFI NAND Flash mode0 Timing Params */ 400 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 401 FTIM0_NAND_TWP(0x18) | \ 402 FTIM0_NAND_TWCHT(0x07) | \ 403 FTIM0_NAND_TWH(0x0a)) 404 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 405 FTIM1_NAND_TWBE(0x39) | \ 406 FTIM1_NAND_TRR(0x0e) | \ 407 FTIM1_NAND_TRP(0x18)) 408 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 409 FTIM2_NAND_TREH(0x0a) | \ 410 FTIM2_NAND_TWHRE(0x1e)) 411 #define CONFIG_SYS_NAND_FTIM3 0x0 412 413 #define CONFIG_SYS_NAND_DDR_LAW 11 414 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 415 #define CONFIG_SYS_MAX_NAND_DEVICE 1 416 #define CONFIG_CMD_NAND 417 418 #if defined(CONFIG_NAND) 419 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 420 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 421 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 422 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 423 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 424 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 425 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 426 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 427 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 428 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 429 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 430 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 431 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 432 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 433 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 434 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 435 #else 436 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 437 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 438 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 439 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 440 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 441 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 442 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 443 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 444 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 445 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 446 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 447 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 448 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 449 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 450 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 451 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 452 #endif 453 454 #ifdef CONFIG_SPL_BUILD 455 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 456 #else 457 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 458 #endif 459 460 #if defined(CONFIG_RAMBOOT_PBL) 461 #define CONFIG_SYS_RAMBOOT 462 #endif 463 464 #define CONFIG_BOARD_EARLY_INIT_R 465 #define CONFIG_MISC_INIT_R 466 467 #define CONFIG_HWCONFIG 468 469 /* define to use L1 as initial stack */ 470 #define CONFIG_L1_INIT_RAM 471 #define CONFIG_SYS_INIT_RAM_LOCK 472 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 473 #ifdef CONFIG_PHYS_64BIT 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 476 /* The assembler doesn't like typecast */ 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 478 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 479 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 480 #else 481 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 484 #endif 485 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 486 487 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 488 GENERATED_GBL_DATA_SIZE) 489 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 490 491 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 492 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 493 494 /* Serial Port */ 495 #define CONFIG_CONS_INDEX 1 496 #define CONFIG_SYS_NS16550_SERIAL 497 #define CONFIG_SYS_NS16550_REG_SIZE 1 498 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 499 500 #define CONFIG_SYS_BAUDRATE_TABLE \ 501 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 502 503 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 504 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 505 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 506 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 507 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 508 509 /* Video */ 510 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 511 #ifdef CONFIG_FSL_DIU_FB 512 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 513 #define CONFIG_VIDEO 514 #define CONFIG_CMD_BMP 515 #define CONFIG_CFB_CONSOLE 516 #define CONFIG_VIDEO_SW_CURSOR 517 #define CONFIG_VGA_AS_SINGLE_DEVICE 518 #define CONFIG_VIDEO_LOGO 519 #define CONFIG_VIDEO_BMP_LOGO 520 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 521 /* 522 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 523 * disable empty flash sector detection, which is I/O-intensive. 524 */ 525 #undef CONFIG_SYS_FLASH_EMPTY_INFO 526 #endif 527 528 /* I2C */ 529 #define CONFIG_SYS_I2C 530 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 531 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 532 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 533 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 534 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 535 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 536 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 537 538 #define I2C_PCA6408_BUS_NUM 1 539 #define I2C_PCA6408_ADDR 0x20 540 541 /* I2C bus multiplexer */ 542 #define I2C_MUX_CH_DEFAULT 0x8 543 544 /* 545 * RTC configuration 546 */ 547 #define RTC 548 #define CONFIG_RTC_DS1337 1 549 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 550 551 /* 552 * eSPI - Enhanced SPI 553 */ 554 #define CONFIG_SPI_FLASH_BAR 555 #define CONFIG_SF_DEFAULT_SPEED 10000000 556 #define CONFIG_SF_DEFAULT_MODE 0 557 558 /* 559 * General PCIe 560 * Memory space is mapped 1-1, but I/O space must start from 0. 561 */ 562 #define CONFIG_PCI /* Enable PCI/PCIE */ 563 #define CONFIG_PCIE1 /* PCIE controller 1 */ 564 #define CONFIG_PCIE2 /* PCIE controller 2 */ 565 #define CONFIG_PCIE3 /* PCIE controller 3 */ 566 #ifdef CONFIG_PPC_T1040 567 #define CONFIG_PCIE4 /* PCIE controller 4 */ 568 #endif 569 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 570 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 571 #define CONFIG_PCI_INDIRECT_BRIDGE 572 573 #ifdef CONFIG_PCI 574 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 575 #ifdef CONFIG_PCIE1 576 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 577 #ifdef CONFIG_PHYS_64BIT 578 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 580 #else 581 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 582 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 583 #endif 584 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 585 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 586 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 587 #ifdef CONFIG_PHYS_64BIT 588 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 589 #else 590 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 591 #endif 592 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 593 #endif 594 595 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 596 #ifdef CONFIG_PCIE2 597 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 598 #ifdef CONFIG_PHYS_64BIT 599 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 600 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 601 #else 602 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 603 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 604 #endif 605 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 606 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 607 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 608 #ifdef CONFIG_PHYS_64BIT 609 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 610 #else 611 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 612 #endif 613 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 614 #endif 615 616 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 617 #ifdef CONFIG_PCIE3 618 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 621 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 622 #else 623 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 624 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 625 #endif 626 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 627 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 628 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 629 #ifdef CONFIG_PHYS_64BIT 630 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 631 #else 632 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 633 #endif 634 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 635 #endif 636 637 /* controller 4, Base address 203000, to be removed */ 638 #ifdef CONFIG_PCIE4 639 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 640 #ifdef CONFIG_PHYS_64BIT 641 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 642 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 643 #else 644 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 645 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 646 #endif 647 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 648 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 649 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 650 #ifdef CONFIG_PHYS_64BIT 651 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 652 #else 653 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 654 #endif 655 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 656 #endif 657 658 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 659 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 660 #define CONFIG_DOS_PARTITION 661 #endif /* CONFIG_PCI */ 662 663 /* 664 * USB 665 */ 666 #define CONFIG_HAS_FSL_DR_USB 667 668 #ifdef CONFIG_HAS_FSL_DR_USB 669 #define CONFIG_USB_EHCI 670 #define CONFIG_USB_EHCI_FSL 671 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 672 #endif 673 674 /* 675 * SDHC 676 */ 677 #define CONFIG_MMC 678 #ifdef CONFIG_MMC 679 #define CONFIG_FSL_ESDHC 680 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 681 #define CONFIG_GENERIC_MMC 682 #define CONFIG_DOS_PARTITION 683 #endif 684 685 /* Qman/Bman */ 686 #ifndef CONFIG_NOBQFMAN 687 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 688 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 689 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 690 #ifdef CONFIG_PHYS_64BIT 691 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 692 #else 693 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 694 #endif 695 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 696 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 697 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 698 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 699 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 700 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 701 CONFIG_SYS_BMAN_CENA_SIZE) 702 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 703 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 704 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 705 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 706 #ifdef CONFIG_PHYS_64BIT 707 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 708 #else 709 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 710 #endif 711 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 712 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 713 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 714 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 715 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 716 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 717 CONFIG_SYS_QMAN_CENA_SIZE) 718 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 719 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 720 721 #define CONFIG_SYS_DPAA_FMAN 722 723 #ifdef CONFIG_T1024RDB 724 #define CONFIG_QE 725 #define CONFIG_U_QE 726 #endif 727 /* Default address of microcode for the Linux FMan driver */ 728 #if defined(CONFIG_SPIFLASH) 729 /* 730 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 731 * env, so we got 0x110000. 732 */ 733 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 734 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 735 #define CONFIG_SYS_QE_FW_ADDR 0x130000 736 #elif defined(CONFIG_SDCARD) 737 /* 738 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 739 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 740 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 741 */ 742 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 743 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 744 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 745 #elif defined(CONFIG_NAND) 746 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 747 #if defined(CONFIG_T1024RDB) 748 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 749 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 750 #elif defined(CONFIG_T1023RDB) 751 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 752 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 753 #endif 754 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 755 /* 756 * Slave has no ucode locally, it can fetch this from remote. When implementing 757 * in two corenet boards, slave's ucode could be stored in master's memory 758 * space, the address can be mapped from slave TLB->slave LAW-> 759 * slave SRIO or PCIE outbound window->master inbound window-> 760 * master LAW->the ucode address in master's memory space. 761 */ 762 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 763 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 764 #else 765 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 766 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 767 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 768 #endif 769 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 770 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 771 #endif /* CONFIG_NOBQFMAN */ 772 773 #ifdef CONFIG_SYS_DPAA_FMAN 774 #define CONFIG_FMAN_ENET 775 #define CONFIG_PHYLIB_10G 776 #define CONFIG_PHY_REALTEK 777 #define CONFIG_PHY_AQUANTIA 778 #if defined(CONFIG_T1024RDB) 779 #define RGMII_PHY1_ADDR 0x2 780 #define RGMII_PHY2_ADDR 0x6 781 #define SGMII_AQR_PHY_ADDR 0x2 782 #define FM1_10GEC1_PHY_ADDR 0x1 783 #elif defined(CONFIG_T1023RDB) 784 #define RGMII_PHY1_ADDR 0x1 785 #define SGMII_RTK_PHY_ADDR 0x3 786 #define SGMII_AQR_PHY_ADDR 0x2 787 #endif 788 #endif 789 790 #ifdef CONFIG_FMAN_ENET 791 #define CONFIG_MII /* MII PHY management */ 792 #define CONFIG_ETHPRIME "FM1@DTSEC4" 793 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 794 #endif 795 796 /* 797 * Dynamic MTD Partition support with mtdparts 798 */ 799 #ifndef CONFIG_SYS_NO_FLASH 800 #define CONFIG_MTD_DEVICE 801 #define CONFIG_MTD_PARTITIONS 802 #define CONFIG_CMD_MTDPARTS 803 #define CONFIG_FLASH_CFI_MTD 804 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 805 "spi0=spife110000.1" 806 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 807 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 808 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 809 "1m(uboot),5m(kernel),128k(dtb),-(user)" 810 #endif 811 812 /* 813 * Environment 814 */ 815 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 816 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 817 818 /* 819 * Command line configuration. 820 */ 821 #define CONFIG_CMD_DATE 822 #define CONFIG_CMD_EEPROM 823 #define CONFIG_CMD_ERRATA 824 #define CONFIG_CMD_IRQ 825 #define CONFIG_CMD_REGINFO 826 827 #ifdef CONFIG_PCI 828 #define CONFIG_CMD_PCI 829 #endif 830 831 /* 832 * Miscellaneous configurable options 833 */ 834 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 835 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 836 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 837 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 838 #ifdef CONFIG_CMD_KGDB 839 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 840 #else 841 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 842 #endif 843 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 844 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 845 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 846 847 /* 848 * For booting Linux, the board info and command line data 849 * have to be in the first 64 MB of memory, since this is 850 * the maximum mapped by the Linux kernel during initialization. 851 */ 852 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 853 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 854 855 #ifdef CONFIG_CMD_KGDB 856 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 857 #endif 858 859 /* 860 * Environment Configuration 861 */ 862 #define CONFIG_ROOTPATH "/opt/nfsroot" 863 #define CONFIG_BOOTFILE "uImage" 864 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 865 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 866 #define CONFIG_BAUDRATE 115200 867 #define __USB_PHY_TYPE utmi 868 869 #ifdef CONFIG_PPC_T1024 870 #define CONFIG_BOARDNAME t1024rdb 871 #define BANK_INTLV cs0_cs1 872 #else 873 #define CONFIG_BOARDNAME t1023rdb 874 #define BANK_INTLV null 875 #endif 876 877 #define CONFIG_EXTRA_ENV_SETTINGS \ 878 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 879 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 880 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 881 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 882 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 883 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 884 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 885 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 886 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 887 "netdev=eth0\0" \ 888 "tftpflash=tftpboot $loadaddr $uboot && " \ 889 "protect off $ubootaddr +$filesize && " \ 890 "erase $ubootaddr +$filesize && " \ 891 "cp.b $loadaddr $ubootaddr $filesize && " \ 892 "protect on $ubootaddr +$filesize && " \ 893 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 894 "consoledev=ttyS0\0" \ 895 "ramdiskaddr=2000000\0" \ 896 "fdtaddr=1e00000\0" \ 897 "bdev=sda3\0" 898 899 #define CONFIG_LINUX \ 900 "setenv bootargs root=/dev/ram rw " \ 901 "console=$consoledev,$baudrate $othbootargs;" \ 902 "setenv ramdiskaddr 0x02000000;" \ 903 "setenv fdtaddr 0x00c00000;" \ 904 "setenv loadaddr 0x1000000;" \ 905 "bootm $loadaddr $ramdiskaddr $fdtaddr" 906 907 #define CONFIG_NFSBOOTCOMMAND \ 908 "setenv bootargs root=/dev/nfs rw " \ 909 "nfsroot=$serverip:$rootpath " \ 910 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 911 "console=$consoledev,$baudrate $othbootargs;" \ 912 "tftp $loadaddr $bootfile;" \ 913 "tftp $fdtaddr $fdtfile;" \ 914 "bootm $loadaddr - $fdtaddr" 915 916 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 917 918 /* Hash command with SHA acceleration supported in hardware */ 919 #ifdef CONFIG_FSL_CAAM 920 #define CONFIG_CMD_HASH 921 #define CONFIG_SHA_HW_ACCEL 922 #endif 923 924 #include <asm/fsl_secure_boot.h> 925 926 #endif /* __T1024RDB_H */ 927