1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 30 31 /* support deep sleep */ 32 #ifdef CONFIG_ARCH_T1024 33 #define CONFIG_DEEP_SLEEP 34 #endif 35 36 #ifdef CONFIG_RAMBOOT_PBL 37 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 40 #define CONFIG_SYS_TEXT_BASE 0x30001000 41 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 42 #define CONFIG_SPL_PAD_TO 0x40000 43 #define CONFIG_SPL_MAX_SIZE 0x28000 44 #define RESET_VECTOR_OFFSET 0x27FFC 45 #define BOOT_PAGE_OFFSET 0x27000 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SPL_SKIP_RELOCATE 48 #define CONFIG_SPL_COMMON_INIT_DDR 49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 50 #endif 51 52 #ifdef CONFIG_NAND 53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 54 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 55 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 56 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 58 #if defined(CONFIG_TARGET_T1024RDB) 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 60 #elif defined(CONFIG_TARGET_T1023RDB) 61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 62 #endif 63 #define CONFIG_SPL_NAND_BOOT 64 #endif 65 66 #ifdef CONFIG_SPIFLASH 67 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 68 #define CONFIG_SPL_SPI_FLASH_MINIMAL 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 74 #ifndef CONFIG_SPL_BUILD 75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 76 #endif 77 #if defined(CONFIG_TARGET_T1024RDB) 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 79 #elif defined(CONFIG_TARGET_T1023RDB) 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 81 #endif 82 #define CONFIG_SPL_SPI_BOOT 83 #endif 84 85 #ifdef CONFIG_SDCARD 86 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 87 #define CONFIG_SPL_MMC_MINIMAL 88 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 89 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 90 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 91 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 92 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 93 #ifndef CONFIG_SPL_BUILD 94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 95 #endif 96 #if defined(CONFIG_TARGET_T1024RDB) 97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 98 #elif defined(CONFIG_TARGET_T1023RDB) 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 100 #endif 101 #define CONFIG_SPL_MMC_BOOT 102 #endif 103 104 #endif /* CONFIG_RAMBOOT_PBL */ 105 106 #ifndef CONFIG_SYS_TEXT_BASE 107 #define CONFIG_SYS_TEXT_BASE 0xeff40000 108 #endif 109 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 112 #endif 113 114 #ifdef CONFIG_MTD_NOR_FLASH 115 #define CONFIG_FLASH_CFI_DRIVER 116 #define CONFIG_SYS_FLASH_CFI 117 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 118 #endif 119 120 /* PCIe Boot - Master */ 121 #define CONFIG_SRIO_PCIE_BOOT_MASTER 122 /* 123 * for slave u-boot IMAGE instored in master memory space, 124 * PHYS must be aligned based on the SIZE 125 */ 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 128 #ifdef CONFIG_PHYS_64BIT 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 131 #else 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 134 #endif 135 /* 136 * for slave UCODE and ENV instored in master memory space, 137 * PHYS must be aligned based on the SIZE 138 */ 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 142 #else 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 145 #endif 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 147 /* slave core release by master*/ 148 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 149 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 150 151 /* PCIe Boot - Slave */ 152 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 153 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 155 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 156 /* Set 1M boot space for PCIe boot */ 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 159 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 160 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 161 #endif 162 163 #if defined(CONFIG_SPIFLASH) 164 #define CONFIG_SYS_EXTRA_ENV_RELOC 165 #define CONFIG_ENV_IS_IN_SPI_FLASH 166 #define CONFIG_ENV_SPI_BUS 0 167 #define CONFIG_ENV_SPI_CS 0 168 #define CONFIG_ENV_SPI_MAX_HZ 10000000 169 #define CONFIG_ENV_SPI_MODE 0 170 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 171 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 172 #if defined(CONFIG_TARGET_T1024RDB) 173 #define CONFIG_ENV_SECT_SIZE 0x10000 174 #elif defined(CONFIG_TARGET_T1023RDB) 175 #define CONFIG_ENV_SECT_SIZE 0x40000 176 #endif 177 #elif defined(CONFIG_SDCARD) 178 #define CONFIG_SYS_EXTRA_ENV_RELOC 179 #define CONFIG_ENV_IS_IN_MMC 180 #define CONFIG_SYS_MMC_ENV_DEV 0 181 #define CONFIG_ENV_SIZE 0x2000 182 #define CONFIG_ENV_OFFSET (512 * 0x800) 183 #elif defined(CONFIG_NAND) 184 #define CONFIG_SYS_EXTRA_ENV_RELOC 185 #define CONFIG_ENV_IS_IN_NAND 186 #define CONFIG_ENV_SIZE 0x2000 187 #if defined(CONFIG_TARGET_T1024RDB) 188 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 189 #elif defined(CONFIG_TARGET_T1023RDB) 190 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 191 #endif 192 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 193 #define CONFIG_ENV_IS_IN_REMOTE 194 #define CONFIG_ENV_ADDR 0xffe20000 195 #define CONFIG_ENV_SIZE 0x2000 196 #elif defined(CONFIG_ENV_IS_NOWHERE) 197 #define CONFIG_ENV_SIZE 0x2000 198 #else 199 #define CONFIG_ENV_IS_IN_FLASH 200 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 201 #define CONFIG_ENV_SIZE 0x2000 202 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 203 #endif 204 205 #ifndef __ASSEMBLY__ 206 unsigned long get_board_sys_clk(void); 207 unsigned long get_board_ddr_clk(void); 208 #endif 209 210 #define CONFIG_SYS_CLK_FREQ 100000000 211 #define CONFIG_DDR_CLK_FREQ 100000000 212 213 /* 214 * These can be toggled for performance analysis, otherwise use default. 215 */ 216 #define CONFIG_SYS_CACHE_STASHING 217 #define CONFIG_BACKSIDE_L2_CACHE 218 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 219 #define CONFIG_BTB /* toggle branch predition */ 220 #define CONFIG_DDR_ECC 221 #ifdef CONFIG_DDR_ECC 222 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 223 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 224 #endif 225 226 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 227 #define CONFIG_SYS_MEMTEST_END 0x00400000 228 #define CONFIG_SYS_ALT_MEMTEST 229 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 230 231 /* 232 * Config the L3 Cache as L3 SRAM 233 */ 234 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 235 #define CONFIG_SYS_L3_SIZE (256 << 10) 236 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 237 #ifdef CONFIG_RAMBOOT_PBL 238 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 239 #endif 240 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 241 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 242 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 243 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 244 245 #ifdef CONFIG_PHYS_64BIT 246 #define CONFIG_SYS_DCSRBAR 0xf0000000 247 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 248 #endif 249 250 /* EEPROM */ 251 #define CONFIG_ID_EEPROM 252 #define CONFIG_SYS_I2C_EEPROM_NXID 253 #define CONFIG_SYS_EEPROM_BUS_NUM 0 254 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 255 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 258 259 /* 260 * DDR Setup 261 */ 262 #define CONFIG_VERY_BIG_RAM 263 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 264 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 265 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 266 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 267 #define CONFIG_FSL_DDR_INTERACTIVE 268 #if defined(CONFIG_TARGET_T1024RDB) 269 #define CONFIG_DDR_SPD 270 #define CONFIG_SYS_SPD_BUS_NUM 0 271 #define SPD_EEPROM_ADDRESS 0x51 272 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 273 #elif defined(CONFIG_TARGET_T1023RDB) 274 #define CONFIG_SYS_DDR_RAW_TIMING 275 #define CONFIG_SYS_SDRAM_SIZE 2048 276 #endif 277 278 /* 279 * IFC Definitions 280 */ 281 #define CONFIG_SYS_FLASH_BASE 0xe8000000 282 #ifdef CONFIG_PHYS_64BIT 283 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 284 #else 285 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 286 #endif 287 288 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 289 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 290 CSPR_PORT_SIZE_16 | \ 291 CSPR_MSEL_NOR | \ 292 CSPR_V) 293 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 294 295 /* NOR Flash Timing Params */ 296 #if defined(CONFIG_TARGET_T1024RDB) 297 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 298 #elif defined(CONFIG_TARGET_T1023RDB) 299 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 300 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 301 #endif 302 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 303 FTIM0_NOR_TEADC(0x5) | \ 304 FTIM0_NOR_TEAHC(0x5)) 305 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 306 FTIM1_NOR_TRAD_NOR(0x1A) |\ 307 FTIM1_NOR_TSEQRAD_NOR(0x13)) 308 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 309 FTIM2_NOR_TCH(0x4) | \ 310 FTIM2_NOR_TWPH(0x0E) | \ 311 FTIM2_NOR_TWP(0x1c)) 312 #define CONFIG_SYS_NOR_FTIM3 0x0 313 314 #define CONFIG_SYS_FLASH_QUIET_TEST 315 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 316 317 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 318 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 319 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 320 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 321 322 #define CONFIG_SYS_FLASH_EMPTY_INFO 323 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 324 325 #ifdef CONFIG_TARGET_T1024RDB 326 /* CPLD on IFC */ 327 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 328 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 329 #define CONFIG_SYS_CSPR2_EXT (0xf) 330 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 331 | CSPR_PORT_SIZE_8 \ 332 | CSPR_MSEL_GPCM \ 333 | CSPR_V) 334 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 335 #define CONFIG_SYS_CSOR2 0x0 336 337 /* CPLD Timing parameters for IFC CS2 */ 338 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 339 FTIM0_GPCM_TEADC(0x0e) | \ 340 FTIM0_GPCM_TEAHC(0x0e)) 341 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 342 FTIM1_GPCM_TRAD(0x1f)) 343 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 344 FTIM2_GPCM_TCH(0x8) | \ 345 FTIM2_GPCM_TWP(0x1f)) 346 #define CONFIG_SYS_CS2_FTIM3 0x0 347 #endif 348 349 /* NAND Flash on IFC */ 350 #define CONFIG_NAND_FSL_IFC 351 #define CONFIG_SYS_NAND_BASE 0xff800000 352 #ifdef CONFIG_PHYS_64BIT 353 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 354 #else 355 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 356 #endif 357 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 358 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 359 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 360 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 361 | CSPR_V) 362 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 363 364 #if defined(CONFIG_TARGET_T1024RDB) 365 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 366 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 367 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 368 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 369 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 370 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 371 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 372 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 373 #elif defined(CONFIG_TARGET_T1023RDB) 374 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 375 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 376 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 377 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 378 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 379 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 380 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 381 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 382 #endif 383 384 #define CONFIG_SYS_NAND_ONFI_DETECTION 385 /* ONFI NAND Flash mode0 Timing Params */ 386 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 387 FTIM0_NAND_TWP(0x18) | \ 388 FTIM0_NAND_TWCHT(0x07) | \ 389 FTIM0_NAND_TWH(0x0a)) 390 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 391 FTIM1_NAND_TWBE(0x39) | \ 392 FTIM1_NAND_TRR(0x0e) | \ 393 FTIM1_NAND_TRP(0x18)) 394 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 395 FTIM2_NAND_TREH(0x0a) | \ 396 FTIM2_NAND_TWHRE(0x1e)) 397 #define CONFIG_SYS_NAND_FTIM3 0x0 398 399 #define CONFIG_SYS_NAND_DDR_LAW 11 400 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 401 #define CONFIG_SYS_MAX_NAND_DEVICE 1 402 #define CONFIG_CMD_NAND 403 404 #if defined(CONFIG_NAND) 405 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 406 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 407 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 408 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 409 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 410 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 411 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 412 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 413 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 421 #else 422 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 423 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 424 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 425 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 426 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 427 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 428 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 429 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 430 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 431 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 432 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 433 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 434 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 435 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 436 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 437 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 438 #endif 439 440 #ifdef CONFIG_SPL_BUILD 441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 442 #else 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 444 #endif 445 446 #if defined(CONFIG_RAMBOOT_PBL) 447 #define CONFIG_SYS_RAMBOOT 448 #endif 449 450 #define CONFIG_BOARD_EARLY_INIT_R 451 #define CONFIG_MISC_INIT_R 452 453 #define CONFIG_HWCONFIG 454 455 /* define to use L1 as initial stack */ 456 #define CONFIG_L1_INIT_RAM 457 #define CONFIG_SYS_INIT_RAM_LOCK 458 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 462 /* The assembler doesn't like typecast */ 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 464 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 465 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 466 #else 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 470 #endif 471 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 472 473 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 474 GENERATED_GBL_DATA_SIZE) 475 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 476 477 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 478 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 479 480 /* Serial Port */ 481 #define CONFIG_CONS_INDEX 1 482 #define CONFIG_SYS_NS16550_SERIAL 483 #define CONFIG_SYS_NS16550_REG_SIZE 1 484 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 485 486 #define CONFIG_SYS_BAUDRATE_TABLE \ 487 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 488 489 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 490 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 491 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 492 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 493 494 /* Video */ 495 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 496 #ifdef CONFIG_FSL_DIU_FB 497 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 498 #define CONFIG_CMD_BMP 499 #define CONFIG_VIDEO_LOGO 500 #define CONFIG_VIDEO_BMP_LOGO 501 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 502 /* 503 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 504 * disable empty flash sector detection, which is I/O-intensive. 505 */ 506 #undef CONFIG_SYS_FLASH_EMPTY_INFO 507 #endif 508 509 /* I2C */ 510 #define CONFIG_SYS_I2C 511 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 512 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 513 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 514 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 515 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 517 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 518 519 #define I2C_PCA6408_BUS_NUM 1 520 #define I2C_PCA6408_ADDR 0x20 521 522 /* I2C bus multiplexer */ 523 #define I2C_MUX_CH_DEFAULT 0x8 524 525 /* 526 * RTC configuration 527 */ 528 #define RTC 529 #define CONFIG_RTC_DS1337 1 530 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 531 532 /* 533 * eSPI - Enhanced SPI 534 */ 535 #define CONFIG_SPI_FLASH_BAR 536 #define CONFIG_SF_DEFAULT_SPEED 10000000 537 #define CONFIG_SF_DEFAULT_MODE 0 538 539 /* 540 * General PCIe 541 * Memory space is mapped 1-1, but I/O space must start from 0. 542 */ 543 #define CONFIG_PCIE1 /* PCIE controller 1 */ 544 #define CONFIG_PCIE2 /* PCIE controller 2 */ 545 #define CONFIG_PCIE3 /* PCIE controller 3 */ 546 #ifdef CONFIG_ARCH_T1040 547 #define CONFIG_PCIE4 /* PCIE controller 4 */ 548 #endif 549 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 550 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 551 #define CONFIG_PCI_INDIRECT_BRIDGE 552 553 #ifdef CONFIG_PCI 554 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 555 #ifdef CONFIG_PCIE1 556 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 557 #ifdef CONFIG_PHYS_64BIT 558 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 559 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 560 #else 561 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 562 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 563 #endif 564 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 565 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 566 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 567 #ifdef CONFIG_PHYS_64BIT 568 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 569 #else 570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 571 #endif 572 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 573 #endif 574 575 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 576 #ifdef CONFIG_PCIE2 577 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 580 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 581 #else 582 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 583 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 584 #endif 585 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 587 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 590 #else 591 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 592 #endif 593 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 594 #endif 595 596 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 597 #ifdef CONFIG_PCIE3 598 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 601 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 602 #else 603 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 604 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 605 #endif 606 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 607 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 608 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 609 #ifdef CONFIG_PHYS_64BIT 610 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 611 #else 612 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 613 #endif 614 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 615 #endif 616 617 /* controller 4, Base address 203000, to be removed */ 618 #ifdef CONFIG_PCIE4 619 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 622 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 623 #else 624 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 625 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 626 #endif 627 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 628 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 629 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 630 #ifdef CONFIG_PHYS_64BIT 631 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 632 #else 633 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 634 #endif 635 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 636 #endif 637 638 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 639 #endif /* CONFIG_PCI */ 640 641 /* 642 * USB 643 */ 644 #define CONFIG_HAS_FSL_DR_USB 645 646 #ifdef CONFIG_HAS_FSL_DR_USB 647 #define CONFIG_USB_EHCI 648 #define CONFIG_USB_EHCI_FSL 649 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 650 #endif 651 652 /* 653 * SDHC 654 */ 655 #ifdef CONFIG_MMC 656 #define CONFIG_FSL_ESDHC 657 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 658 #endif 659 660 /* Qman/Bman */ 661 #ifndef CONFIG_NOBQFMAN 662 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 663 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 664 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 665 #ifdef CONFIG_PHYS_64BIT 666 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 667 #else 668 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 669 #endif 670 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 671 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 672 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 673 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 674 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 675 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 676 CONFIG_SYS_BMAN_CENA_SIZE) 677 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 678 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 679 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 680 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 681 #ifdef CONFIG_PHYS_64BIT 682 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 683 #else 684 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 685 #endif 686 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 687 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 688 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 689 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 690 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 691 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 692 CONFIG_SYS_QMAN_CENA_SIZE) 693 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 694 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 695 696 #define CONFIG_SYS_DPAA_FMAN 697 698 #ifdef CONFIG_TARGET_T1024RDB 699 #define CONFIG_QE 700 #define CONFIG_U_QE 701 #endif 702 /* Default address of microcode for the Linux FMan driver */ 703 #if defined(CONFIG_SPIFLASH) 704 /* 705 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 706 * env, so we got 0x110000. 707 */ 708 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 709 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 710 #define CONFIG_SYS_QE_FW_ADDR 0x130000 711 #elif defined(CONFIG_SDCARD) 712 /* 713 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 714 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 715 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 716 */ 717 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 718 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 719 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 720 #elif defined(CONFIG_NAND) 721 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 722 #if defined(CONFIG_TARGET_T1024RDB) 723 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 724 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 725 #elif defined(CONFIG_TARGET_T1023RDB) 726 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 727 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 728 #endif 729 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 730 /* 731 * Slave has no ucode locally, it can fetch this from remote. When implementing 732 * in two corenet boards, slave's ucode could be stored in master's memory 733 * space, the address can be mapped from slave TLB->slave LAW-> 734 * slave SRIO or PCIE outbound window->master inbound window-> 735 * master LAW->the ucode address in master's memory space. 736 */ 737 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 738 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 739 #else 740 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 741 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 742 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 743 #endif 744 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 745 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 746 #endif /* CONFIG_NOBQFMAN */ 747 748 #ifdef CONFIG_SYS_DPAA_FMAN 749 #define CONFIG_FMAN_ENET 750 #define CONFIG_PHYLIB_10G 751 #define CONFIG_PHY_REALTEK 752 #define CONFIG_PHY_AQUANTIA 753 #if defined(CONFIG_TARGET_T1024RDB) 754 #define RGMII_PHY1_ADDR 0x2 755 #define RGMII_PHY2_ADDR 0x6 756 #define SGMII_AQR_PHY_ADDR 0x2 757 #define FM1_10GEC1_PHY_ADDR 0x1 758 #elif defined(CONFIG_TARGET_T1023RDB) 759 #define RGMII_PHY1_ADDR 0x1 760 #define SGMII_RTK_PHY_ADDR 0x3 761 #define SGMII_AQR_PHY_ADDR 0x2 762 #endif 763 #endif 764 765 #ifdef CONFIG_FMAN_ENET 766 #define CONFIG_MII /* MII PHY management */ 767 #define CONFIG_ETHPRIME "FM1@DTSEC4" 768 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 769 #endif 770 771 /* 772 * Dynamic MTD Partition support with mtdparts 773 */ 774 #ifdef CONFIG_MTD_NOR_FLASH 775 #define CONFIG_MTD_DEVICE 776 #define CONFIG_MTD_PARTITIONS 777 #define CONFIG_CMD_MTDPARTS 778 #define CONFIG_FLASH_CFI_MTD 779 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 780 "spi0=spife110000.1" 781 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 782 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 783 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 784 "1m(uboot),5m(kernel),128k(dtb),-(user)" 785 #endif 786 787 /* 788 * Environment 789 */ 790 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 791 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 792 793 /* 794 * Command line configuration. 795 */ 796 #define CONFIG_CMD_DATE 797 #define CONFIG_CMD_EEPROM 798 #define CONFIG_CMD_ERRATA 799 #define CONFIG_CMD_IRQ 800 #define CONFIG_CMD_REGINFO 801 802 #ifdef CONFIG_PCI 803 #define CONFIG_CMD_PCI 804 #endif 805 806 /* 807 * Miscellaneous configurable options 808 */ 809 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 810 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 811 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 812 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 813 #ifdef CONFIG_CMD_KGDB 814 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 815 #else 816 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 817 #endif 818 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 819 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 820 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 821 822 /* 823 * For booting Linux, the board info and command line data 824 * have to be in the first 64 MB of memory, since this is 825 * the maximum mapped by the Linux kernel during initialization. 826 */ 827 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 828 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 829 830 #ifdef CONFIG_CMD_KGDB 831 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 832 #endif 833 834 /* 835 * Environment Configuration 836 */ 837 #define CONFIG_ROOTPATH "/opt/nfsroot" 838 #define CONFIG_BOOTFILE "uImage" 839 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 840 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 841 #define CONFIG_BAUDRATE 115200 842 #define __USB_PHY_TYPE utmi 843 844 #ifdef CONFIG_ARCH_T1024 845 #define CONFIG_BOARDNAME t1024rdb 846 #define BANK_INTLV cs0_cs1 847 #else 848 #define CONFIG_BOARDNAME t1023rdb 849 #define BANK_INTLV null 850 #endif 851 852 #define CONFIG_EXTRA_ENV_SETTINGS \ 853 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 854 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 855 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 856 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 857 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 858 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 859 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 860 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 861 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 862 "netdev=eth0\0" \ 863 "tftpflash=tftpboot $loadaddr $uboot && " \ 864 "protect off $ubootaddr +$filesize && " \ 865 "erase $ubootaddr +$filesize && " \ 866 "cp.b $loadaddr $ubootaddr $filesize && " \ 867 "protect on $ubootaddr +$filesize && " \ 868 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 869 "consoledev=ttyS0\0" \ 870 "ramdiskaddr=2000000\0" \ 871 "fdtaddr=1e00000\0" \ 872 "bdev=sda3\0" 873 874 #define CONFIG_LINUX \ 875 "setenv bootargs root=/dev/ram rw " \ 876 "console=$consoledev,$baudrate $othbootargs;" \ 877 "setenv ramdiskaddr 0x02000000;" \ 878 "setenv fdtaddr 0x00c00000;" \ 879 "setenv loadaddr 0x1000000;" \ 880 "bootm $loadaddr $ramdiskaddr $fdtaddr" 881 882 #define CONFIG_NFSBOOTCOMMAND \ 883 "setenv bootargs root=/dev/nfs rw " \ 884 "nfsroot=$serverip:$rootpath " \ 885 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 886 "console=$consoledev,$baudrate $othbootargs;" \ 887 "tftp $loadaddr $bootfile;" \ 888 "tftp $fdtaddr $fdtfile;" \ 889 "bootm $loadaddr - $fdtaddr" 890 891 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 892 893 /* Hash command with SHA acceleration supported in hardware */ 894 #ifdef CONFIG_FSL_CAAM 895 #define CONFIG_CMD_HASH 896 #define CONFIG_SHA_HW_ACCEL 897 #endif 898 899 #include <asm/fsl_secure_boot.h> 900 901 #endif /* __T1024RDB_H */ 902