1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #define CONFIG_E500MC /* BOOKE e500mc family */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_ENV_OVERWRITE 33 34 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 35 36 /* support deep sleep */ 37 #ifdef CONFIG_PPC_T1024 38 #define CONFIG_DEEP_SLEEP 39 #endif 40 #if defined(CONFIG_DEEP_SLEEP) 41 #define CONFIG_SILENT_CONSOLE 42 #define CONFIG_BOARD_EARLY_INIT_F 43 #endif 44 45 #ifdef CONFIG_RAMBOOT_PBL 46 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 47 #if defined(CONFIG_T1024RDB) 48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 49 #elif defined(CONFIG_T1023RDB) 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 51 #endif 52 #define CONFIG_SPL_FLUSH_IMAGE 53 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 #define CONFIG_SYS_TEXT_BASE 0x30001000 56 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 57 #define CONFIG_SPL_PAD_TO 0x40000 58 #define CONFIG_SPL_MAX_SIZE 0x28000 59 #define RESET_VECTOR_OFFSET 0x27FFC 60 #define BOOT_PAGE_OFFSET 0x27000 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #ifdef CONFIG_NAND 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 70 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 71 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #define CONFIG_SPL_SPI_BOOT 89 #endif 90 91 #ifdef CONFIG_SDCARD 92 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 93 #define CONFIG_SPL_MMC_MINIMAL 94 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 96 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 97 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #define CONFIG_SPL_MMC_BOOT 103 #endif 104 105 #endif /* CONFIG_RAMBOOT_PBL */ 106 107 #ifndef CONFIG_SYS_TEXT_BASE 108 #define CONFIG_SYS_TEXT_BASE 0xeff40000 109 #endif 110 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 113 #endif 114 115 #ifndef CONFIG_SYS_NO_FLASH 116 #define CONFIG_FLASH_CFI_DRIVER 117 #define CONFIG_SYS_FLASH_CFI 118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 119 #endif 120 121 /* PCIe Boot - Master */ 122 #define CONFIG_SRIO_PCIE_BOOT_MASTER 123 /* 124 * for slave u-boot IMAGE instored in master memory space, 125 * PHYS must be aligned based on the SIZE 126 */ 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 132 #else 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 135 #endif 136 /* 137 * for slave UCODE and ENV instored in master memory space, 138 * PHYS must be aligned based on the SIZE 139 */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 143 #else 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 146 #endif 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 148 /* slave core release by master*/ 149 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 150 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 151 152 /* PCIe Boot - Slave */ 153 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 156 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 157 /* Set 1M boot space for PCIe boot */ 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 161 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 162 #define CONFIG_SYS_NO_FLASH 163 #endif 164 165 #if defined(CONFIG_SPIFLASH) 166 #define CONFIG_SYS_EXTRA_ENV_RELOC 167 #define CONFIG_ENV_IS_IN_SPI_FLASH 168 #define CONFIG_ENV_SPI_BUS 0 169 #define CONFIG_ENV_SPI_CS 0 170 #define CONFIG_ENV_SPI_MAX_HZ 10000000 171 #define CONFIG_ENV_SPI_MODE 0 172 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 173 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 174 #if defined(CONFIG_T1024RDB) 175 #define CONFIG_ENV_SECT_SIZE 0x10000 176 #elif defined(CONFIG_T1023RDB) 177 #define CONFIG_ENV_SECT_SIZE 0x40000 178 #endif 179 #elif defined(CONFIG_SDCARD) 180 #define CONFIG_SYS_EXTRA_ENV_RELOC 181 #define CONFIG_ENV_IS_IN_MMC 182 #define CONFIG_SYS_MMC_ENV_DEV 0 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_OFFSET (512 * 0x800) 185 #elif defined(CONFIG_NAND) 186 #define CONFIG_SYS_EXTRA_ENV_RELOC 187 #define CONFIG_ENV_IS_IN_NAND 188 #define CONFIG_ENV_SIZE 0x2000 189 #if defined(CONFIG_T1024RDB) 190 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 191 #elif defined(CONFIG_T1023RDB) 192 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 193 #endif 194 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 195 #define CONFIG_ENV_IS_IN_REMOTE 196 #define CONFIG_ENV_ADDR 0xffe20000 197 #define CONFIG_ENV_SIZE 0x2000 198 #elif defined(CONFIG_ENV_IS_NOWHERE) 199 #define CONFIG_ENV_SIZE 0x2000 200 #else 201 #define CONFIG_ENV_IS_IN_FLASH 202 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 203 #define CONFIG_ENV_SIZE 0x2000 204 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 205 #endif 206 207 #ifndef __ASSEMBLY__ 208 unsigned long get_board_sys_clk(void); 209 unsigned long get_board_ddr_clk(void); 210 #endif 211 212 #define CONFIG_SYS_CLK_FREQ 100000000 213 #define CONFIG_DDR_CLK_FREQ 100000000 214 215 /* 216 * These can be toggled for performance analysis, otherwise use default. 217 */ 218 #define CONFIG_SYS_CACHE_STASHING 219 #define CONFIG_BACKSIDE_L2_CACHE 220 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 221 #define CONFIG_BTB /* toggle branch predition */ 222 #define CONFIG_DDR_ECC 223 #ifdef CONFIG_DDR_ECC 224 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 225 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 226 #endif 227 228 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 229 #define CONFIG_SYS_MEMTEST_END 0x00400000 230 #define CONFIG_SYS_ALT_MEMTEST 231 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 232 233 /* 234 * Config the L3 Cache as L3 SRAM 235 */ 236 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 237 #define CONFIG_SYS_L3_SIZE (256 << 10) 238 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 239 #ifdef CONFIG_RAMBOOT_PBL 240 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 241 #endif 242 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 243 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 244 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 245 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 246 247 #ifdef CONFIG_PHYS_64BIT 248 #define CONFIG_SYS_DCSRBAR 0xf0000000 249 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 250 #endif 251 252 /* EEPROM */ 253 #define CONFIG_ID_EEPROM 254 #define CONFIG_SYS_I2C_EEPROM_NXID 255 #define CONFIG_SYS_EEPROM_BUS_NUM 0 256 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 257 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 260 261 /* 262 * DDR Setup 263 */ 264 #define CONFIG_VERY_BIG_RAM 265 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 266 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 267 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 268 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 269 #define CONFIG_FSL_DDR_INTERACTIVE 270 #if defined(CONFIG_T1024RDB) 271 #define CONFIG_DDR_SPD 272 #define CONFIG_SYS_FSL_DDR3 273 #define CONFIG_SYS_SPD_BUS_NUM 0 274 #define SPD_EEPROM_ADDRESS 0x51 275 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 276 #elif defined(CONFIG_T1023RDB) 277 #define CONFIG_SYS_FSL_DDR4 278 #define CONFIG_SYS_DDR_RAW_TIMING 279 #define CONFIG_SYS_SDRAM_SIZE 2048 280 #endif 281 282 /* 283 * IFC Definitions 284 */ 285 #define CONFIG_SYS_FLASH_BASE 0xe8000000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 288 #else 289 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 290 #endif 291 292 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 293 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 294 CSPR_PORT_SIZE_16 | \ 295 CSPR_MSEL_NOR | \ 296 CSPR_V) 297 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 298 299 /* NOR Flash Timing Params */ 300 #if defined(CONFIG_T1024RDB) 301 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 302 #elif defined(CONFIG_T1023RDB) 303 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 304 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 305 #endif 306 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 307 FTIM0_NOR_TEADC(0x5) | \ 308 FTIM0_NOR_TEAHC(0x5)) 309 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 310 FTIM1_NOR_TRAD_NOR(0x1A) |\ 311 FTIM1_NOR_TSEQRAD_NOR(0x13)) 312 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 313 FTIM2_NOR_TCH(0x4) | \ 314 FTIM2_NOR_TWPH(0x0E) | \ 315 FTIM2_NOR_TWP(0x1c)) 316 #define CONFIG_SYS_NOR_FTIM3 0x0 317 318 #define CONFIG_SYS_FLASH_QUIET_TEST 319 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 320 321 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 322 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 323 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 324 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 325 326 #define CONFIG_SYS_FLASH_EMPTY_INFO 327 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 328 329 #ifdef CONFIG_T1024RDB 330 /* CPLD on IFC */ 331 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 332 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 333 #define CONFIG_SYS_CSPR2_EXT (0xf) 334 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 335 | CSPR_PORT_SIZE_8 \ 336 | CSPR_MSEL_GPCM \ 337 | CSPR_V) 338 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 339 #define CONFIG_SYS_CSOR2 0x0 340 341 /* CPLD Timing parameters for IFC CS2 */ 342 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 343 FTIM0_GPCM_TEADC(0x0e) | \ 344 FTIM0_GPCM_TEAHC(0x0e)) 345 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 346 FTIM1_GPCM_TRAD(0x1f)) 347 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 348 FTIM2_GPCM_TCH(0x8) | \ 349 FTIM2_GPCM_TWP(0x1f)) 350 #define CONFIG_SYS_CS2_FTIM3 0x0 351 #endif 352 353 /* NAND Flash on IFC */ 354 #define CONFIG_NAND_FSL_IFC 355 #define CONFIG_SYS_NAND_BASE 0xff800000 356 #ifdef CONFIG_PHYS_64BIT 357 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 358 #else 359 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 360 #endif 361 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 362 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 363 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 364 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 365 | CSPR_V) 366 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 367 368 #if defined(CONFIG_T1024RDB) 369 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 370 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 371 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 372 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 373 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 374 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 375 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 376 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 377 #elif defined(CONFIG_T1023RDB) 378 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 379 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 380 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 381 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 382 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 383 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 384 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 385 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 386 #endif 387 388 #define CONFIG_SYS_NAND_ONFI_DETECTION 389 /* ONFI NAND Flash mode0 Timing Params */ 390 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 391 FTIM0_NAND_TWP(0x18) | \ 392 FTIM0_NAND_TWCHT(0x07) | \ 393 FTIM0_NAND_TWH(0x0a)) 394 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 395 FTIM1_NAND_TWBE(0x39) | \ 396 FTIM1_NAND_TRR(0x0e) | \ 397 FTIM1_NAND_TRP(0x18)) 398 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 399 FTIM2_NAND_TREH(0x0a) | \ 400 FTIM2_NAND_TWHRE(0x1e)) 401 #define CONFIG_SYS_NAND_FTIM3 0x0 402 403 #define CONFIG_SYS_NAND_DDR_LAW 11 404 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 405 #define CONFIG_SYS_MAX_NAND_DEVICE 1 406 #define CONFIG_CMD_NAND 407 408 #if defined(CONFIG_NAND) 409 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 410 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 411 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 412 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 413 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 414 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 415 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 416 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 417 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 418 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 419 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 420 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 421 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 422 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 423 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 424 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 425 #else 426 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 427 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 428 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 429 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 430 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 431 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 432 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 433 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 434 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 435 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 436 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 437 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 438 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 439 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 440 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 441 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 442 #endif 443 444 #ifdef CONFIG_SPL_BUILD 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 446 #else 447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 448 #endif 449 450 #if defined(CONFIG_RAMBOOT_PBL) 451 #define CONFIG_SYS_RAMBOOT 452 #endif 453 454 #define CONFIG_BOARD_EARLY_INIT_R 455 #define CONFIG_MISC_INIT_R 456 457 #define CONFIG_HWCONFIG 458 459 /* define to use L1 as initial stack */ 460 #define CONFIG_L1_INIT_RAM 461 #define CONFIG_SYS_INIT_RAM_LOCK 462 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 466 /* The assembler doesn't like typecast */ 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 468 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 469 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 470 #else 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 474 #endif 475 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 476 477 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 478 GENERATED_GBL_DATA_SIZE) 479 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 480 481 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 482 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 483 484 /* Serial Port */ 485 #define CONFIG_CONS_INDEX 1 486 #define CONFIG_SYS_NS16550_SERIAL 487 #define CONFIG_SYS_NS16550_REG_SIZE 1 488 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 489 490 #define CONFIG_SYS_BAUDRATE_TABLE \ 491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 492 493 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 494 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 495 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 496 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 497 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 498 499 /* Video */ 500 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 501 #ifdef CONFIG_FSL_DIU_FB 502 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 503 #define CONFIG_VIDEO 504 #define CONFIG_CMD_BMP 505 #define CONFIG_CFB_CONSOLE 506 #define CONFIG_VIDEO_SW_CURSOR 507 #define CONFIG_VGA_AS_SINGLE_DEVICE 508 #define CONFIG_VIDEO_LOGO 509 #define CONFIG_VIDEO_BMP_LOGO 510 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 511 /* 512 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 513 * disable empty flash sector detection, which is I/O-intensive. 514 */ 515 #undef CONFIG_SYS_FLASH_EMPTY_INFO 516 #endif 517 518 /* I2C */ 519 #define CONFIG_SYS_I2C 520 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 521 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 522 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 523 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 524 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 525 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 526 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 527 528 #define I2C_PCA6408_BUS_NUM 1 529 #define I2C_PCA6408_ADDR 0x20 530 531 /* I2C bus multiplexer */ 532 #define I2C_MUX_CH_DEFAULT 0x8 533 534 /* 535 * RTC configuration 536 */ 537 #define RTC 538 #define CONFIG_RTC_DS1337 1 539 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 540 541 /* 542 * eSPI - Enhanced SPI 543 */ 544 #define CONFIG_SPI_FLASH_BAR 545 #define CONFIG_SF_DEFAULT_SPEED 10000000 546 #define CONFIG_SF_DEFAULT_MODE 0 547 548 /* 549 * General PCIe 550 * Memory space is mapped 1-1, but I/O space must start from 0. 551 */ 552 #define CONFIG_PCI /* Enable PCI/PCIE */ 553 #define CONFIG_PCIE1 /* PCIE controller 1 */ 554 #define CONFIG_PCIE2 /* PCIE controller 2 */ 555 #define CONFIG_PCIE3 /* PCIE controller 3 */ 556 #ifdef CONFIG_PPC_T1040 557 #define CONFIG_PCIE4 /* PCIE controller 4 */ 558 #endif 559 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 560 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 561 #define CONFIG_PCI_INDIRECT_BRIDGE 562 563 #ifdef CONFIG_PCI 564 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 565 #ifdef CONFIG_PCIE1 566 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 567 #ifdef CONFIG_PHYS_64BIT 568 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 569 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 570 #else 571 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 572 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 573 #endif 574 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 575 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 576 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 577 #ifdef CONFIG_PHYS_64BIT 578 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 579 #else 580 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 581 #endif 582 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 583 #endif 584 585 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 586 #ifdef CONFIG_PCIE2 587 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 590 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 591 #else 592 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 593 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 594 #endif 595 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 596 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 597 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 598 #ifdef CONFIG_PHYS_64BIT 599 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 600 #else 601 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 602 #endif 603 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 604 #endif 605 606 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 607 #ifdef CONFIG_PCIE3 608 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 609 #ifdef CONFIG_PHYS_64BIT 610 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 611 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 612 #else 613 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 614 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 615 #endif 616 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 617 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 618 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 621 #else 622 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 623 #endif 624 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 625 #endif 626 627 /* controller 4, Base address 203000, to be removed */ 628 #ifdef CONFIG_PCIE4 629 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 630 #ifdef CONFIG_PHYS_64BIT 631 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 632 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 633 #else 634 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 635 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 636 #endif 637 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 638 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 639 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 640 #ifdef CONFIG_PHYS_64BIT 641 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 642 #else 643 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 644 #endif 645 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 646 #endif 647 648 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 649 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 650 #define CONFIG_DOS_PARTITION 651 #endif /* CONFIG_PCI */ 652 653 /* 654 * USB 655 */ 656 #define CONFIG_HAS_FSL_DR_USB 657 658 #ifdef CONFIG_HAS_FSL_DR_USB 659 #define CONFIG_USB_EHCI 660 #define CONFIG_USB_EHCI_FSL 661 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 662 #endif 663 664 /* 665 * SDHC 666 */ 667 #define CONFIG_MMC 668 #ifdef CONFIG_MMC 669 #define CONFIG_FSL_ESDHC 670 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 671 #define CONFIG_GENERIC_MMC 672 #define CONFIG_DOS_PARTITION 673 #endif 674 675 /* Qman/Bman */ 676 #ifndef CONFIG_NOBQFMAN 677 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 678 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 679 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 680 #ifdef CONFIG_PHYS_64BIT 681 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 682 #else 683 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 684 #endif 685 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 686 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 687 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 688 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 689 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 690 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 691 CONFIG_SYS_BMAN_CENA_SIZE) 692 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 693 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 694 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 695 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 696 #ifdef CONFIG_PHYS_64BIT 697 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 698 #else 699 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 700 #endif 701 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 702 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 703 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 704 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 705 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 706 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 707 CONFIG_SYS_QMAN_CENA_SIZE) 708 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 709 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 710 711 #define CONFIG_SYS_DPAA_FMAN 712 713 #ifdef CONFIG_T1024RDB 714 #define CONFIG_QE 715 #define CONFIG_U_QE 716 #endif 717 /* Default address of microcode for the Linux FMan driver */ 718 #if defined(CONFIG_SPIFLASH) 719 /* 720 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 721 * env, so we got 0x110000. 722 */ 723 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 724 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 725 #define CONFIG_SYS_QE_FW_ADDR 0x130000 726 #elif defined(CONFIG_SDCARD) 727 /* 728 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 729 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 730 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 731 */ 732 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 733 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 734 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 735 #elif defined(CONFIG_NAND) 736 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 737 #if defined(CONFIG_T1024RDB) 738 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 739 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 740 #elif defined(CONFIG_T1023RDB) 741 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 742 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 743 #endif 744 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 745 /* 746 * Slave has no ucode locally, it can fetch this from remote. When implementing 747 * in two corenet boards, slave's ucode could be stored in master's memory 748 * space, the address can be mapped from slave TLB->slave LAW-> 749 * slave SRIO or PCIE outbound window->master inbound window-> 750 * master LAW->the ucode address in master's memory space. 751 */ 752 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 753 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 754 #else 755 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 756 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 757 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 758 #endif 759 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 760 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 761 #endif /* CONFIG_NOBQFMAN */ 762 763 #ifdef CONFIG_SYS_DPAA_FMAN 764 #define CONFIG_FMAN_ENET 765 #define CONFIG_PHYLIB_10G 766 #define CONFIG_PHY_REALTEK 767 #define CONFIG_PHY_AQUANTIA 768 #if defined(CONFIG_T1024RDB) 769 #define RGMII_PHY1_ADDR 0x2 770 #define RGMII_PHY2_ADDR 0x6 771 #define SGMII_AQR_PHY_ADDR 0x2 772 #define FM1_10GEC1_PHY_ADDR 0x1 773 #elif defined(CONFIG_T1023RDB) 774 #define RGMII_PHY1_ADDR 0x1 775 #define SGMII_RTK_PHY_ADDR 0x3 776 #define SGMII_AQR_PHY_ADDR 0x2 777 #endif 778 #endif 779 780 #ifdef CONFIG_FMAN_ENET 781 #define CONFIG_MII /* MII PHY management */ 782 #define CONFIG_ETHPRIME "FM1@DTSEC4" 783 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 784 #endif 785 786 /* 787 * Dynamic MTD Partition support with mtdparts 788 */ 789 #ifndef CONFIG_SYS_NO_FLASH 790 #define CONFIG_MTD_DEVICE 791 #define CONFIG_MTD_PARTITIONS 792 #define CONFIG_CMD_MTDPARTS 793 #define CONFIG_FLASH_CFI_MTD 794 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 795 "spi0=spife110000.1" 796 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 797 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 798 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 799 "1m(uboot),5m(kernel),128k(dtb),-(user)" 800 #endif 801 802 /* 803 * Environment 804 */ 805 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 806 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 807 808 /* 809 * Command line configuration. 810 */ 811 #define CONFIG_CMD_DATE 812 #define CONFIG_CMD_EEPROM 813 #define CONFIG_CMD_ERRATA 814 #define CONFIG_CMD_IRQ 815 #define CONFIG_CMD_REGINFO 816 817 #ifdef CONFIG_PCI 818 #define CONFIG_CMD_PCI 819 #endif 820 821 /* 822 * Miscellaneous configurable options 823 */ 824 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 825 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 826 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 827 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 828 #ifdef CONFIG_CMD_KGDB 829 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 830 #else 831 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 832 #endif 833 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 834 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 835 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 836 837 /* 838 * For booting Linux, the board info and command line data 839 * have to be in the first 64 MB of memory, since this is 840 * the maximum mapped by the Linux kernel during initialization. 841 */ 842 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 843 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 844 845 #ifdef CONFIG_CMD_KGDB 846 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 847 #endif 848 849 /* 850 * Environment Configuration 851 */ 852 #define CONFIG_ROOTPATH "/opt/nfsroot" 853 #define CONFIG_BOOTFILE "uImage" 854 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 855 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 856 #define CONFIG_BAUDRATE 115200 857 #define __USB_PHY_TYPE utmi 858 859 #ifdef CONFIG_PPC_T1024 860 #define CONFIG_BOARDNAME t1024rdb 861 #define BANK_INTLV cs0_cs1 862 #else 863 #define CONFIG_BOARDNAME t1023rdb 864 #define BANK_INTLV null 865 #endif 866 867 #define CONFIG_EXTRA_ENV_SETTINGS \ 868 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 869 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 870 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 871 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 872 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 873 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 874 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 875 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 876 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 877 "netdev=eth0\0" \ 878 "tftpflash=tftpboot $loadaddr $uboot && " \ 879 "protect off $ubootaddr +$filesize && " \ 880 "erase $ubootaddr +$filesize && " \ 881 "cp.b $loadaddr $ubootaddr $filesize && " \ 882 "protect on $ubootaddr +$filesize && " \ 883 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 884 "consoledev=ttyS0\0" \ 885 "ramdiskaddr=2000000\0" \ 886 "fdtaddr=1e00000\0" \ 887 "bdev=sda3\0" 888 889 #define CONFIG_LINUX \ 890 "setenv bootargs root=/dev/ram rw " \ 891 "console=$consoledev,$baudrate $othbootargs;" \ 892 "setenv ramdiskaddr 0x02000000;" \ 893 "setenv fdtaddr 0x00c00000;" \ 894 "setenv loadaddr 0x1000000;" \ 895 "bootm $loadaddr $ramdiskaddr $fdtaddr" 896 897 #define CONFIG_NFSBOOTCOMMAND \ 898 "setenv bootargs root=/dev/nfs rw " \ 899 "nfsroot=$serverip:$rootpath " \ 900 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 901 "console=$consoledev,$baudrate $othbootargs;" \ 902 "tftp $loadaddr $bootfile;" \ 903 "tftp $fdtaddr $fdtfile;" \ 904 "bootm $loadaddr - $fdtaddr" 905 906 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 907 908 /* Hash command with SHA acceleration supported in hardware */ 909 #ifdef CONFIG_FSL_CAAM 910 #define CONFIG_CMD_HASH 911 #define CONFIG_SHA_HW_ACCEL 912 #endif 913 914 #include <asm/fsl_secure_boot.h> 915 916 #endif /* __T1024RDB_H */ 917