1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 RDB board configuration file 8 */ 9 10 #ifndef __T1024RDB_H 11 #define __T1024RDB_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 /* support deep sleep */ 28 #ifdef CONFIG_ARCH_T1024 29 #define CONFIG_DEEP_SLEEP 30 #endif 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 #ifdef CONFIG_SPL_BUILD 41 #define CONFIG_SPL_SKIP_RELOCATE 42 #define CONFIG_SPL_COMMON_INIT_DDR 43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 44 #endif 45 46 #ifdef CONFIG_NAND 47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 52 #if defined(CONFIG_TARGET_T1024RDB) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 54 #elif defined(CONFIG_TARGET_T1023RDB) 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 56 #endif 57 #define CONFIG_SPL_NAND_BOOT 58 #endif 59 60 #ifdef CONFIG_SPIFLASH 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #if defined(CONFIG_TARGET_T1024RDB) 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 73 #elif defined(CONFIG_TARGET_T1023RDB) 74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 75 #endif 76 #define CONFIG_SPL_SPI_BOOT 77 #endif 78 79 #ifdef CONFIG_SDCARD 80 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 81 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #if defined(CONFIG_TARGET_T1024RDB) 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 91 #elif defined(CONFIG_TARGET_T1023RDB) 92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 93 #endif 94 #define CONFIG_SPL_MMC_BOOT 95 #endif 96 97 #endif /* CONFIG_RAMBOOT_PBL */ 98 99 #ifndef CONFIG_RESET_VECTOR_ADDRESS 100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 101 #endif 102 103 /* PCIe Boot - Master */ 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER 105 /* 106 * for slave u-boot IMAGE instored in master memory space, 107 * PHYS must be aligned based on the SIZE 108 */ 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 111 #ifdef CONFIG_PHYS_64BIT 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 114 #else 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 117 #endif 118 /* 119 * for slave UCODE and ENV instored in master memory space, 120 * PHYS must be aligned based on the SIZE 121 */ 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 125 #else 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 128 #endif 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 130 /* slave core release by master*/ 131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 133 134 /* PCIe Boot - Slave */ 135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 139 /* Set 1M boot space for PCIe boot */ 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 10000000 150 #define CONFIG_ENV_SPI_MODE 0 151 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 152 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 153 #if defined(CONFIG_TARGET_T1024RDB) 154 #define CONFIG_ENV_SECT_SIZE 0x10000 155 #elif defined(CONFIG_TARGET_T1023RDB) 156 #define CONFIG_ENV_SECT_SIZE 0x40000 157 #endif 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_MMC_ENV_DEV 0 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_OFFSET (512 * 0x800) 162 #elif defined(CONFIG_NAND) 163 #define CONFIG_ENV_SIZE 0x2000 164 #if defined(CONFIG_TARGET_T1024RDB) 165 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 166 #elif defined(CONFIG_TARGET_T1023RDB) 167 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 168 #endif 169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 170 #define CONFIG_ENV_ADDR 0xffe20000 171 #define CONFIG_ENV_SIZE 0x2000 172 #elif defined(CONFIG_ENV_IS_NOWHERE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #else 175 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 178 #endif 179 180 #ifndef __ASSEMBLY__ 181 unsigned long get_board_sys_clk(void); 182 unsigned long get_board_ddr_clk(void); 183 #endif 184 185 #define CONFIG_SYS_CLK_FREQ 100000000 186 #define CONFIG_DDR_CLK_FREQ 100000000 187 188 /* 189 * These can be toggled for performance analysis, otherwise use default. 190 */ 191 #define CONFIG_SYS_CACHE_STASHING 192 #define CONFIG_BACKSIDE_L2_CACHE 193 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 194 #define CONFIG_BTB /* toggle branch predition */ 195 #define CONFIG_DDR_ECC 196 #ifdef CONFIG_DDR_ECC 197 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 198 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 199 #endif 200 201 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 202 #define CONFIG_SYS_MEMTEST_END 0x00400000 203 204 /* 205 * Config the L3 Cache as L3 SRAM 206 */ 207 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 208 #define CONFIG_SYS_L3_SIZE (256 << 10) 209 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 210 #ifdef CONFIG_RAMBOOT_PBL 211 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 212 #endif 213 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 214 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 215 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 216 217 #ifdef CONFIG_PHYS_64BIT 218 #define CONFIG_SYS_DCSRBAR 0xf0000000 219 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 220 #endif 221 222 /* EEPROM */ 223 #define CONFIG_ID_EEPROM 224 #define CONFIG_SYS_I2C_EEPROM_NXID 225 #define CONFIG_SYS_EEPROM_BUS_NUM 0 226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 230 231 /* 232 * DDR Setup 233 */ 234 #define CONFIG_VERY_BIG_RAM 235 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 236 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 237 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 238 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 239 #define CONFIG_FSL_DDR_INTERACTIVE 240 #if defined(CONFIG_TARGET_T1024RDB) 241 #define CONFIG_DDR_SPD 242 #define CONFIG_SYS_SPD_BUS_NUM 0 243 #define SPD_EEPROM_ADDRESS 0x51 244 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 245 #elif defined(CONFIG_TARGET_T1023RDB) 246 #define CONFIG_SYS_DDR_RAW_TIMING 247 #define CONFIG_SYS_SDRAM_SIZE 2048 248 #endif 249 250 /* 251 * IFC Definitions 252 */ 253 #define CONFIG_SYS_FLASH_BASE 0xe8000000 254 #ifdef CONFIG_PHYS_64BIT 255 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 256 #else 257 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 258 #endif 259 260 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 261 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 262 CSPR_PORT_SIZE_16 | \ 263 CSPR_MSEL_NOR | \ 264 CSPR_V) 265 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 266 267 /* NOR Flash Timing Params */ 268 #if defined(CONFIG_TARGET_T1024RDB) 269 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 270 #elif defined(CONFIG_TARGET_T1023RDB) 271 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 272 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 273 #endif 274 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 275 FTIM0_NOR_TEADC(0x5) | \ 276 FTIM0_NOR_TEAHC(0x5)) 277 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 278 FTIM1_NOR_TRAD_NOR(0x1A) |\ 279 FTIM1_NOR_TSEQRAD_NOR(0x13)) 280 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 281 FTIM2_NOR_TCH(0x4) | \ 282 FTIM2_NOR_TWPH(0x0E) | \ 283 FTIM2_NOR_TWP(0x1c)) 284 #define CONFIG_SYS_NOR_FTIM3 0x0 285 286 #define CONFIG_SYS_FLASH_QUIET_TEST 287 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 288 289 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 290 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 291 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 292 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 293 294 #define CONFIG_SYS_FLASH_EMPTY_INFO 295 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 296 297 #ifdef CONFIG_TARGET_T1024RDB 298 /* CPLD on IFC */ 299 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 300 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 301 #define CONFIG_SYS_CSPR2_EXT (0xf) 302 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 303 | CSPR_PORT_SIZE_8 \ 304 | CSPR_MSEL_GPCM \ 305 | CSPR_V) 306 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 307 #define CONFIG_SYS_CSOR2 0x0 308 309 /* CPLD Timing parameters for IFC CS2 */ 310 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 311 FTIM0_GPCM_TEADC(0x0e) | \ 312 FTIM0_GPCM_TEAHC(0x0e)) 313 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 314 FTIM1_GPCM_TRAD(0x1f)) 315 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 316 FTIM2_GPCM_TCH(0x8) | \ 317 FTIM2_GPCM_TWP(0x1f)) 318 #define CONFIG_SYS_CS2_FTIM3 0x0 319 #endif 320 321 /* NAND Flash on IFC */ 322 #define CONFIG_NAND_FSL_IFC 323 #define CONFIG_SYS_NAND_BASE 0xff800000 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 326 #else 327 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 328 #endif 329 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 330 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 331 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 332 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 333 | CSPR_V) 334 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 335 336 #if defined(CONFIG_TARGET_T1024RDB) 337 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 338 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 339 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 340 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 341 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 342 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 343 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 344 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 345 #elif defined(CONFIG_TARGET_T1023RDB) 346 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 347 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 348 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 349 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 350 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 351 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 352 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 353 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 354 #endif 355 356 #define CONFIG_SYS_NAND_ONFI_DETECTION 357 /* ONFI NAND Flash mode0 Timing Params */ 358 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 359 FTIM0_NAND_TWP(0x18) | \ 360 FTIM0_NAND_TWCHT(0x07) | \ 361 FTIM0_NAND_TWH(0x0a)) 362 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 363 FTIM1_NAND_TWBE(0x39) | \ 364 FTIM1_NAND_TRR(0x0e) | \ 365 FTIM1_NAND_TRP(0x18)) 366 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 367 FTIM2_NAND_TREH(0x0a) | \ 368 FTIM2_NAND_TWHRE(0x1e)) 369 #define CONFIG_SYS_NAND_FTIM3 0x0 370 371 #define CONFIG_SYS_NAND_DDR_LAW 11 372 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 373 #define CONFIG_SYS_MAX_NAND_DEVICE 1 374 375 #if defined(CONFIG_NAND) 376 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 377 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 378 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 379 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 380 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 381 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 382 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 383 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 384 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 385 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 386 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 387 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 388 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 389 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 390 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 391 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 392 #else 393 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 394 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 395 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 396 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 397 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 398 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 399 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 400 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 401 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 402 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 403 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 404 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 405 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 406 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 407 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 408 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 409 #endif 410 411 #ifdef CONFIG_SPL_BUILD 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 413 #else 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 415 #endif 416 417 #if defined(CONFIG_RAMBOOT_PBL) 418 #define CONFIG_SYS_RAMBOOT 419 #endif 420 421 #define CONFIG_HWCONFIG 422 423 /* define to use L1 as initial stack */ 424 #define CONFIG_L1_INIT_RAM 425 #define CONFIG_SYS_INIT_RAM_LOCK 426 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 430 /* The assembler doesn't like typecast */ 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 432 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 433 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 434 #else 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 438 #endif 439 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 440 441 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 442 GENERATED_GBL_DATA_SIZE) 443 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 444 445 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 446 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 447 448 /* Serial Port */ 449 #define CONFIG_SYS_NS16550_SERIAL 450 #define CONFIG_SYS_NS16550_REG_SIZE 1 451 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 452 453 #define CONFIG_SYS_BAUDRATE_TABLE \ 454 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 455 456 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 457 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 458 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 459 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 460 461 /* Video */ 462 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 463 #ifdef CONFIG_FSL_DIU_FB 464 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 465 #define CONFIG_VIDEO_LOGO 466 #define CONFIG_VIDEO_BMP_LOGO 467 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 468 /* 469 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 470 * disable empty flash sector detection, which is I/O-intensive. 471 */ 472 #undef CONFIG_SYS_FLASH_EMPTY_INFO 473 #endif 474 475 /* I2C */ 476 #define CONFIG_SYS_I2C 477 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 478 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 479 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 480 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 481 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 482 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 483 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 484 485 #define I2C_PCA6408_BUS_NUM 1 486 #define I2C_PCA6408_ADDR 0x20 487 488 /* I2C bus multiplexer */ 489 #define I2C_MUX_CH_DEFAULT 0x8 490 491 /* 492 * RTC configuration 493 */ 494 #define RTC 495 #define CONFIG_RTC_DS1337 1 496 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 497 498 /* 499 * eSPI - Enhanced SPI 500 */ 501 #define CONFIG_SPI_FLASH_BAR 502 #define CONFIG_SF_DEFAULT_SPEED 10000000 503 #define CONFIG_SF_DEFAULT_MODE 0 504 505 /* 506 * General PCIe 507 * Memory space is mapped 1-1, but I/O space must start from 0. 508 */ 509 #define CONFIG_PCIE1 /* PCIE controller 1 */ 510 #define CONFIG_PCIE2 /* PCIE controller 2 */ 511 #define CONFIG_PCIE3 /* PCIE controller 3 */ 512 #ifdef CONFIG_ARCH_T1040 513 #define CONFIG_PCIE4 /* PCIE controller 4 */ 514 #endif 515 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 516 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 517 #define CONFIG_PCI_INDIRECT_BRIDGE 518 519 #ifdef CONFIG_PCI 520 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 521 #ifdef CONFIG_PCIE1 522 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 523 #ifdef CONFIG_PHYS_64BIT 524 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 526 #else 527 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 528 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 529 #endif 530 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 531 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 532 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 533 #ifdef CONFIG_PHYS_64BIT 534 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 535 #else 536 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 537 #endif 538 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 539 #endif 540 541 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 542 #ifdef CONFIG_PCIE2 543 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 544 #ifdef CONFIG_PHYS_64BIT 545 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 546 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 547 #else 548 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 549 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 550 #endif 551 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 552 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 553 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 554 #ifdef CONFIG_PHYS_64BIT 555 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 556 #else 557 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 558 #endif 559 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 560 #endif 561 562 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 563 #ifdef CONFIG_PCIE3 564 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 565 #ifdef CONFIG_PHYS_64BIT 566 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 568 #else 569 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 570 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 571 #endif 572 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 573 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 574 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 575 #ifdef CONFIG_PHYS_64BIT 576 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 577 #else 578 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 579 #endif 580 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 581 #endif 582 583 /* controller 4, Base address 203000, to be removed */ 584 #ifdef CONFIG_PCIE4 585 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 586 #ifdef CONFIG_PHYS_64BIT 587 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 588 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 589 #else 590 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 591 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 592 #endif 593 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 594 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 595 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 596 #ifdef CONFIG_PHYS_64BIT 597 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 598 #else 599 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 600 #endif 601 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 602 #endif 603 604 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 605 #endif /* CONFIG_PCI */ 606 607 /* 608 * USB 609 */ 610 #define CONFIG_HAS_FSL_DR_USB 611 612 #ifdef CONFIG_HAS_FSL_DR_USB 613 #define CONFIG_USB_EHCI_FSL 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 615 #endif 616 617 /* 618 * SDHC 619 */ 620 #ifdef CONFIG_MMC 621 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 622 #endif 623 624 /* Qman/Bman */ 625 #ifndef CONFIG_NOBQFMAN 626 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 627 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 628 #ifdef CONFIG_PHYS_64BIT 629 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 630 #else 631 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 632 #endif 633 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 634 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 635 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 636 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 637 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 638 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 639 CONFIG_SYS_BMAN_CENA_SIZE) 640 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 642 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 643 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 644 #ifdef CONFIG_PHYS_64BIT 645 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 646 #else 647 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 648 #endif 649 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 650 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 651 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 652 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 653 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 654 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 655 CONFIG_SYS_QMAN_CENA_SIZE) 656 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 657 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 658 659 #define CONFIG_SYS_DPAA_FMAN 660 661 #ifdef CONFIG_TARGET_T1024RDB 662 #define CONFIG_QE 663 #endif 664 /* Default address of microcode for the Linux FMan driver */ 665 #if defined(CONFIG_SPIFLASH) 666 /* 667 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 668 * env, so we got 0x110000. 669 */ 670 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 671 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 672 #define CONFIG_SYS_QE_FW_ADDR 0x130000 673 #elif defined(CONFIG_SDCARD) 674 /* 675 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 676 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 677 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 678 */ 679 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 680 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 681 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 682 #elif defined(CONFIG_NAND) 683 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 684 #if defined(CONFIG_TARGET_T1024RDB) 685 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 686 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 687 #elif defined(CONFIG_TARGET_T1023RDB) 688 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 689 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 690 #endif 691 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 692 /* 693 * Slave has no ucode locally, it can fetch this from remote. When implementing 694 * in two corenet boards, slave's ucode could be stored in master's memory 695 * space, the address can be mapped from slave TLB->slave LAW-> 696 * slave SRIO or PCIE outbound window->master inbound window-> 697 * master LAW->the ucode address in master's memory space. 698 */ 699 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 700 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 701 #else 702 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 703 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 704 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 705 #endif 706 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 707 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 708 #endif /* CONFIG_NOBQFMAN */ 709 710 #ifdef CONFIG_SYS_DPAA_FMAN 711 #define CONFIG_FMAN_ENET 712 #define CONFIG_PHY_REALTEK 713 #if defined(CONFIG_TARGET_T1024RDB) 714 #define RGMII_PHY1_ADDR 0x2 715 #define RGMII_PHY2_ADDR 0x6 716 #define SGMII_AQR_PHY_ADDR 0x2 717 #define FM1_10GEC1_PHY_ADDR 0x1 718 #elif defined(CONFIG_TARGET_T1023RDB) 719 #define RGMII_PHY1_ADDR 0x1 720 #define SGMII_RTK_PHY_ADDR 0x3 721 #define SGMII_AQR_PHY_ADDR 0x2 722 #endif 723 #endif 724 725 #ifdef CONFIG_FMAN_ENET 726 #define CONFIG_ETHPRIME "FM1@DTSEC4" 727 #endif 728 729 /* 730 * Dynamic MTD Partition support with mtdparts 731 */ 732 733 /* 734 * Environment 735 */ 736 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 737 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 738 739 /* 740 * Miscellaneous configurable options 741 */ 742 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 743 744 /* 745 * For booting Linux, the board info and command line data 746 * have to be in the first 64 MB of memory, since this is 747 * the maximum mapped by the Linux kernel during initialization. 748 */ 749 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 750 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 751 752 #ifdef CONFIG_CMD_KGDB 753 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 754 #endif 755 756 /* 757 * Environment Configuration 758 */ 759 #define CONFIG_ROOTPATH "/opt/nfsroot" 760 #define CONFIG_BOOTFILE "uImage" 761 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 762 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 763 #define __USB_PHY_TYPE utmi 764 765 #ifdef CONFIG_ARCH_T1024 766 #define CONFIG_BOARDNAME t1024rdb 767 #define BANK_INTLV cs0_cs1 768 #else 769 #define CONFIG_BOARDNAME t1023rdb 770 #define BANK_INTLV null 771 #endif 772 773 #define CONFIG_EXTRA_ENV_SETTINGS \ 774 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 775 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 776 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 777 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 778 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 779 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 780 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 781 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 782 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 783 "netdev=eth0\0" \ 784 "tftpflash=tftpboot $loadaddr $uboot && " \ 785 "protect off $ubootaddr +$filesize && " \ 786 "erase $ubootaddr +$filesize && " \ 787 "cp.b $loadaddr $ubootaddr $filesize && " \ 788 "protect on $ubootaddr +$filesize && " \ 789 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 790 "consoledev=ttyS0\0" \ 791 "ramdiskaddr=2000000\0" \ 792 "fdtaddr=1e00000\0" \ 793 "bdev=sda3\0" 794 795 #define CONFIG_LINUX \ 796 "setenv bootargs root=/dev/ram rw " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "setenv ramdiskaddr 0x02000000;" \ 799 "setenv fdtaddr 0x00c00000;" \ 800 "setenv loadaddr 0x1000000;" \ 801 "bootm $loadaddr $ramdiskaddr $fdtaddr" 802 803 #define CONFIG_NFSBOOTCOMMAND \ 804 "setenv bootargs root=/dev/nfs rw " \ 805 "nfsroot=$serverip:$rootpath " \ 806 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 807 "console=$consoledev,$baudrate $othbootargs;" \ 808 "tftp $loadaddr $bootfile;" \ 809 "tftp $fdtaddr $fdtfile;" \ 810 "bootm $loadaddr - $fdtaddr" 811 812 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 813 814 #include <asm/fsl_secure_boot.h> 815 816 #endif /* __T1024RDB_H */ 817