1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 /* support deep sleep */ 30 #ifdef CONFIG_ARCH_T1024 31 #define CONFIG_DEEP_SLEEP 32 #endif 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x30001000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #if defined(CONFIG_TARGET_T1024RDB) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 58 #elif defined(CONFIG_TARGET_T1023RDB) 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 60 #endif 61 #define CONFIG_SPL_NAND_BOOT 62 #endif 63 64 #ifdef CONFIG_SPIFLASH 65 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 72 #ifndef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #endif 75 #if defined(CONFIG_TARGET_T1024RDB) 76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 77 #elif defined(CONFIG_TARGET_T1023RDB) 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 79 #endif 80 #define CONFIG_SPL_SPI_BOOT 81 #endif 82 83 #ifdef CONFIG_SDCARD 84 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 85 #define CONFIG_SPL_MMC_MINIMAL 86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #if defined(CONFIG_TARGET_T1024RDB) 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 96 #elif defined(CONFIG_TARGET_T1023RDB) 97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 98 #endif 99 #define CONFIG_SPL_MMC_BOOT 100 #endif 101 102 #endif /* CONFIG_RAMBOOT_PBL */ 103 104 #ifndef CONFIG_SYS_TEXT_BASE 105 #define CONFIG_SYS_TEXT_BASE 0xeff40000 106 #endif 107 108 #ifndef CONFIG_RESET_VECTOR_ADDRESS 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 110 #endif 111 112 #ifdef CONFIG_MTD_NOR_FLASH 113 #define CONFIG_FLASH_CFI_DRIVER 114 #define CONFIG_SYS_FLASH_CFI 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 116 #endif 117 118 /* PCIe Boot - Master */ 119 #define CONFIG_SRIO_PCIE_BOOT_MASTER 120 /* 121 * for slave u-boot IMAGE instored in master memory space, 122 * PHYS must be aligned based on the SIZE 123 */ 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 129 #else 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 132 #endif 133 /* 134 * for slave UCODE and ENV instored in master memory space, 135 * PHYS must be aligned based on the SIZE 136 */ 137 #ifdef CONFIG_PHYS_64BIT 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 140 #else 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 143 #endif 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 145 /* slave core release by master*/ 146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 148 149 /* PCIe Boot - Slave */ 150 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 154 /* Set 1M boot space for PCIe boot */ 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 159 #endif 160 161 #if defined(CONFIG_SPIFLASH) 162 #define CONFIG_SYS_EXTRA_ENV_RELOC 163 #define CONFIG_ENV_SPI_BUS 0 164 #define CONFIG_ENV_SPI_CS 0 165 #define CONFIG_ENV_SPI_MAX_HZ 10000000 166 #define CONFIG_ENV_SPI_MODE 0 167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 169 #if defined(CONFIG_TARGET_T1024RDB) 170 #define CONFIG_ENV_SECT_SIZE 0x10000 171 #elif defined(CONFIG_TARGET_T1023RDB) 172 #define CONFIG_ENV_SECT_SIZE 0x40000 173 #endif 174 #elif defined(CONFIG_SDCARD) 175 #define CONFIG_SYS_EXTRA_ENV_RELOC 176 #define CONFIG_SYS_MMC_ENV_DEV 0 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_OFFSET (512 * 0x800) 179 #elif defined(CONFIG_NAND) 180 #define CONFIG_SYS_EXTRA_ENV_RELOC 181 #define CONFIG_ENV_SIZE 0x2000 182 #if defined(CONFIG_TARGET_T1024RDB) 183 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 184 #elif defined(CONFIG_TARGET_T1023RDB) 185 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 186 #endif 187 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 188 #define CONFIG_ENV_ADDR 0xffe20000 189 #define CONFIG_ENV_SIZE 0x2000 190 #elif defined(CONFIG_ENV_IS_NOWHERE) 191 #define CONFIG_ENV_SIZE 0x2000 192 #else 193 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 194 #define CONFIG_ENV_SIZE 0x2000 195 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 196 #endif 197 198 #ifndef __ASSEMBLY__ 199 unsigned long get_board_sys_clk(void); 200 unsigned long get_board_ddr_clk(void); 201 #endif 202 203 #define CONFIG_SYS_CLK_FREQ 100000000 204 #define CONFIG_DDR_CLK_FREQ 100000000 205 206 /* 207 * These can be toggled for performance analysis, otherwise use default. 208 */ 209 #define CONFIG_SYS_CACHE_STASHING 210 #define CONFIG_BACKSIDE_L2_CACHE 211 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 212 #define CONFIG_BTB /* toggle branch predition */ 213 #define CONFIG_DDR_ECC 214 #ifdef CONFIG_DDR_ECC 215 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 216 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 217 #endif 218 219 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 220 #define CONFIG_SYS_MEMTEST_END 0x00400000 221 #define CONFIG_SYS_ALT_MEMTEST 222 223 /* 224 * Config the L3 Cache as L3 SRAM 225 */ 226 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 227 #define CONFIG_SYS_L3_SIZE (256 << 10) 228 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 229 #ifdef CONFIG_RAMBOOT_PBL 230 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 231 #endif 232 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 233 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 234 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 235 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 236 237 #ifdef CONFIG_PHYS_64BIT 238 #define CONFIG_SYS_DCSRBAR 0xf0000000 239 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 240 #endif 241 242 /* EEPROM */ 243 #define CONFIG_ID_EEPROM 244 #define CONFIG_SYS_I2C_EEPROM_NXID 245 #define CONFIG_SYS_EEPROM_BUS_NUM 0 246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 250 251 /* 252 * DDR Setup 253 */ 254 #define CONFIG_VERY_BIG_RAM 255 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 256 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 257 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 258 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 259 #define CONFIG_FSL_DDR_INTERACTIVE 260 #if defined(CONFIG_TARGET_T1024RDB) 261 #define CONFIG_DDR_SPD 262 #define CONFIG_SYS_SPD_BUS_NUM 0 263 #define SPD_EEPROM_ADDRESS 0x51 264 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 265 #elif defined(CONFIG_TARGET_T1023RDB) 266 #define CONFIG_SYS_DDR_RAW_TIMING 267 #define CONFIG_SYS_SDRAM_SIZE 2048 268 #endif 269 270 /* 271 * IFC Definitions 272 */ 273 #define CONFIG_SYS_FLASH_BASE 0xe8000000 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 276 #else 277 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 278 #endif 279 280 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 281 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 282 CSPR_PORT_SIZE_16 | \ 283 CSPR_MSEL_NOR | \ 284 CSPR_V) 285 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 286 287 /* NOR Flash Timing Params */ 288 #if defined(CONFIG_TARGET_T1024RDB) 289 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 290 #elif defined(CONFIG_TARGET_T1023RDB) 291 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 292 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 293 #endif 294 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 295 FTIM0_NOR_TEADC(0x5) | \ 296 FTIM0_NOR_TEAHC(0x5)) 297 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 298 FTIM1_NOR_TRAD_NOR(0x1A) |\ 299 FTIM1_NOR_TSEQRAD_NOR(0x13)) 300 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 301 FTIM2_NOR_TCH(0x4) | \ 302 FTIM2_NOR_TWPH(0x0E) | \ 303 FTIM2_NOR_TWP(0x1c)) 304 #define CONFIG_SYS_NOR_FTIM3 0x0 305 306 #define CONFIG_SYS_FLASH_QUIET_TEST 307 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 308 309 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 310 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 311 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 312 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 313 314 #define CONFIG_SYS_FLASH_EMPTY_INFO 315 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 316 317 #ifdef CONFIG_TARGET_T1024RDB 318 /* CPLD on IFC */ 319 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 320 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 321 #define CONFIG_SYS_CSPR2_EXT (0xf) 322 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 323 | CSPR_PORT_SIZE_8 \ 324 | CSPR_MSEL_GPCM \ 325 | CSPR_V) 326 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 327 #define CONFIG_SYS_CSOR2 0x0 328 329 /* CPLD Timing parameters for IFC CS2 */ 330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 331 FTIM0_GPCM_TEADC(0x0e) | \ 332 FTIM0_GPCM_TEAHC(0x0e)) 333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 334 FTIM1_GPCM_TRAD(0x1f)) 335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 336 FTIM2_GPCM_TCH(0x8) | \ 337 FTIM2_GPCM_TWP(0x1f)) 338 #define CONFIG_SYS_CS2_FTIM3 0x0 339 #endif 340 341 /* NAND Flash on IFC */ 342 #define CONFIG_NAND_FSL_IFC 343 #define CONFIG_SYS_NAND_BASE 0xff800000 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 346 #else 347 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 348 #endif 349 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 350 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 351 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 352 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 353 | CSPR_V) 354 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 355 356 #if defined(CONFIG_TARGET_T1024RDB) 357 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 358 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 359 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 360 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 361 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 362 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 363 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 364 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 365 #elif defined(CONFIG_TARGET_T1023RDB) 366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 369 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 370 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 371 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 372 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 373 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 374 #endif 375 376 #define CONFIG_SYS_NAND_ONFI_DETECTION 377 /* ONFI NAND Flash mode0 Timing Params */ 378 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 379 FTIM0_NAND_TWP(0x18) | \ 380 FTIM0_NAND_TWCHT(0x07) | \ 381 FTIM0_NAND_TWH(0x0a)) 382 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 383 FTIM1_NAND_TWBE(0x39) | \ 384 FTIM1_NAND_TRR(0x0e) | \ 385 FTIM1_NAND_TRP(0x18)) 386 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 387 FTIM2_NAND_TREH(0x0a) | \ 388 FTIM2_NAND_TWHRE(0x1e)) 389 #define CONFIG_SYS_NAND_FTIM3 0x0 390 391 #define CONFIG_SYS_NAND_DDR_LAW 11 392 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 393 #define CONFIG_SYS_MAX_NAND_DEVICE 1 394 395 #if defined(CONFIG_NAND) 396 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 397 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 398 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 399 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 400 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 401 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 402 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 403 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 404 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 405 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 406 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 407 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 408 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 409 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 410 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 411 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 412 #else 413 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 414 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 415 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 416 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 417 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 418 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 419 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 420 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 421 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 429 #endif 430 431 #ifdef CONFIG_SPL_BUILD 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 433 #else 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 435 #endif 436 437 #if defined(CONFIG_RAMBOOT_PBL) 438 #define CONFIG_SYS_RAMBOOT 439 #endif 440 441 #define CONFIG_BOARD_EARLY_INIT_R 442 #define CONFIG_MISC_INIT_R 443 444 #define CONFIG_HWCONFIG 445 446 /* define to use L1 as initial stack */ 447 #define CONFIG_L1_INIT_RAM 448 #define CONFIG_SYS_INIT_RAM_LOCK 449 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 453 /* The assembler doesn't like typecast */ 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 455 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 456 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 457 #else 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 461 #endif 462 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 463 464 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 465 GENERATED_GBL_DATA_SIZE) 466 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 467 468 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 469 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 470 471 /* Serial Port */ 472 #define CONFIG_CONS_INDEX 1 473 #define CONFIG_SYS_NS16550_SERIAL 474 #define CONFIG_SYS_NS16550_REG_SIZE 1 475 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 476 477 #define CONFIG_SYS_BAUDRATE_TABLE \ 478 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 479 480 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 481 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 482 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 483 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 484 485 /* Video */ 486 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 487 #ifdef CONFIG_FSL_DIU_FB 488 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 489 #define CONFIG_VIDEO_LOGO 490 #define CONFIG_VIDEO_BMP_LOGO 491 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 492 /* 493 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 494 * disable empty flash sector detection, which is I/O-intensive. 495 */ 496 #undef CONFIG_SYS_FLASH_EMPTY_INFO 497 #endif 498 499 /* I2C */ 500 #define CONFIG_SYS_I2C 501 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 502 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 503 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 504 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 505 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 506 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 507 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 508 509 #define I2C_PCA6408_BUS_NUM 1 510 #define I2C_PCA6408_ADDR 0x20 511 512 /* I2C bus multiplexer */ 513 #define I2C_MUX_CH_DEFAULT 0x8 514 515 /* 516 * RTC configuration 517 */ 518 #define RTC 519 #define CONFIG_RTC_DS1337 1 520 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 521 522 /* 523 * eSPI - Enhanced SPI 524 */ 525 #define CONFIG_SPI_FLASH_BAR 526 #define CONFIG_SF_DEFAULT_SPEED 10000000 527 #define CONFIG_SF_DEFAULT_MODE 0 528 529 /* 530 * General PCIe 531 * Memory space is mapped 1-1, but I/O space must start from 0. 532 */ 533 #define CONFIG_PCIE1 /* PCIE controller 1 */ 534 #define CONFIG_PCIE2 /* PCIE controller 2 */ 535 #define CONFIG_PCIE3 /* PCIE controller 3 */ 536 #ifdef CONFIG_ARCH_T1040 537 #define CONFIG_PCIE4 /* PCIE controller 4 */ 538 #endif 539 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 540 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 541 #define CONFIG_PCI_INDIRECT_BRIDGE 542 543 #ifdef CONFIG_PCI 544 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 545 #ifdef CONFIG_PCIE1 546 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 547 #ifdef CONFIG_PHYS_64BIT 548 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 549 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 550 #else 551 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 552 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 553 #endif 554 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 555 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 556 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 557 #ifdef CONFIG_PHYS_64BIT 558 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 559 #else 560 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 561 #endif 562 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 563 #endif 564 565 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 566 #ifdef CONFIG_PCIE2 567 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 571 #else 572 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 573 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 574 #endif 575 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 576 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 577 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 580 #else 581 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 582 #endif 583 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 587 #ifdef CONFIG_PCIE3 588 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 592 #else 593 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 594 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 595 #endif 596 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 598 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 601 #else 602 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 603 #endif 604 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 /* controller 4, Base address 203000, to be removed */ 608 #ifdef CONFIG_PCIE4 609 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 612 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 613 #else 614 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 615 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 616 #endif 617 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 618 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 619 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 622 #else 623 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 624 #endif 625 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 626 #endif 627 628 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 629 #endif /* CONFIG_PCI */ 630 631 /* 632 * USB 633 */ 634 #define CONFIG_HAS_FSL_DR_USB 635 636 #ifdef CONFIG_HAS_FSL_DR_USB 637 #define CONFIG_USB_EHCI_FSL 638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 639 #endif 640 641 /* 642 * SDHC 643 */ 644 #ifdef CONFIG_MMC 645 #define CONFIG_FSL_ESDHC 646 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 647 #endif 648 649 /* Qman/Bman */ 650 #ifndef CONFIG_NOBQFMAN 651 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 652 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 653 #ifdef CONFIG_PHYS_64BIT 654 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 655 #else 656 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 657 #endif 658 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 659 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 660 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 661 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 662 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 663 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 664 CONFIG_SYS_BMAN_CENA_SIZE) 665 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 666 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 667 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 668 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 669 #ifdef CONFIG_PHYS_64BIT 670 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 671 #else 672 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 673 #endif 674 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 675 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 676 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 677 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 678 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 679 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 680 CONFIG_SYS_QMAN_CENA_SIZE) 681 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 682 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 683 684 #define CONFIG_SYS_DPAA_FMAN 685 686 #ifdef CONFIG_TARGET_T1024RDB 687 #define CONFIG_QE 688 #define CONFIG_U_QE 689 #endif 690 /* Default address of microcode for the Linux FMan driver */ 691 #if defined(CONFIG_SPIFLASH) 692 /* 693 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 694 * env, so we got 0x110000. 695 */ 696 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 697 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 698 #define CONFIG_SYS_QE_FW_ADDR 0x130000 699 #elif defined(CONFIG_SDCARD) 700 /* 701 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 702 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 703 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 704 */ 705 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 706 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 707 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 708 #elif defined(CONFIG_NAND) 709 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 710 #if defined(CONFIG_TARGET_T1024RDB) 711 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 712 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 713 #elif defined(CONFIG_TARGET_T1023RDB) 714 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 715 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 716 #endif 717 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 718 /* 719 * Slave has no ucode locally, it can fetch this from remote. When implementing 720 * in two corenet boards, slave's ucode could be stored in master's memory 721 * space, the address can be mapped from slave TLB->slave LAW-> 722 * slave SRIO or PCIE outbound window->master inbound window-> 723 * master LAW->the ucode address in master's memory space. 724 */ 725 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 726 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 727 #else 728 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 729 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 730 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 731 #endif 732 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 733 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 734 #endif /* CONFIG_NOBQFMAN */ 735 736 #ifdef CONFIG_SYS_DPAA_FMAN 737 #define CONFIG_FMAN_ENET 738 #define CONFIG_PHYLIB_10G 739 #define CONFIG_PHY_REALTEK 740 #define CONFIG_PHY_AQUANTIA 741 #if defined(CONFIG_TARGET_T1024RDB) 742 #define RGMII_PHY1_ADDR 0x2 743 #define RGMII_PHY2_ADDR 0x6 744 #define SGMII_AQR_PHY_ADDR 0x2 745 #define FM1_10GEC1_PHY_ADDR 0x1 746 #elif defined(CONFIG_TARGET_T1023RDB) 747 #define RGMII_PHY1_ADDR 0x1 748 #define SGMII_RTK_PHY_ADDR 0x3 749 #define SGMII_AQR_PHY_ADDR 0x2 750 #endif 751 #endif 752 753 #ifdef CONFIG_FMAN_ENET 754 #define CONFIG_MII /* MII PHY management */ 755 #define CONFIG_ETHPRIME "FM1@DTSEC4" 756 #endif 757 758 /* 759 * Dynamic MTD Partition support with mtdparts 760 */ 761 #ifdef CONFIG_MTD_NOR_FLASH 762 #define CONFIG_MTD_DEVICE 763 #define CONFIG_MTD_PARTITIONS 764 #define CONFIG_FLASH_CFI_MTD 765 #endif 766 767 /* 768 * Environment 769 */ 770 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 771 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 772 773 /* 774 * Miscellaneous configurable options 775 */ 776 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 777 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 778 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 779 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 780 781 /* 782 * For booting Linux, the board info and command line data 783 * have to be in the first 64 MB of memory, since this is 784 * the maximum mapped by the Linux kernel during initialization. 785 */ 786 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 787 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 788 789 #ifdef CONFIG_CMD_KGDB 790 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 791 #endif 792 793 /* 794 * Environment Configuration 795 */ 796 #define CONFIG_ROOTPATH "/opt/nfsroot" 797 #define CONFIG_BOOTFILE "uImage" 798 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 799 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 800 #define __USB_PHY_TYPE utmi 801 802 #ifdef CONFIG_ARCH_T1024 803 #define CONFIG_BOARDNAME t1024rdb 804 #define BANK_INTLV cs0_cs1 805 #else 806 #define CONFIG_BOARDNAME t1023rdb 807 #define BANK_INTLV null 808 #endif 809 810 #define CONFIG_EXTRA_ENV_SETTINGS \ 811 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 812 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 813 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 814 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 815 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 816 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 817 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 818 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 819 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 820 "netdev=eth0\0" \ 821 "tftpflash=tftpboot $loadaddr $uboot && " \ 822 "protect off $ubootaddr +$filesize && " \ 823 "erase $ubootaddr +$filesize && " \ 824 "cp.b $loadaddr $ubootaddr $filesize && " \ 825 "protect on $ubootaddr +$filesize && " \ 826 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 827 "consoledev=ttyS0\0" \ 828 "ramdiskaddr=2000000\0" \ 829 "fdtaddr=1e00000\0" \ 830 "bdev=sda3\0" 831 832 #define CONFIG_LINUX \ 833 "setenv bootargs root=/dev/ram rw " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "setenv ramdiskaddr 0x02000000;" \ 836 "setenv fdtaddr 0x00c00000;" \ 837 "setenv loadaddr 0x1000000;" \ 838 "bootm $loadaddr $ramdiskaddr $fdtaddr" 839 840 #define CONFIG_NFSBOOTCOMMAND \ 841 "setenv bootargs root=/dev/nfs rw " \ 842 "nfsroot=$serverip:$rootpath " \ 843 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "tftp $loadaddr $bootfile;" \ 846 "tftp $fdtaddr $fdtfile;" \ 847 "bootm $loadaddr - $fdtaddr" 848 849 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 850 851 #include <asm/fsl_secure_boot.h> 852 853 #endif /* __T1024RDB_H */ 854