1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 #define CONFIG_FSL_IFC /* Enable IFC Support */ 27 28 #define CONFIG_ENV_OVERWRITE 29 30 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 31 32 /* support deep sleep */ 33 #ifdef CONFIG_ARCH_T1024 34 #define CONFIG_DEEP_SLEEP 35 #endif 36 37 #ifdef CONFIG_RAMBOOT_PBL 38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 39 #define CONFIG_SPL_FLUSH_IMAGE 40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 41 #define CONFIG_SYS_TEXT_BASE 0x30001000 42 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 43 #define CONFIG_SPL_PAD_TO 0x40000 44 #define CONFIG_SPL_MAX_SIZE 0x28000 45 #define RESET_VECTOR_OFFSET 0x27FFC 46 #define BOOT_PAGE_OFFSET 0x27000 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 54 #ifdef CONFIG_NAND 55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 57 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 58 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 60 #if defined(CONFIG_TARGET_T1024RDB) 61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 62 #elif defined(CONFIG_TARGET_T1023RDB) 63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 64 #endif 65 #define CONFIG_SPL_NAND_BOOT 66 #endif 67 68 #ifdef CONFIG_SPIFLASH 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 70 #define CONFIG_SPL_SPI_FLASH_MINIMAL 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #if defined(CONFIG_TARGET_T1024RDB) 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 81 #elif defined(CONFIG_TARGET_T1023RDB) 82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 83 #endif 84 #define CONFIG_SPL_SPI_BOOT 85 #endif 86 87 #ifdef CONFIG_SDCARD 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 89 #define CONFIG_SPL_MMC_MINIMAL 90 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 92 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 93 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #if defined(CONFIG_TARGET_T1024RDB) 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 100 #elif defined(CONFIG_TARGET_T1023RDB) 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 102 #endif 103 #define CONFIG_SPL_MMC_BOOT 104 #endif 105 106 #endif /* CONFIG_RAMBOOT_PBL */ 107 108 #ifndef CONFIG_SYS_TEXT_BASE 109 #define CONFIG_SYS_TEXT_BASE 0xeff40000 110 #endif 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 #ifndef CONFIG_SYS_NO_FLASH 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 120 #endif 121 122 /* PCIe Boot - Master */ 123 #define CONFIG_SRIO_PCIE_BOOT_MASTER 124 /* 125 * for slave u-boot IMAGE instored in master memory space, 126 * PHYS must be aligned based on the SIZE 127 */ 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 133 #else 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 136 #endif 137 /* 138 * for slave UCODE and ENV instored in master memory space, 139 * PHYS must be aligned based on the SIZE 140 */ 141 #ifdef CONFIG_PHYS_64BIT 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 144 #else 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 147 #endif 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 149 /* slave core release by master*/ 150 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 151 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 152 153 /* PCIe Boot - Slave */ 154 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 158 /* Set 1M boot space for PCIe boot */ 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 161 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 162 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 163 #define CONFIG_SYS_NO_FLASH 164 #endif 165 166 #if defined(CONFIG_SPIFLASH) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_SPI_FLASH 169 #define CONFIG_ENV_SPI_BUS 0 170 #define CONFIG_ENV_SPI_CS 0 171 #define CONFIG_ENV_SPI_MAX_HZ 10000000 172 #define CONFIG_ENV_SPI_MODE 0 173 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 174 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 175 #if defined(CONFIG_TARGET_T1024RDB) 176 #define CONFIG_ENV_SECT_SIZE 0x10000 177 #elif defined(CONFIG_TARGET_T1023RDB) 178 #define CONFIG_ENV_SECT_SIZE 0x40000 179 #endif 180 #elif defined(CONFIG_SDCARD) 181 #define CONFIG_SYS_EXTRA_ENV_RELOC 182 #define CONFIG_ENV_IS_IN_MMC 183 #define CONFIG_SYS_MMC_ENV_DEV 0 184 #define CONFIG_ENV_SIZE 0x2000 185 #define CONFIG_ENV_OFFSET (512 * 0x800) 186 #elif defined(CONFIG_NAND) 187 #define CONFIG_SYS_EXTRA_ENV_RELOC 188 #define CONFIG_ENV_IS_IN_NAND 189 #define CONFIG_ENV_SIZE 0x2000 190 #if defined(CONFIG_TARGET_T1024RDB) 191 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 192 #elif defined(CONFIG_TARGET_T1023RDB) 193 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 194 #endif 195 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 196 #define CONFIG_ENV_IS_IN_REMOTE 197 #define CONFIG_ENV_ADDR 0xffe20000 198 #define CONFIG_ENV_SIZE 0x2000 199 #elif defined(CONFIG_ENV_IS_NOWHERE) 200 #define CONFIG_ENV_SIZE 0x2000 201 #else 202 #define CONFIG_ENV_IS_IN_FLASH 203 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 204 #define CONFIG_ENV_SIZE 0x2000 205 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 206 #endif 207 208 #ifndef __ASSEMBLY__ 209 unsigned long get_board_sys_clk(void); 210 unsigned long get_board_ddr_clk(void); 211 #endif 212 213 #define CONFIG_SYS_CLK_FREQ 100000000 214 #define CONFIG_DDR_CLK_FREQ 100000000 215 216 /* 217 * These can be toggled for performance analysis, otherwise use default. 218 */ 219 #define CONFIG_SYS_CACHE_STASHING 220 #define CONFIG_BACKSIDE_L2_CACHE 221 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 222 #define CONFIG_BTB /* toggle branch predition */ 223 #define CONFIG_DDR_ECC 224 #ifdef CONFIG_DDR_ECC 225 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 226 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 227 #endif 228 229 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 230 #define CONFIG_SYS_MEMTEST_END 0x00400000 231 #define CONFIG_SYS_ALT_MEMTEST 232 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 233 234 /* 235 * Config the L3 Cache as L3 SRAM 236 */ 237 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 238 #define CONFIG_SYS_L3_SIZE (256 << 10) 239 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 240 #ifdef CONFIG_RAMBOOT_PBL 241 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 242 #endif 243 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 244 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 245 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 246 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 247 248 #ifdef CONFIG_PHYS_64BIT 249 #define CONFIG_SYS_DCSRBAR 0xf0000000 250 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 251 #endif 252 253 /* EEPROM */ 254 #define CONFIG_ID_EEPROM 255 #define CONFIG_SYS_I2C_EEPROM_NXID 256 #define CONFIG_SYS_EEPROM_BUS_NUM 0 257 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 261 262 /* 263 * DDR Setup 264 */ 265 #define CONFIG_VERY_BIG_RAM 266 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 267 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 268 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 269 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 270 #define CONFIG_FSL_DDR_INTERACTIVE 271 #if defined(CONFIG_TARGET_T1024RDB) 272 #define CONFIG_DDR_SPD 273 #define CONFIG_SYS_SPD_BUS_NUM 0 274 #define SPD_EEPROM_ADDRESS 0x51 275 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 276 #elif defined(CONFIG_TARGET_T1023RDB) 277 #define CONFIG_SYS_DDR_RAW_TIMING 278 #define CONFIG_SYS_SDRAM_SIZE 2048 279 #endif 280 281 /* 282 * IFC Definitions 283 */ 284 #define CONFIG_SYS_FLASH_BASE 0xe8000000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 287 #else 288 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 289 #endif 290 291 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 292 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 293 CSPR_PORT_SIZE_16 | \ 294 CSPR_MSEL_NOR | \ 295 CSPR_V) 296 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 297 298 /* NOR Flash Timing Params */ 299 #if defined(CONFIG_TARGET_T1024RDB) 300 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 301 #elif defined(CONFIG_TARGET_T1023RDB) 302 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 303 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 304 #endif 305 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 306 FTIM0_NOR_TEADC(0x5) | \ 307 FTIM0_NOR_TEAHC(0x5)) 308 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 309 FTIM1_NOR_TRAD_NOR(0x1A) |\ 310 FTIM1_NOR_TSEQRAD_NOR(0x13)) 311 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 312 FTIM2_NOR_TCH(0x4) | \ 313 FTIM2_NOR_TWPH(0x0E) | \ 314 FTIM2_NOR_TWP(0x1c)) 315 #define CONFIG_SYS_NOR_FTIM3 0x0 316 317 #define CONFIG_SYS_FLASH_QUIET_TEST 318 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 319 320 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 321 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 322 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 323 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 324 325 #define CONFIG_SYS_FLASH_EMPTY_INFO 326 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 327 328 #ifdef CONFIG_TARGET_T1024RDB 329 /* CPLD on IFC */ 330 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 331 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 332 #define CONFIG_SYS_CSPR2_EXT (0xf) 333 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 334 | CSPR_PORT_SIZE_8 \ 335 | CSPR_MSEL_GPCM \ 336 | CSPR_V) 337 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 338 #define CONFIG_SYS_CSOR2 0x0 339 340 /* CPLD Timing parameters for IFC CS2 */ 341 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 342 FTIM0_GPCM_TEADC(0x0e) | \ 343 FTIM0_GPCM_TEAHC(0x0e)) 344 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 345 FTIM1_GPCM_TRAD(0x1f)) 346 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 347 FTIM2_GPCM_TCH(0x8) | \ 348 FTIM2_GPCM_TWP(0x1f)) 349 #define CONFIG_SYS_CS2_FTIM3 0x0 350 #endif 351 352 /* NAND Flash on IFC */ 353 #define CONFIG_NAND_FSL_IFC 354 #define CONFIG_SYS_NAND_BASE 0xff800000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 357 #else 358 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 359 #endif 360 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 361 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 362 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 363 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 364 | CSPR_V) 365 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 366 367 #if defined(CONFIG_TARGET_T1024RDB) 368 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 369 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 370 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 371 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 372 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 373 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 374 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 375 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 376 #elif defined(CONFIG_TARGET_T1023RDB) 377 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 378 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 379 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 380 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 381 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 382 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 383 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 384 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 385 #endif 386 387 #define CONFIG_SYS_NAND_ONFI_DETECTION 388 /* ONFI NAND Flash mode0 Timing Params */ 389 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 390 FTIM0_NAND_TWP(0x18) | \ 391 FTIM0_NAND_TWCHT(0x07) | \ 392 FTIM0_NAND_TWH(0x0a)) 393 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 394 FTIM1_NAND_TWBE(0x39) | \ 395 FTIM1_NAND_TRR(0x0e) | \ 396 FTIM1_NAND_TRP(0x18)) 397 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 398 FTIM2_NAND_TREH(0x0a) | \ 399 FTIM2_NAND_TWHRE(0x1e)) 400 #define CONFIG_SYS_NAND_FTIM3 0x0 401 402 #define CONFIG_SYS_NAND_DDR_LAW 11 403 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 404 #define CONFIG_SYS_MAX_NAND_DEVICE 1 405 #define CONFIG_CMD_NAND 406 407 #if defined(CONFIG_NAND) 408 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 409 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 410 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 411 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 412 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 413 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 414 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 415 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 416 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 417 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 418 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 424 #else 425 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 426 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 427 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 428 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 429 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 430 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 431 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 432 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 433 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 434 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 435 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 436 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 437 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 438 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 439 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 440 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 441 #endif 442 443 #ifdef CONFIG_SPL_BUILD 444 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 445 #else 446 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 447 #endif 448 449 #if defined(CONFIG_RAMBOOT_PBL) 450 #define CONFIG_SYS_RAMBOOT 451 #endif 452 453 #define CONFIG_BOARD_EARLY_INIT_R 454 #define CONFIG_MISC_INIT_R 455 456 #define CONFIG_HWCONFIG 457 458 /* define to use L1 as initial stack */ 459 #define CONFIG_L1_INIT_RAM 460 #define CONFIG_SYS_INIT_RAM_LOCK 461 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 465 /* The assembler doesn't like typecast */ 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 467 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 468 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 469 #else 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 473 #endif 474 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 475 476 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 477 GENERATED_GBL_DATA_SIZE) 478 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 479 480 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 481 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 482 483 /* Serial Port */ 484 #define CONFIG_CONS_INDEX 1 485 #define CONFIG_SYS_NS16550_SERIAL 486 #define CONFIG_SYS_NS16550_REG_SIZE 1 487 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 488 489 #define CONFIG_SYS_BAUDRATE_TABLE \ 490 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 491 492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 494 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 495 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 496 497 /* Video */ 498 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 499 #ifdef CONFIG_FSL_DIU_FB 500 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 501 #define CONFIG_CMD_BMP 502 #define CONFIG_VIDEO_LOGO 503 #define CONFIG_VIDEO_BMP_LOGO 504 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 505 /* 506 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 507 * disable empty flash sector detection, which is I/O-intensive. 508 */ 509 #undef CONFIG_SYS_FLASH_EMPTY_INFO 510 #endif 511 512 /* I2C */ 513 #define CONFIG_SYS_I2C 514 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 515 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 516 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 518 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 519 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 520 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 521 522 #define I2C_PCA6408_BUS_NUM 1 523 #define I2C_PCA6408_ADDR 0x20 524 525 /* I2C bus multiplexer */ 526 #define I2C_MUX_CH_DEFAULT 0x8 527 528 /* 529 * RTC configuration 530 */ 531 #define RTC 532 #define CONFIG_RTC_DS1337 1 533 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 534 535 /* 536 * eSPI - Enhanced SPI 537 */ 538 #define CONFIG_SPI_FLASH_BAR 539 #define CONFIG_SF_DEFAULT_SPEED 10000000 540 #define CONFIG_SF_DEFAULT_MODE 0 541 542 /* 543 * General PCIe 544 * Memory space is mapped 1-1, but I/O space must start from 0. 545 */ 546 #define CONFIG_PCIE1 /* PCIE controller 1 */ 547 #define CONFIG_PCIE2 /* PCIE controller 2 */ 548 #define CONFIG_PCIE3 /* PCIE controller 3 */ 549 #ifdef CONFIG_ARCH_T1040 550 #define CONFIG_PCIE4 /* PCIE controller 4 */ 551 #endif 552 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 553 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 554 #define CONFIG_PCI_INDIRECT_BRIDGE 555 556 #ifdef CONFIG_PCI 557 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 558 #ifdef CONFIG_PCIE1 559 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 560 #ifdef CONFIG_PHYS_64BIT 561 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 562 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 563 #else 564 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 565 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 566 #endif 567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 570 #ifdef CONFIG_PHYS_64BIT 571 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 572 #else 573 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 574 #endif 575 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 576 #endif 577 578 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 579 #ifdef CONFIG_PCIE2 580 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 581 #ifdef CONFIG_PHYS_64BIT 582 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 584 #else 585 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 586 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 587 #endif 588 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 590 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 591 #ifdef CONFIG_PHYS_64BIT 592 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 593 #else 594 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 595 #endif 596 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 597 #endif 598 599 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 600 #ifdef CONFIG_PCIE3 601 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 602 #ifdef CONFIG_PHYS_64BIT 603 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 604 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 605 #else 606 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 607 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 608 #endif 609 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 610 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 611 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 614 #else 615 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 616 #endif 617 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 618 #endif 619 620 /* controller 4, Base address 203000, to be removed */ 621 #ifdef CONFIG_PCIE4 622 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 623 #ifdef CONFIG_PHYS_64BIT 624 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 625 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 626 #else 627 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 628 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 629 #endif 630 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 631 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 632 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 633 #ifdef CONFIG_PHYS_64BIT 634 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 635 #else 636 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 637 #endif 638 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 639 #endif 640 641 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 642 #define CONFIG_DOS_PARTITION 643 #endif /* CONFIG_PCI */ 644 645 /* 646 * USB 647 */ 648 #define CONFIG_HAS_FSL_DR_USB 649 650 #ifdef CONFIG_HAS_FSL_DR_USB 651 #define CONFIG_USB_EHCI 652 #define CONFIG_USB_EHCI_FSL 653 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 654 #endif 655 656 /* 657 * SDHC 658 */ 659 #ifdef CONFIG_MMC 660 #define CONFIG_FSL_ESDHC 661 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 662 #define CONFIG_GENERIC_MMC 663 #define CONFIG_DOS_PARTITION 664 #endif 665 666 /* Qman/Bman */ 667 #ifndef CONFIG_NOBQFMAN 668 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 669 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 670 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 671 #ifdef CONFIG_PHYS_64BIT 672 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 673 #else 674 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 675 #endif 676 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 677 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 678 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 679 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 680 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 681 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 682 CONFIG_SYS_BMAN_CENA_SIZE) 683 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 684 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 685 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 686 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 687 #ifdef CONFIG_PHYS_64BIT 688 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 689 #else 690 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 691 #endif 692 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 693 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 694 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 695 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 696 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 697 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 698 CONFIG_SYS_QMAN_CENA_SIZE) 699 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 700 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 701 702 #define CONFIG_SYS_DPAA_FMAN 703 704 #ifdef CONFIG_TARGET_T1024RDB 705 #define CONFIG_QE 706 #define CONFIG_U_QE 707 #endif 708 /* Default address of microcode for the Linux FMan driver */ 709 #if defined(CONFIG_SPIFLASH) 710 /* 711 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 712 * env, so we got 0x110000. 713 */ 714 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 715 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 716 #define CONFIG_SYS_QE_FW_ADDR 0x130000 717 #elif defined(CONFIG_SDCARD) 718 /* 719 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 720 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 721 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 722 */ 723 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 724 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 725 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 726 #elif defined(CONFIG_NAND) 727 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 728 #if defined(CONFIG_TARGET_T1024RDB) 729 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 730 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 731 #elif defined(CONFIG_TARGET_T1023RDB) 732 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 733 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 734 #endif 735 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 736 /* 737 * Slave has no ucode locally, it can fetch this from remote. When implementing 738 * in two corenet boards, slave's ucode could be stored in master's memory 739 * space, the address can be mapped from slave TLB->slave LAW-> 740 * slave SRIO or PCIE outbound window->master inbound window-> 741 * master LAW->the ucode address in master's memory space. 742 */ 743 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 744 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 745 #else 746 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 747 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 748 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 749 #endif 750 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 751 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 752 #endif /* CONFIG_NOBQFMAN */ 753 754 #ifdef CONFIG_SYS_DPAA_FMAN 755 #define CONFIG_FMAN_ENET 756 #define CONFIG_PHYLIB_10G 757 #define CONFIG_PHY_REALTEK 758 #define CONFIG_PHY_AQUANTIA 759 #if defined(CONFIG_TARGET_T1024RDB) 760 #define RGMII_PHY1_ADDR 0x2 761 #define RGMII_PHY2_ADDR 0x6 762 #define SGMII_AQR_PHY_ADDR 0x2 763 #define FM1_10GEC1_PHY_ADDR 0x1 764 #elif defined(CONFIG_TARGET_T1023RDB) 765 #define RGMII_PHY1_ADDR 0x1 766 #define SGMII_RTK_PHY_ADDR 0x3 767 #define SGMII_AQR_PHY_ADDR 0x2 768 #endif 769 #endif 770 771 #ifdef CONFIG_FMAN_ENET 772 #define CONFIG_MII /* MII PHY management */ 773 #define CONFIG_ETHPRIME "FM1@DTSEC4" 774 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 775 #endif 776 777 /* 778 * Dynamic MTD Partition support with mtdparts 779 */ 780 #ifndef CONFIG_SYS_NO_FLASH 781 #define CONFIG_MTD_DEVICE 782 #define CONFIG_MTD_PARTITIONS 783 #define CONFIG_CMD_MTDPARTS 784 #define CONFIG_FLASH_CFI_MTD 785 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 786 "spi0=spife110000.1" 787 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 788 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 789 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 790 "1m(uboot),5m(kernel),128k(dtb),-(user)" 791 #endif 792 793 /* 794 * Environment 795 */ 796 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 797 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 798 799 /* 800 * Command line configuration. 801 */ 802 #define CONFIG_CMD_DATE 803 #define CONFIG_CMD_EEPROM 804 #define CONFIG_CMD_ERRATA 805 #define CONFIG_CMD_IRQ 806 #define CONFIG_CMD_REGINFO 807 808 #ifdef CONFIG_PCI 809 #define CONFIG_CMD_PCI 810 #endif 811 812 /* 813 * Miscellaneous configurable options 814 */ 815 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 816 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 817 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 818 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 819 #ifdef CONFIG_CMD_KGDB 820 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 821 #else 822 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 823 #endif 824 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 825 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 826 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 827 828 /* 829 * For booting Linux, the board info and command line data 830 * have to be in the first 64 MB of memory, since this is 831 * the maximum mapped by the Linux kernel during initialization. 832 */ 833 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 834 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 835 836 #ifdef CONFIG_CMD_KGDB 837 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 838 #endif 839 840 /* 841 * Environment Configuration 842 */ 843 #define CONFIG_ROOTPATH "/opt/nfsroot" 844 #define CONFIG_BOOTFILE "uImage" 845 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 846 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 847 #define CONFIG_BAUDRATE 115200 848 #define __USB_PHY_TYPE utmi 849 850 #ifdef CONFIG_ARCH_T1024 851 #define CONFIG_BOARDNAME t1024rdb 852 #define BANK_INTLV cs0_cs1 853 #else 854 #define CONFIG_BOARDNAME t1023rdb 855 #define BANK_INTLV null 856 #endif 857 858 #define CONFIG_EXTRA_ENV_SETTINGS \ 859 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 860 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 861 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 862 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 863 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 864 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 865 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 866 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 867 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 868 "netdev=eth0\0" \ 869 "tftpflash=tftpboot $loadaddr $uboot && " \ 870 "protect off $ubootaddr +$filesize && " \ 871 "erase $ubootaddr +$filesize && " \ 872 "cp.b $loadaddr $ubootaddr $filesize && " \ 873 "protect on $ubootaddr +$filesize && " \ 874 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 875 "consoledev=ttyS0\0" \ 876 "ramdiskaddr=2000000\0" \ 877 "fdtaddr=1e00000\0" \ 878 "bdev=sda3\0" 879 880 #define CONFIG_LINUX \ 881 "setenv bootargs root=/dev/ram rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "setenv ramdiskaddr 0x02000000;" \ 884 "setenv fdtaddr 0x00c00000;" \ 885 "setenv loadaddr 0x1000000;" \ 886 "bootm $loadaddr $ramdiskaddr $fdtaddr" 887 888 #define CONFIG_NFSBOOTCOMMAND \ 889 "setenv bootargs root=/dev/nfs rw " \ 890 "nfsroot=$serverip:$rootpath " \ 891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 892 "console=$consoledev,$baudrate $othbootargs;" \ 893 "tftp $loadaddr $bootfile;" \ 894 "tftp $fdtaddr $fdtfile;" \ 895 "bootm $loadaddr - $fdtaddr" 896 897 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 898 899 /* Hash command with SHA acceleration supported in hardware */ 900 #ifdef CONFIG_FSL_CAAM 901 #define CONFIG_CMD_HASH 902 #define CONFIG_SHA_HW_ACCEL 903 #endif 904 905 #include <asm/fsl_secure_boot.h> 906 907 #endif /* __T1024RDB_H */ 908