1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 30 31 /* support deep sleep */ 32 #ifdef CONFIG_ARCH_T1024 33 #define CONFIG_DEEP_SLEEP 34 #endif 35 36 #ifdef CONFIG_RAMBOOT_PBL 37 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 40 #define CONFIG_SYS_TEXT_BASE 0x30001000 41 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 42 #define CONFIG_SPL_PAD_TO 0x40000 43 #define CONFIG_SPL_MAX_SIZE 0x28000 44 #define RESET_VECTOR_OFFSET 0x27FFC 45 #define BOOT_PAGE_OFFSET 0x27000 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SPL_SKIP_RELOCATE 48 #define CONFIG_SPL_COMMON_INIT_DDR 49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 50 #define CONFIG_SYS_NO_FLASH 51 #endif 52 53 #ifdef CONFIG_NAND 54 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 55 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #if defined(CONFIG_TARGET_T1024RDB) 60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 61 #elif defined(CONFIG_TARGET_T1023RDB) 62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 63 #endif 64 #define CONFIG_SPL_NAND_BOOT 65 #endif 66 67 #ifdef CONFIG_SPIFLASH 68 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 69 #define CONFIG_SPL_SPI_FLASH_MINIMAL 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 75 #ifndef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 77 #endif 78 #if defined(CONFIG_TARGET_T1024RDB) 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 80 #elif defined(CONFIG_TARGET_T1023RDB) 81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 82 #endif 83 #define CONFIG_SPL_SPI_BOOT 84 #endif 85 86 #ifdef CONFIG_SDCARD 87 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 88 #define CONFIG_SPL_MMC_MINIMAL 89 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 90 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 91 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 92 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 93 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 94 #ifndef CONFIG_SPL_BUILD 95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 96 #endif 97 #if defined(CONFIG_TARGET_T1024RDB) 98 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 99 #elif defined(CONFIG_TARGET_T1023RDB) 100 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 101 #endif 102 #define CONFIG_SPL_MMC_BOOT 103 #endif 104 105 #endif /* CONFIG_RAMBOOT_PBL */ 106 107 #ifndef CONFIG_SYS_TEXT_BASE 108 #define CONFIG_SYS_TEXT_BASE 0xeff40000 109 #endif 110 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 113 #endif 114 115 #ifndef CONFIG_SYS_NO_FLASH 116 #define CONFIG_FLASH_CFI_DRIVER 117 #define CONFIG_SYS_FLASH_CFI 118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 119 #endif 120 121 /* PCIe Boot - Master */ 122 #define CONFIG_SRIO_PCIE_BOOT_MASTER 123 /* 124 * for slave u-boot IMAGE instored in master memory space, 125 * PHYS must be aligned based on the SIZE 126 */ 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 132 #else 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 135 #endif 136 /* 137 * for slave UCODE and ENV instored in master memory space, 138 * PHYS must be aligned based on the SIZE 139 */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 143 #else 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 146 #endif 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 148 /* slave core release by master*/ 149 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 150 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 151 152 /* PCIe Boot - Slave */ 153 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 156 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 157 /* Set 1M boot space for PCIe boot */ 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 161 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 162 #define CONFIG_SYS_NO_FLASH 163 #endif 164 165 #if defined(CONFIG_SPIFLASH) 166 #define CONFIG_SYS_EXTRA_ENV_RELOC 167 #define CONFIG_ENV_IS_IN_SPI_FLASH 168 #define CONFIG_ENV_SPI_BUS 0 169 #define CONFIG_ENV_SPI_CS 0 170 #define CONFIG_ENV_SPI_MAX_HZ 10000000 171 #define CONFIG_ENV_SPI_MODE 0 172 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 173 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 174 #if defined(CONFIG_TARGET_T1024RDB) 175 #define CONFIG_ENV_SECT_SIZE 0x10000 176 #elif defined(CONFIG_TARGET_T1023RDB) 177 #define CONFIG_ENV_SECT_SIZE 0x40000 178 #endif 179 #elif defined(CONFIG_SDCARD) 180 #define CONFIG_SYS_EXTRA_ENV_RELOC 181 #define CONFIG_ENV_IS_IN_MMC 182 #define CONFIG_SYS_MMC_ENV_DEV 0 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_OFFSET (512 * 0x800) 185 #elif defined(CONFIG_NAND) 186 #define CONFIG_SYS_EXTRA_ENV_RELOC 187 #define CONFIG_ENV_IS_IN_NAND 188 #define CONFIG_ENV_SIZE 0x2000 189 #if defined(CONFIG_TARGET_T1024RDB) 190 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 191 #elif defined(CONFIG_TARGET_T1023RDB) 192 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 193 #endif 194 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 195 #define CONFIG_ENV_IS_IN_REMOTE 196 #define CONFIG_ENV_ADDR 0xffe20000 197 #define CONFIG_ENV_SIZE 0x2000 198 #elif defined(CONFIG_ENV_IS_NOWHERE) 199 #define CONFIG_ENV_SIZE 0x2000 200 #else 201 #define CONFIG_ENV_IS_IN_FLASH 202 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 203 #define CONFIG_ENV_SIZE 0x2000 204 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 205 #endif 206 207 #ifndef __ASSEMBLY__ 208 unsigned long get_board_sys_clk(void); 209 unsigned long get_board_ddr_clk(void); 210 #endif 211 212 #define CONFIG_SYS_CLK_FREQ 100000000 213 #define CONFIG_DDR_CLK_FREQ 100000000 214 215 /* 216 * These can be toggled for performance analysis, otherwise use default. 217 */ 218 #define CONFIG_SYS_CACHE_STASHING 219 #define CONFIG_BACKSIDE_L2_CACHE 220 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 221 #define CONFIG_BTB /* toggle branch predition */ 222 #define CONFIG_DDR_ECC 223 #ifdef CONFIG_DDR_ECC 224 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 225 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 226 #endif 227 228 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 229 #define CONFIG_SYS_MEMTEST_END 0x00400000 230 #define CONFIG_SYS_ALT_MEMTEST 231 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 232 233 /* 234 * Config the L3 Cache as L3 SRAM 235 */ 236 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 237 #define CONFIG_SYS_L3_SIZE (256 << 10) 238 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 239 #ifdef CONFIG_RAMBOOT_PBL 240 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 241 #endif 242 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 243 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 244 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 245 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 246 247 #ifdef CONFIG_PHYS_64BIT 248 #define CONFIG_SYS_DCSRBAR 0xf0000000 249 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 250 #endif 251 252 /* EEPROM */ 253 #define CONFIG_ID_EEPROM 254 #define CONFIG_SYS_I2C_EEPROM_NXID 255 #define CONFIG_SYS_EEPROM_BUS_NUM 0 256 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 257 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 260 261 /* 262 * DDR Setup 263 */ 264 #define CONFIG_VERY_BIG_RAM 265 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 266 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 267 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 268 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 269 #define CONFIG_FSL_DDR_INTERACTIVE 270 #if defined(CONFIG_TARGET_T1024RDB) 271 #define CONFIG_DDR_SPD 272 #define CONFIG_SYS_SPD_BUS_NUM 0 273 #define SPD_EEPROM_ADDRESS 0x51 274 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 275 #elif defined(CONFIG_TARGET_T1023RDB) 276 #define CONFIG_SYS_DDR_RAW_TIMING 277 #define CONFIG_SYS_SDRAM_SIZE 2048 278 #endif 279 280 /* 281 * IFC Definitions 282 */ 283 #define CONFIG_SYS_FLASH_BASE 0xe8000000 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 286 #else 287 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 288 #endif 289 290 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 291 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 292 CSPR_PORT_SIZE_16 | \ 293 CSPR_MSEL_NOR | \ 294 CSPR_V) 295 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 296 297 /* NOR Flash Timing Params */ 298 #if defined(CONFIG_TARGET_T1024RDB) 299 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 300 #elif defined(CONFIG_TARGET_T1023RDB) 301 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 302 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 303 #endif 304 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 305 FTIM0_NOR_TEADC(0x5) | \ 306 FTIM0_NOR_TEAHC(0x5)) 307 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 308 FTIM1_NOR_TRAD_NOR(0x1A) |\ 309 FTIM1_NOR_TSEQRAD_NOR(0x13)) 310 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 311 FTIM2_NOR_TCH(0x4) | \ 312 FTIM2_NOR_TWPH(0x0E) | \ 313 FTIM2_NOR_TWP(0x1c)) 314 #define CONFIG_SYS_NOR_FTIM3 0x0 315 316 #define CONFIG_SYS_FLASH_QUIET_TEST 317 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 318 319 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 320 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 321 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 322 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 323 324 #define CONFIG_SYS_FLASH_EMPTY_INFO 325 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 326 327 #ifdef CONFIG_TARGET_T1024RDB 328 /* CPLD on IFC */ 329 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 330 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 331 #define CONFIG_SYS_CSPR2_EXT (0xf) 332 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 333 | CSPR_PORT_SIZE_8 \ 334 | CSPR_MSEL_GPCM \ 335 | CSPR_V) 336 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 337 #define CONFIG_SYS_CSOR2 0x0 338 339 /* CPLD Timing parameters for IFC CS2 */ 340 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 341 FTIM0_GPCM_TEADC(0x0e) | \ 342 FTIM0_GPCM_TEAHC(0x0e)) 343 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 344 FTIM1_GPCM_TRAD(0x1f)) 345 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 346 FTIM2_GPCM_TCH(0x8) | \ 347 FTIM2_GPCM_TWP(0x1f)) 348 #define CONFIG_SYS_CS2_FTIM3 0x0 349 #endif 350 351 /* NAND Flash on IFC */ 352 #define CONFIG_NAND_FSL_IFC 353 #define CONFIG_SYS_NAND_BASE 0xff800000 354 #ifdef CONFIG_PHYS_64BIT 355 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 356 #else 357 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 358 #endif 359 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 360 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 362 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 363 | CSPR_V) 364 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 365 366 #if defined(CONFIG_TARGET_T1024RDB) 367 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 368 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 369 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 370 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 371 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 372 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 373 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 374 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 375 #elif defined(CONFIG_TARGET_T1023RDB) 376 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 377 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 378 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 379 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 380 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 381 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 382 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 383 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 384 #endif 385 386 #define CONFIG_SYS_NAND_ONFI_DETECTION 387 /* ONFI NAND Flash mode0 Timing Params */ 388 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 389 FTIM0_NAND_TWP(0x18) | \ 390 FTIM0_NAND_TWCHT(0x07) | \ 391 FTIM0_NAND_TWH(0x0a)) 392 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 393 FTIM1_NAND_TWBE(0x39) | \ 394 FTIM1_NAND_TRR(0x0e) | \ 395 FTIM1_NAND_TRP(0x18)) 396 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 397 FTIM2_NAND_TREH(0x0a) | \ 398 FTIM2_NAND_TWHRE(0x1e)) 399 #define CONFIG_SYS_NAND_FTIM3 0x0 400 401 #define CONFIG_SYS_NAND_DDR_LAW 11 402 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 403 #define CONFIG_SYS_MAX_NAND_DEVICE 1 404 #define CONFIG_CMD_NAND 405 406 #if defined(CONFIG_NAND) 407 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 408 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 409 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 410 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 411 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 412 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 413 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 414 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 415 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #else 424 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 425 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 426 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 427 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 428 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 429 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 430 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 431 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 432 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 433 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 434 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 435 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 436 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 437 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 438 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 439 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 440 #endif 441 442 #ifdef CONFIG_SPL_BUILD 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 444 #else 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 446 #endif 447 448 #if defined(CONFIG_RAMBOOT_PBL) 449 #define CONFIG_SYS_RAMBOOT 450 #endif 451 452 #define CONFIG_BOARD_EARLY_INIT_R 453 #define CONFIG_MISC_INIT_R 454 455 #define CONFIG_HWCONFIG 456 457 /* define to use L1 as initial stack */ 458 #define CONFIG_L1_INIT_RAM 459 #define CONFIG_SYS_INIT_RAM_LOCK 460 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 464 /* The assembler doesn't like typecast */ 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 466 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 467 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 468 #else 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 472 #endif 473 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 474 475 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 476 GENERATED_GBL_DATA_SIZE) 477 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 478 479 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 480 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 481 482 /* Serial Port */ 483 #define CONFIG_CONS_INDEX 1 484 #define CONFIG_SYS_NS16550_SERIAL 485 #define CONFIG_SYS_NS16550_REG_SIZE 1 486 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 487 488 #define CONFIG_SYS_BAUDRATE_TABLE \ 489 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 490 491 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 492 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 493 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 494 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 495 496 /* Video */ 497 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 498 #ifdef CONFIG_FSL_DIU_FB 499 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 500 #define CONFIG_CMD_BMP 501 #define CONFIG_VIDEO_LOGO 502 #define CONFIG_VIDEO_BMP_LOGO 503 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 504 /* 505 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 506 * disable empty flash sector detection, which is I/O-intensive. 507 */ 508 #undef CONFIG_SYS_FLASH_EMPTY_INFO 509 #endif 510 511 /* I2C */ 512 #define CONFIG_SYS_I2C 513 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 514 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 515 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 517 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 519 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 520 521 #define I2C_PCA6408_BUS_NUM 1 522 #define I2C_PCA6408_ADDR 0x20 523 524 /* I2C bus multiplexer */ 525 #define I2C_MUX_CH_DEFAULT 0x8 526 527 /* 528 * RTC configuration 529 */ 530 #define RTC 531 #define CONFIG_RTC_DS1337 1 532 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 533 534 /* 535 * eSPI - Enhanced SPI 536 */ 537 #define CONFIG_SPI_FLASH_BAR 538 #define CONFIG_SF_DEFAULT_SPEED 10000000 539 #define CONFIG_SF_DEFAULT_MODE 0 540 541 /* 542 * General PCIe 543 * Memory space is mapped 1-1, but I/O space must start from 0. 544 */ 545 #define CONFIG_PCIE1 /* PCIE controller 1 */ 546 #define CONFIG_PCIE2 /* PCIE controller 2 */ 547 #define CONFIG_PCIE3 /* PCIE controller 3 */ 548 #ifdef CONFIG_ARCH_T1040 549 #define CONFIG_PCIE4 /* PCIE controller 4 */ 550 #endif 551 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 552 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 553 #define CONFIG_PCI_INDIRECT_BRIDGE 554 555 #ifdef CONFIG_PCI 556 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 557 #ifdef CONFIG_PCIE1 558 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 562 #else 563 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 564 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 565 #endif 566 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 568 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 569 #ifdef CONFIG_PHYS_64BIT 570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 571 #else 572 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 573 #endif 574 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 575 #endif 576 577 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 578 #ifdef CONFIG_PCIE2 579 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 583 #else 584 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 585 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 586 #endif 587 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 589 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 592 #else 593 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 594 #endif 595 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 599 #ifdef CONFIG_PCIE3 600 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 604 #else 605 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 606 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 607 #endif 608 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 610 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 611 #ifdef CONFIG_PHYS_64BIT 612 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 613 #else 614 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 615 #endif 616 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 617 #endif 618 619 /* controller 4, Base address 203000, to be removed */ 620 #ifdef CONFIG_PCIE4 621 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 622 #ifdef CONFIG_PHYS_64BIT 623 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 624 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 625 #else 626 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 627 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 628 #endif 629 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 630 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 631 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 632 #ifdef CONFIG_PHYS_64BIT 633 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 634 #else 635 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 636 #endif 637 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 638 #endif 639 640 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 641 #endif /* CONFIG_PCI */ 642 643 /* 644 * USB 645 */ 646 #define CONFIG_HAS_FSL_DR_USB 647 648 #ifdef CONFIG_HAS_FSL_DR_USB 649 #define CONFIG_USB_EHCI 650 #define CONFIG_USB_EHCI_FSL 651 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 652 #endif 653 654 /* 655 * SDHC 656 */ 657 #ifdef CONFIG_MMC 658 #define CONFIG_FSL_ESDHC 659 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 660 #endif 661 662 /* Qman/Bman */ 663 #ifndef CONFIG_NOBQFMAN 664 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 665 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 666 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 667 #ifdef CONFIG_PHYS_64BIT 668 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 669 #else 670 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 671 #endif 672 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 673 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 674 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 675 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 676 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 677 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 678 CONFIG_SYS_BMAN_CENA_SIZE) 679 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 680 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 681 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 682 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 683 #ifdef CONFIG_PHYS_64BIT 684 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 685 #else 686 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 687 #endif 688 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 689 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 690 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 691 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 692 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 693 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 694 CONFIG_SYS_QMAN_CENA_SIZE) 695 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 696 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 697 698 #define CONFIG_SYS_DPAA_FMAN 699 700 #ifdef CONFIG_TARGET_T1024RDB 701 #define CONFIG_QE 702 #define CONFIG_U_QE 703 #endif 704 /* Default address of microcode for the Linux FMan driver */ 705 #if defined(CONFIG_SPIFLASH) 706 /* 707 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 708 * env, so we got 0x110000. 709 */ 710 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 711 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 712 #define CONFIG_SYS_QE_FW_ADDR 0x130000 713 #elif defined(CONFIG_SDCARD) 714 /* 715 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 716 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 717 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 718 */ 719 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 720 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 721 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 722 #elif defined(CONFIG_NAND) 723 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 724 #if defined(CONFIG_TARGET_T1024RDB) 725 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 726 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 727 #elif defined(CONFIG_TARGET_T1023RDB) 728 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 729 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 730 #endif 731 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 732 /* 733 * Slave has no ucode locally, it can fetch this from remote. When implementing 734 * in two corenet boards, slave's ucode could be stored in master's memory 735 * space, the address can be mapped from slave TLB->slave LAW-> 736 * slave SRIO or PCIE outbound window->master inbound window-> 737 * master LAW->the ucode address in master's memory space. 738 */ 739 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 740 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 741 #else 742 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 743 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 744 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 745 #endif 746 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 747 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 748 #endif /* CONFIG_NOBQFMAN */ 749 750 #ifdef CONFIG_SYS_DPAA_FMAN 751 #define CONFIG_FMAN_ENET 752 #define CONFIG_PHYLIB_10G 753 #define CONFIG_PHY_REALTEK 754 #define CONFIG_PHY_AQUANTIA 755 #if defined(CONFIG_TARGET_T1024RDB) 756 #define RGMII_PHY1_ADDR 0x2 757 #define RGMII_PHY2_ADDR 0x6 758 #define SGMII_AQR_PHY_ADDR 0x2 759 #define FM1_10GEC1_PHY_ADDR 0x1 760 #elif defined(CONFIG_TARGET_T1023RDB) 761 #define RGMII_PHY1_ADDR 0x1 762 #define SGMII_RTK_PHY_ADDR 0x3 763 #define SGMII_AQR_PHY_ADDR 0x2 764 #endif 765 #endif 766 767 #ifdef CONFIG_FMAN_ENET 768 #define CONFIG_MII /* MII PHY management */ 769 #define CONFIG_ETHPRIME "FM1@DTSEC4" 770 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 771 #endif 772 773 /* 774 * Dynamic MTD Partition support with mtdparts 775 */ 776 #ifndef CONFIG_SYS_NO_FLASH 777 #define CONFIG_MTD_DEVICE 778 #define CONFIG_MTD_PARTITIONS 779 #define CONFIG_CMD_MTDPARTS 780 #define CONFIG_FLASH_CFI_MTD 781 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 782 "spi0=spife110000.1" 783 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 784 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 785 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 786 "1m(uboot),5m(kernel),128k(dtb),-(user)" 787 #endif 788 789 /* 790 * Environment 791 */ 792 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 793 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 794 795 /* 796 * Command line configuration. 797 */ 798 #define CONFIG_CMD_DATE 799 #define CONFIG_CMD_EEPROM 800 #define CONFIG_CMD_ERRATA 801 #define CONFIG_CMD_IRQ 802 #define CONFIG_CMD_REGINFO 803 804 #ifdef CONFIG_PCI 805 #define CONFIG_CMD_PCI 806 #endif 807 808 /* 809 * Miscellaneous configurable options 810 */ 811 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 812 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 813 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 814 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 815 #ifdef CONFIG_CMD_KGDB 816 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 817 #else 818 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 819 #endif 820 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 821 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 822 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 823 824 /* 825 * For booting Linux, the board info and command line data 826 * have to be in the first 64 MB of memory, since this is 827 * the maximum mapped by the Linux kernel during initialization. 828 */ 829 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 830 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 831 832 #ifdef CONFIG_CMD_KGDB 833 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 834 #endif 835 836 /* 837 * Environment Configuration 838 */ 839 #define CONFIG_ROOTPATH "/opt/nfsroot" 840 #define CONFIG_BOOTFILE "uImage" 841 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 842 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 843 #define CONFIG_BAUDRATE 115200 844 #define __USB_PHY_TYPE utmi 845 846 #ifdef CONFIG_ARCH_T1024 847 #define CONFIG_BOARDNAME t1024rdb 848 #define BANK_INTLV cs0_cs1 849 #else 850 #define CONFIG_BOARDNAME t1023rdb 851 #define BANK_INTLV null 852 #endif 853 854 #define CONFIG_EXTRA_ENV_SETTINGS \ 855 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 856 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 857 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 858 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 859 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 860 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 861 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 862 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 863 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 864 "netdev=eth0\0" \ 865 "tftpflash=tftpboot $loadaddr $uboot && " \ 866 "protect off $ubootaddr +$filesize && " \ 867 "erase $ubootaddr +$filesize && " \ 868 "cp.b $loadaddr $ubootaddr $filesize && " \ 869 "protect on $ubootaddr +$filesize && " \ 870 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 871 "consoledev=ttyS0\0" \ 872 "ramdiskaddr=2000000\0" \ 873 "fdtaddr=1e00000\0" \ 874 "bdev=sda3\0" 875 876 #define CONFIG_LINUX \ 877 "setenv bootargs root=/dev/ram rw " \ 878 "console=$consoledev,$baudrate $othbootargs;" \ 879 "setenv ramdiskaddr 0x02000000;" \ 880 "setenv fdtaddr 0x00c00000;" \ 881 "setenv loadaddr 0x1000000;" \ 882 "bootm $loadaddr $ramdiskaddr $fdtaddr" 883 884 #define CONFIG_NFSBOOTCOMMAND \ 885 "setenv bootargs root=/dev/nfs rw " \ 886 "nfsroot=$serverip:$rootpath " \ 887 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "tftp $loadaddr $bootfile;" \ 890 "tftp $fdtaddr $fdtfile;" \ 891 "bootm $loadaddr - $fdtaddr" 892 893 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 894 895 /* Hash command with SHA acceleration supported in hardware */ 896 #ifdef CONFIG_FSL_CAAM 897 #define CONFIG_CMD_HASH 898 #define CONFIG_SHA_HW_ACCEL 899 #endif 900 901 #include <asm/fsl_secure_boot.h> 902 903 #endif /* __T1024RDB_H */ 904