1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 RDB board configuration file 8 */ 9 10 #ifndef __T1024RDB_H 11 #define __T1024RDB_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_MP /* support multiple processors */ 16 #define CONFIG_ENABLE_36BIT_PHYS 17 18 #ifdef CONFIG_PHYS_64BIT 19 #define CONFIG_ADDR_MAP 1 20 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 21 #endif 22 23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 25 26 #define CONFIG_ENV_OVERWRITE 27 28 /* support deep sleep */ 29 #ifdef CONFIG_ARCH_T1024 30 #define CONFIG_DEEP_SLEEP 31 #endif 32 33 #ifdef CONFIG_RAMBOOT_PBL 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 35 #define CONFIG_SPL_FLUSH_IMAGE 36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_SKIP_RELOCATE 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 46 #endif 47 48 #ifdef CONFIG_NAND 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #if defined(CONFIG_TARGET_T1024RDB) 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 56 #elif defined(CONFIG_TARGET_T1023RDB) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 58 #endif 59 #define CONFIG_SPL_NAND_BOOT 60 #endif 61 62 #ifdef CONFIG_SPIFLASH 63 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 64 #define CONFIG_SPL_SPI_FLASH_MINIMAL 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 69 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 70 #ifndef CONFIG_SPL_BUILD 71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 72 #endif 73 #if defined(CONFIG_TARGET_T1024RDB) 74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 75 #elif defined(CONFIG_TARGET_T1023RDB) 76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 77 #endif 78 #define CONFIG_SPL_SPI_BOOT 79 #endif 80 81 #ifdef CONFIG_SDCARD 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 83 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 84 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 85 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 86 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 88 #ifndef CONFIG_SPL_BUILD 89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 90 #endif 91 #if defined(CONFIG_TARGET_T1024RDB) 92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 93 #elif defined(CONFIG_TARGET_T1023RDB) 94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 95 #endif 96 #define CONFIG_SPL_MMC_BOOT 97 #endif 98 99 #endif /* CONFIG_RAMBOOT_PBL */ 100 101 #ifndef CONFIG_RESET_VECTOR_ADDRESS 102 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 103 #endif 104 105 #ifdef CONFIG_MTD_NOR_FLASH 106 #define CONFIG_FLASH_CFI_DRIVER 107 #define CONFIG_SYS_FLASH_CFI 108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109 #endif 110 111 /* PCIe Boot - Master */ 112 #define CONFIG_SRIO_PCIE_BOOT_MASTER 113 /* 114 * for slave u-boot IMAGE instored in master memory space, 115 * PHYS must be aligned based on the SIZE 116 */ 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 119 #ifdef CONFIG_PHYS_64BIT 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 122 #else 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 125 #endif 126 /* 127 * for slave UCODE and ENV instored in master memory space, 128 * PHYS must be aligned based on the SIZE 129 */ 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 133 #else 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 136 #endif 137 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 138 /* slave core release by master*/ 139 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 140 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 141 142 /* PCIe Boot - Slave */ 143 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 145 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 146 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 147 /* Set 1M boot space for PCIe boot */ 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 149 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 150 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 151 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 152 #endif 153 154 #if defined(CONFIG_SPIFLASH) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_SPI_BUS 0 157 #define CONFIG_ENV_SPI_CS 0 158 #define CONFIG_ENV_SPI_MAX_HZ 10000000 159 #define CONFIG_ENV_SPI_MODE 0 160 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 161 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 162 #if defined(CONFIG_TARGET_T1024RDB) 163 #define CONFIG_ENV_SECT_SIZE 0x10000 164 #elif defined(CONFIG_TARGET_T1023RDB) 165 #define CONFIG_ENV_SECT_SIZE 0x40000 166 #endif 167 #elif defined(CONFIG_SDCARD) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_SYS_MMC_ENV_DEV 0 170 #define CONFIG_ENV_SIZE 0x2000 171 #define CONFIG_ENV_OFFSET (512 * 0x800) 172 #elif defined(CONFIG_NAND) 173 #define CONFIG_SYS_EXTRA_ENV_RELOC 174 #define CONFIG_ENV_SIZE 0x2000 175 #if defined(CONFIG_TARGET_T1024RDB) 176 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 177 #elif defined(CONFIG_TARGET_T1023RDB) 178 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 179 #endif 180 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 181 #define CONFIG_ENV_ADDR 0xffe20000 182 #define CONFIG_ENV_SIZE 0x2000 183 #elif defined(CONFIG_ENV_IS_NOWHERE) 184 #define CONFIG_ENV_SIZE 0x2000 185 #else 186 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 187 #define CONFIG_ENV_SIZE 0x2000 188 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 189 #endif 190 191 #ifndef __ASSEMBLY__ 192 unsigned long get_board_sys_clk(void); 193 unsigned long get_board_ddr_clk(void); 194 #endif 195 196 #define CONFIG_SYS_CLK_FREQ 100000000 197 #define CONFIG_DDR_CLK_FREQ 100000000 198 199 /* 200 * These can be toggled for performance analysis, otherwise use default. 201 */ 202 #define CONFIG_SYS_CACHE_STASHING 203 #define CONFIG_BACKSIDE_L2_CACHE 204 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 205 #define CONFIG_BTB /* toggle branch predition */ 206 #define CONFIG_DDR_ECC 207 #ifdef CONFIG_DDR_ECC 208 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 209 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 210 #endif 211 212 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 213 #define CONFIG_SYS_MEMTEST_END 0x00400000 214 215 /* 216 * Config the L3 Cache as L3 SRAM 217 */ 218 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 219 #define CONFIG_SYS_L3_SIZE (256 << 10) 220 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 221 #ifdef CONFIG_RAMBOOT_PBL 222 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 223 #endif 224 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 225 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 226 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 227 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 228 229 #ifdef CONFIG_PHYS_64BIT 230 #define CONFIG_SYS_DCSRBAR 0xf0000000 231 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 232 #endif 233 234 /* EEPROM */ 235 #define CONFIG_ID_EEPROM 236 #define CONFIG_SYS_I2C_EEPROM_NXID 237 #define CONFIG_SYS_EEPROM_BUS_NUM 0 238 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 242 243 /* 244 * DDR Setup 245 */ 246 #define CONFIG_VERY_BIG_RAM 247 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 248 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 249 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 250 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 251 #define CONFIG_FSL_DDR_INTERACTIVE 252 #if defined(CONFIG_TARGET_T1024RDB) 253 #define CONFIG_DDR_SPD 254 #define CONFIG_SYS_SPD_BUS_NUM 0 255 #define SPD_EEPROM_ADDRESS 0x51 256 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 257 #elif defined(CONFIG_TARGET_T1023RDB) 258 #define CONFIG_SYS_DDR_RAW_TIMING 259 #define CONFIG_SYS_SDRAM_SIZE 2048 260 #endif 261 262 /* 263 * IFC Definitions 264 */ 265 #define CONFIG_SYS_FLASH_BASE 0xe8000000 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 268 #else 269 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 270 #endif 271 272 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 273 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 274 CSPR_PORT_SIZE_16 | \ 275 CSPR_MSEL_NOR | \ 276 CSPR_V) 277 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 278 279 /* NOR Flash Timing Params */ 280 #if defined(CONFIG_TARGET_T1024RDB) 281 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 282 #elif defined(CONFIG_TARGET_T1023RDB) 283 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 284 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 285 #endif 286 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 287 FTIM0_NOR_TEADC(0x5) | \ 288 FTIM0_NOR_TEAHC(0x5)) 289 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 290 FTIM1_NOR_TRAD_NOR(0x1A) |\ 291 FTIM1_NOR_TSEQRAD_NOR(0x13)) 292 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 293 FTIM2_NOR_TCH(0x4) | \ 294 FTIM2_NOR_TWPH(0x0E) | \ 295 FTIM2_NOR_TWP(0x1c)) 296 #define CONFIG_SYS_NOR_FTIM3 0x0 297 298 #define CONFIG_SYS_FLASH_QUIET_TEST 299 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 300 301 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 302 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 303 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 304 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 305 306 #define CONFIG_SYS_FLASH_EMPTY_INFO 307 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 308 309 #ifdef CONFIG_TARGET_T1024RDB 310 /* CPLD on IFC */ 311 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 312 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 313 #define CONFIG_SYS_CSPR2_EXT (0xf) 314 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 315 | CSPR_PORT_SIZE_8 \ 316 | CSPR_MSEL_GPCM \ 317 | CSPR_V) 318 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 319 #define CONFIG_SYS_CSOR2 0x0 320 321 /* CPLD Timing parameters for IFC CS2 */ 322 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 323 FTIM0_GPCM_TEADC(0x0e) | \ 324 FTIM0_GPCM_TEAHC(0x0e)) 325 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 326 FTIM1_GPCM_TRAD(0x1f)) 327 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 328 FTIM2_GPCM_TCH(0x8) | \ 329 FTIM2_GPCM_TWP(0x1f)) 330 #define CONFIG_SYS_CS2_FTIM3 0x0 331 #endif 332 333 /* NAND Flash on IFC */ 334 #define CONFIG_NAND_FSL_IFC 335 #define CONFIG_SYS_NAND_BASE 0xff800000 336 #ifdef CONFIG_PHYS_64BIT 337 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 338 #else 339 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 340 #endif 341 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 342 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 343 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 344 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 345 | CSPR_V) 346 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 347 348 #if defined(CONFIG_TARGET_T1024RDB) 349 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 350 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 351 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 352 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 353 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 354 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 355 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 356 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 357 #elif defined(CONFIG_TARGET_T1023RDB) 358 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 359 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 360 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 361 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 362 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 363 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 364 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 365 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 366 #endif 367 368 #define CONFIG_SYS_NAND_ONFI_DETECTION 369 /* ONFI NAND Flash mode0 Timing Params */ 370 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 371 FTIM0_NAND_TWP(0x18) | \ 372 FTIM0_NAND_TWCHT(0x07) | \ 373 FTIM0_NAND_TWH(0x0a)) 374 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 375 FTIM1_NAND_TWBE(0x39) | \ 376 FTIM1_NAND_TRR(0x0e) | \ 377 FTIM1_NAND_TRP(0x18)) 378 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 379 FTIM2_NAND_TREH(0x0a) | \ 380 FTIM2_NAND_TWHRE(0x1e)) 381 #define CONFIG_SYS_NAND_FTIM3 0x0 382 383 #define CONFIG_SYS_NAND_DDR_LAW 11 384 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 385 #define CONFIG_SYS_MAX_NAND_DEVICE 1 386 387 #if defined(CONFIG_NAND) 388 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 389 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 390 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 391 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 392 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 393 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 394 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 395 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 396 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 397 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 398 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 399 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 400 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 401 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 402 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 403 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 404 #else 405 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 406 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 407 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 421 #endif 422 423 #ifdef CONFIG_SPL_BUILD 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 425 #else 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 427 #endif 428 429 #if defined(CONFIG_RAMBOOT_PBL) 430 #define CONFIG_SYS_RAMBOOT 431 #endif 432 433 #define CONFIG_MISC_INIT_R 434 435 #define CONFIG_HWCONFIG 436 437 /* define to use L1 as initial stack */ 438 #define CONFIG_L1_INIT_RAM 439 #define CONFIG_SYS_INIT_RAM_LOCK 440 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 441 #ifdef CONFIG_PHYS_64BIT 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 444 /* The assembler doesn't like typecast */ 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 446 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 447 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 448 #else 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 452 #endif 453 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 454 455 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 456 GENERATED_GBL_DATA_SIZE) 457 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 458 459 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 460 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 461 462 /* Serial Port */ 463 #define CONFIG_SYS_NS16550_SERIAL 464 #define CONFIG_SYS_NS16550_REG_SIZE 1 465 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 466 467 #define CONFIG_SYS_BAUDRATE_TABLE \ 468 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 469 470 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 471 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 472 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 473 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 474 475 /* Video */ 476 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 477 #ifdef CONFIG_FSL_DIU_FB 478 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 479 #define CONFIG_VIDEO_LOGO 480 #define CONFIG_VIDEO_BMP_LOGO 481 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 482 /* 483 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 484 * disable empty flash sector detection, which is I/O-intensive. 485 */ 486 #undef CONFIG_SYS_FLASH_EMPTY_INFO 487 #endif 488 489 /* I2C */ 490 #define CONFIG_SYS_I2C 491 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 492 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 493 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 494 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 495 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 496 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 497 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 498 499 #define I2C_PCA6408_BUS_NUM 1 500 #define I2C_PCA6408_ADDR 0x20 501 502 /* I2C bus multiplexer */ 503 #define I2C_MUX_CH_DEFAULT 0x8 504 505 /* 506 * RTC configuration 507 */ 508 #define RTC 509 #define CONFIG_RTC_DS1337 1 510 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 511 512 /* 513 * eSPI - Enhanced SPI 514 */ 515 #define CONFIG_SPI_FLASH_BAR 516 #define CONFIG_SF_DEFAULT_SPEED 10000000 517 #define CONFIG_SF_DEFAULT_MODE 0 518 519 /* 520 * General PCIe 521 * Memory space is mapped 1-1, but I/O space must start from 0. 522 */ 523 #define CONFIG_PCIE1 /* PCIE controller 1 */ 524 #define CONFIG_PCIE2 /* PCIE controller 2 */ 525 #define CONFIG_PCIE3 /* PCIE controller 3 */ 526 #ifdef CONFIG_ARCH_T1040 527 #define CONFIG_PCIE4 /* PCIE controller 4 */ 528 #endif 529 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 530 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 531 #define CONFIG_PCI_INDIRECT_BRIDGE 532 533 #ifdef CONFIG_PCI 534 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 535 #ifdef CONFIG_PCIE1 536 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 537 #ifdef CONFIG_PHYS_64BIT 538 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 539 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 540 #else 541 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 542 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 543 #endif 544 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 545 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 546 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 547 #ifdef CONFIG_PHYS_64BIT 548 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 549 #else 550 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 551 #endif 552 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 553 #endif 554 555 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 556 #ifdef CONFIG_PCIE2 557 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 558 #ifdef CONFIG_PHYS_64BIT 559 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 560 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 561 #else 562 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 563 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 564 #endif 565 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 566 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 567 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 570 #else 571 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 572 #endif 573 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 574 #endif 575 576 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 577 #ifdef CONFIG_PCIE3 578 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 579 #ifdef CONFIG_PHYS_64BIT 580 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 582 #else 583 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 584 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 585 #endif 586 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 587 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 588 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 591 #else 592 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 593 #endif 594 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 595 #endif 596 597 /* controller 4, Base address 203000, to be removed */ 598 #ifdef CONFIG_PCIE4 599 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 600 #ifdef CONFIG_PHYS_64BIT 601 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 602 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 603 #else 604 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 605 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 606 #endif 607 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 608 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 609 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 612 #else 613 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 614 #endif 615 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 616 #endif 617 618 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 619 #endif /* CONFIG_PCI */ 620 621 /* 622 * USB 623 */ 624 #define CONFIG_HAS_FSL_DR_USB 625 626 #ifdef CONFIG_HAS_FSL_DR_USB 627 #define CONFIG_USB_EHCI_FSL 628 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 629 #endif 630 631 /* 632 * SDHC 633 */ 634 #ifdef CONFIG_MMC 635 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 636 #endif 637 638 /* Qman/Bman */ 639 #ifndef CONFIG_NOBQFMAN 640 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 641 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 642 #ifdef CONFIG_PHYS_64BIT 643 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 644 #else 645 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 646 #endif 647 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 648 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 649 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 650 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 651 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 653 CONFIG_SYS_BMAN_CENA_SIZE) 654 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 655 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 656 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 657 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 658 #ifdef CONFIG_PHYS_64BIT 659 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 660 #else 661 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 662 #endif 663 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 664 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 665 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 666 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 667 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 668 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 669 CONFIG_SYS_QMAN_CENA_SIZE) 670 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 671 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 672 673 #define CONFIG_SYS_DPAA_FMAN 674 675 #ifdef CONFIG_TARGET_T1024RDB 676 #define CONFIG_QE 677 #define CONFIG_U_QE 678 #endif 679 /* Default address of microcode for the Linux FMan driver */ 680 #if defined(CONFIG_SPIFLASH) 681 /* 682 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 683 * env, so we got 0x110000. 684 */ 685 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 686 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 687 #define CONFIG_SYS_QE_FW_ADDR 0x130000 688 #elif defined(CONFIG_SDCARD) 689 /* 690 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 691 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 692 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 693 */ 694 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 695 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 696 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 697 #elif defined(CONFIG_NAND) 698 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 699 #if defined(CONFIG_TARGET_T1024RDB) 700 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 701 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 702 #elif defined(CONFIG_TARGET_T1023RDB) 703 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 704 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 705 #endif 706 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 707 /* 708 * Slave has no ucode locally, it can fetch this from remote. When implementing 709 * in two corenet boards, slave's ucode could be stored in master's memory 710 * space, the address can be mapped from slave TLB->slave LAW-> 711 * slave SRIO or PCIE outbound window->master inbound window-> 712 * master LAW->the ucode address in master's memory space. 713 */ 714 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 715 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 716 #else 717 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 718 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 719 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 720 #endif 721 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 722 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 723 #endif /* CONFIG_NOBQFMAN */ 724 725 #ifdef CONFIG_SYS_DPAA_FMAN 726 #define CONFIG_FMAN_ENET 727 #define CONFIG_PHYLIB_10G 728 #define CONFIG_PHY_REALTEK 729 #define CONFIG_PHY_AQUANTIA 730 #if defined(CONFIG_TARGET_T1024RDB) 731 #define RGMII_PHY1_ADDR 0x2 732 #define RGMII_PHY2_ADDR 0x6 733 #define SGMII_AQR_PHY_ADDR 0x2 734 #define FM1_10GEC1_PHY_ADDR 0x1 735 #elif defined(CONFIG_TARGET_T1023RDB) 736 #define RGMII_PHY1_ADDR 0x1 737 #define SGMII_RTK_PHY_ADDR 0x3 738 #define SGMII_AQR_PHY_ADDR 0x2 739 #endif 740 #endif 741 742 #ifdef CONFIG_FMAN_ENET 743 #define CONFIG_MII /* MII PHY management */ 744 #define CONFIG_ETHPRIME "FM1@DTSEC4" 745 #endif 746 747 /* 748 * Dynamic MTD Partition support with mtdparts 749 */ 750 #ifdef CONFIG_MTD_NOR_FLASH 751 #define CONFIG_MTD_DEVICE 752 #define CONFIG_MTD_PARTITIONS 753 #define CONFIG_FLASH_CFI_MTD 754 #endif 755 756 /* 757 * Environment 758 */ 759 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 760 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 761 762 /* 763 * Miscellaneous configurable options 764 */ 765 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 766 767 /* 768 * For booting Linux, the board info and command line data 769 * have to be in the first 64 MB of memory, since this is 770 * the maximum mapped by the Linux kernel during initialization. 771 */ 772 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 773 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 774 775 #ifdef CONFIG_CMD_KGDB 776 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 777 #endif 778 779 /* 780 * Environment Configuration 781 */ 782 #define CONFIG_ROOTPATH "/opt/nfsroot" 783 #define CONFIG_BOOTFILE "uImage" 784 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 785 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 786 #define __USB_PHY_TYPE utmi 787 788 #ifdef CONFIG_ARCH_T1024 789 #define CONFIG_BOARDNAME t1024rdb 790 #define BANK_INTLV cs0_cs1 791 #else 792 #define CONFIG_BOARDNAME t1023rdb 793 #define BANK_INTLV null 794 #endif 795 796 #define CONFIG_EXTRA_ENV_SETTINGS \ 797 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 798 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 799 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 800 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 801 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 802 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 803 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 804 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 805 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 806 "netdev=eth0\0" \ 807 "tftpflash=tftpboot $loadaddr $uboot && " \ 808 "protect off $ubootaddr +$filesize && " \ 809 "erase $ubootaddr +$filesize && " \ 810 "cp.b $loadaddr $ubootaddr $filesize && " \ 811 "protect on $ubootaddr +$filesize && " \ 812 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 813 "consoledev=ttyS0\0" \ 814 "ramdiskaddr=2000000\0" \ 815 "fdtaddr=1e00000\0" \ 816 "bdev=sda3\0" 817 818 #define CONFIG_LINUX \ 819 "setenv bootargs root=/dev/ram rw " \ 820 "console=$consoledev,$baudrate $othbootargs;" \ 821 "setenv ramdiskaddr 0x02000000;" \ 822 "setenv fdtaddr 0x00c00000;" \ 823 "setenv loadaddr 0x1000000;" \ 824 "bootm $loadaddr $ramdiskaddr $fdtaddr" 825 826 #define CONFIG_NFSBOOTCOMMAND \ 827 "setenv bootargs root=/dev/nfs rw " \ 828 "nfsroot=$serverip:$rootpath " \ 829 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "tftp $loadaddr $bootfile;" \ 832 "tftp $fdtaddr $fdtfile;" \ 833 "bootm $loadaddr - $fdtaddr" 834 835 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 836 837 #include <asm/fsl_secure_boot.h> 838 839 #endif /* __T1024RDB_H */ 840