1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #define CONFIG_E500MC /* BOOKE e500mc family */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 31 #define CONFIG_ENV_OVERWRITE 32 33 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 34 35 /* support deep sleep */ 36 #ifdef CONFIG_ARCH_T1024 37 #define CONFIG_DEEP_SLEEP 38 #endif 39 #if defined(CONFIG_DEEP_SLEEP) 40 #define CONFIG_BOARD_EARLY_INIT_F 41 #endif 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 45 #define CONFIG_SPL_FLUSH_IMAGE 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_SYS_TEXT_BASE 0x30001000 48 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 49 #define CONFIG_SPL_PAD_TO 0x40000 50 #define CONFIG_SPL_MAX_SIZE 0x28000 51 #define RESET_VECTOR_OFFSET 0x27FFC 52 #define BOOT_PAGE_OFFSET 0x27000 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SPL_SKIP_RELOCATE 55 #define CONFIG_SPL_COMMON_INIT_DDR 56 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 57 #define CONFIG_SYS_NO_FLASH 58 #endif 59 60 #ifdef CONFIG_NAND 61 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 62 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 63 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 64 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 66 #if defined(CONFIG_T1024RDB) 67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 68 #elif defined(CONFIG_T1023RDB) 69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 70 #endif 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_SPI_FLASH_MINIMAL 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #if defined(CONFIG_T1024RDB) 86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 87 #elif defined(CONFIG_T1023RDB) 88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 89 #endif 90 #define CONFIG_SPL_SPI_BOOT 91 #endif 92 93 #ifdef CONFIG_SDCARD 94 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 95 #define CONFIG_SPL_MMC_MINIMAL 96 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 97 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 98 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 99 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 101 #ifndef CONFIG_SPL_BUILD 102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 103 #endif 104 #if defined(CONFIG_T1024RDB) 105 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 106 #elif defined(CONFIG_T1023RDB) 107 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 108 #endif 109 #define CONFIG_SPL_MMC_BOOT 110 #endif 111 112 #endif /* CONFIG_RAMBOOT_PBL */ 113 114 #ifndef CONFIG_SYS_TEXT_BASE 115 #define CONFIG_SYS_TEXT_BASE 0xeff40000 116 #endif 117 118 #ifndef CONFIG_RESET_VECTOR_ADDRESS 119 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 120 #endif 121 122 #ifndef CONFIG_SYS_NO_FLASH 123 #define CONFIG_FLASH_CFI_DRIVER 124 #define CONFIG_SYS_FLASH_CFI 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 126 #endif 127 128 /* PCIe Boot - Master */ 129 #define CONFIG_SRIO_PCIE_BOOT_MASTER 130 /* 131 * for slave u-boot IMAGE instored in master memory space, 132 * PHYS must be aligned based on the SIZE 133 */ 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 139 #else 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 142 #endif 143 /* 144 * for slave UCODE and ENV instored in master memory space, 145 * PHYS must be aligned based on the SIZE 146 */ 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 150 #else 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 152 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 153 #endif 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 155 /* slave core release by master*/ 156 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 157 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 158 159 /* PCIe Boot - Slave */ 160 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 162 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 163 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 164 /* Set 1M boot space for PCIe boot */ 165 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 166 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 167 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 168 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 169 #define CONFIG_SYS_NO_FLASH 170 #endif 171 172 #if defined(CONFIG_SPIFLASH) 173 #define CONFIG_SYS_EXTRA_ENV_RELOC 174 #define CONFIG_ENV_IS_IN_SPI_FLASH 175 #define CONFIG_ENV_SPI_BUS 0 176 #define CONFIG_ENV_SPI_CS 0 177 #define CONFIG_ENV_SPI_MAX_HZ 10000000 178 #define CONFIG_ENV_SPI_MODE 0 179 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 180 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 181 #if defined(CONFIG_T1024RDB) 182 #define CONFIG_ENV_SECT_SIZE 0x10000 183 #elif defined(CONFIG_T1023RDB) 184 #define CONFIG_ENV_SECT_SIZE 0x40000 185 #endif 186 #elif defined(CONFIG_SDCARD) 187 #define CONFIG_SYS_EXTRA_ENV_RELOC 188 #define CONFIG_ENV_IS_IN_MMC 189 #define CONFIG_SYS_MMC_ENV_DEV 0 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_OFFSET (512 * 0x800) 192 #elif defined(CONFIG_NAND) 193 #define CONFIG_SYS_EXTRA_ENV_RELOC 194 #define CONFIG_ENV_IS_IN_NAND 195 #define CONFIG_ENV_SIZE 0x2000 196 #if defined(CONFIG_T1024RDB) 197 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 198 #elif defined(CONFIG_T1023RDB) 199 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 200 #endif 201 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 202 #define CONFIG_ENV_IS_IN_REMOTE 203 #define CONFIG_ENV_ADDR 0xffe20000 204 #define CONFIG_ENV_SIZE 0x2000 205 #elif defined(CONFIG_ENV_IS_NOWHERE) 206 #define CONFIG_ENV_SIZE 0x2000 207 #else 208 #define CONFIG_ENV_IS_IN_FLASH 209 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 210 #define CONFIG_ENV_SIZE 0x2000 211 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 212 #endif 213 214 #ifndef __ASSEMBLY__ 215 unsigned long get_board_sys_clk(void); 216 unsigned long get_board_ddr_clk(void); 217 #endif 218 219 #define CONFIG_SYS_CLK_FREQ 100000000 220 #define CONFIG_DDR_CLK_FREQ 100000000 221 222 /* 223 * These can be toggled for performance analysis, otherwise use default. 224 */ 225 #define CONFIG_SYS_CACHE_STASHING 226 #define CONFIG_BACKSIDE_L2_CACHE 227 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 228 #define CONFIG_BTB /* toggle branch predition */ 229 #define CONFIG_DDR_ECC 230 #ifdef CONFIG_DDR_ECC 231 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 232 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 233 #endif 234 235 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 236 #define CONFIG_SYS_MEMTEST_END 0x00400000 237 #define CONFIG_SYS_ALT_MEMTEST 238 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 239 240 /* 241 * Config the L3 Cache as L3 SRAM 242 */ 243 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 244 #define CONFIG_SYS_L3_SIZE (256 << 10) 245 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 246 #ifdef CONFIG_RAMBOOT_PBL 247 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 248 #endif 249 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 250 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 251 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 252 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 253 254 #ifdef CONFIG_PHYS_64BIT 255 #define CONFIG_SYS_DCSRBAR 0xf0000000 256 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 257 #endif 258 259 /* EEPROM */ 260 #define CONFIG_ID_EEPROM 261 #define CONFIG_SYS_I2C_EEPROM_NXID 262 #define CONFIG_SYS_EEPROM_BUS_NUM 0 263 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 267 268 /* 269 * DDR Setup 270 */ 271 #define CONFIG_VERY_BIG_RAM 272 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 273 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 274 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 275 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 276 #define CONFIG_FSL_DDR_INTERACTIVE 277 #if defined(CONFIG_T1024RDB) 278 #define CONFIG_DDR_SPD 279 #define CONFIG_SYS_FSL_DDR3 280 #define CONFIG_SYS_SPD_BUS_NUM 0 281 #define SPD_EEPROM_ADDRESS 0x51 282 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 283 #elif defined(CONFIG_T1023RDB) 284 #define CONFIG_SYS_FSL_DDR4 285 #define CONFIG_SYS_DDR_RAW_TIMING 286 #define CONFIG_SYS_SDRAM_SIZE 2048 287 #endif 288 289 /* 290 * IFC Definitions 291 */ 292 #define CONFIG_SYS_FLASH_BASE 0xe8000000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 295 #else 296 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 297 #endif 298 299 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 300 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 301 CSPR_PORT_SIZE_16 | \ 302 CSPR_MSEL_NOR | \ 303 CSPR_V) 304 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 305 306 /* NOR Flash Timing Params */ 307 #if defined(CONFIG_T1024RDB) 308 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 309 #elif defined(CONFIG_T1023RDB) 310 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 311 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 312 #endif 313 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 314 FTIM0_NOR_TEADC(0x5) | \ 315 FTIM0_NOR_TEAHC(0x5)) 316 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 317 FTIM1_NOR_TRAD_NOR(0x1A) |\ 318 FTIM1_NOR_TSEQRAD_NOR(0x13)) 319 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 320 FTIM2_NOR_TCH(0x4) | \ 321 FTIM2_NOR_TWPH(0x0E) | \ 322 FTIM2_NOR_TWP(0x1c)) 323 #define CONFIG_SYS_NOR_FTIM3 0x0 324 325 #define CONFIG_SYS_FLASH_QUIET_TEST 326 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 327 328 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 329 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 330 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 331 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 332 333 #define CONFIG_SYS_FLASH_EMPTY_INFO 334 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 335 336 #ifdef CONFIG_T1024RDB 337 /* CPLD on IFC */ 338 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 339 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 340 #define CONFIG_SYS_CSPR2_EXT (0xf) 341 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 342 | CSPR_PORT_SIZE_8 \ 343 | CSPR_MSEL_GPCM \ 344 | CSPR_V) 345 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 346 #define CONFIG_SYS_CSOR2 0x0 347 348 /* CPLD Timing parameters for IFC CS2 */ 349 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 350 FTIM0_GPCM_TEADC(0x0e) | \ 351 FTIM0_GPCM_TEAHC(0x0e)) 352 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 353 FTIM1_GPCM_TRAD(0x1f)) 354 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 355 FTIM2_GPCM_TCH(0x8) | \ 356 FTIM2_GPCM_TWP(0x1f)) 357 #define CONFIG_SYS_CS2_FTIM3 0x0 358 #endif 359 360 /* NAND Flash on IFC */ 361 #define CONFIG_NAND_FSL_IFC 362 #define CONFIG_SYS_NAND_BASE 0xff800000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 365 #else 366 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 367 #endif 368 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 369 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 370 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 371 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 372 | CSPR_V) 373 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 374 375 #if defined(CONFIG_T1024RDB) 376 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 377 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 378 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 379 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 380 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 381 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 382 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 383 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 384 #elif defined(CONFIG_T1023RDB) 385 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 386 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 387 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 388 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 389 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 390 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 391 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 392 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 393 #endif 394 395 #define CONFIG_SYS_NAND_ONFI_DETECTION 396 /* ONFI NAND Flash mode0 Timing Params */ 397 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 398 FTIM0_NAND_TWP(0x18) | \ 399 FTIM0_NAND_TWCHT(0x07) | \ 400 FTIM0_NAND_TWH(0x0a)) 401 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 402 FTIM1_NAND_TWBE(0x39) | \ 403 FTIM1_NAND_TRR(0x0e) | \ 404 FTIM1_NAND_TRP(0x18)) 405 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 406 FTIM2_NAND_TREH(0x0a) | \ 407 FTIM2_NAND_TWHRE(0x1e)) 408 #define CONFIG_SYS_NAND_FTIM3 0x0 409 410 #define CONFIG_SYS_NAND_DDR_LAW 11 411 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 412 #define CONFIG_SYS_MAX_NAND_DEVICE 1 413 #define CONFIG_CMD_NAND 414 415 #if defined(CONFIG_NAND) 416 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 417 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 418 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 419 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 420 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 421 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 422 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 423 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 424 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 425 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 426 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 427 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 428 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 429 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 430 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 431 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 432 #else 433 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 434 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 435 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 436 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 437 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 438 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 439 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 440 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 441 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 442 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 443 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 444 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 445 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 446 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 447 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 448 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 449 #endif 450 451 #ifdef CONFIG_SPL_BUILD 452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 453 #else 454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 455 #endif 456 457 #if defined(CONFIG_RAMBOOT_PBL) 458 #define CONFIG_SYS_RAMBOOT 459 #endif 460 461 #define CONFIG_BOARD_EARLY_INIT_R 462 #define CONFIG_MISC_INIT_R 463 464 #define CONFIG_HWCONFIG 465 466 /* define to use L1 as initial stack */ 467 #define CONFIG_L1_INIT_RAM 468 #define CONFIG_SYS_INIT_RAM_LOCK 469 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 473 /* The assembler doesn't like typecast */ 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 475 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 476 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 477 #else 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 481 #endif 482 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 483 484 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 485 GENERATED_GBL_DATA_SIZE) 486 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 487 488 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 489 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 490 491 /* Serial Port */ 492 #define CONFIG_CONS_INDEX 1 493 #define CONFIG_SYS_NS16550_SERIAL 494 #define CONFIG_SYS_NS16550_REG_SIZE 1 495 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 496 497 #define CONFIG_SYS_BAUDRATE_TABLE \ 498 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 499 500 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 501 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 502 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 503 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 504 505 /* Video */ 506 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 507 #ifdef CONFIG_FSL_DIU_FB 508 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 509 #define CONFIG_CMD_BMP 510 #define CONFIG_VIDEO_LOGO 511 #define CONFIG_VIDEO_BMP_LOGO 512 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 513 /* 514 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 515 * disable empty flash sector detection, which is I/O-intensive. 516 */ 517 #undef CONFIG_SYS_FLASH_EMPTY_INFO 518 #endif 519 520 /* I2C */ 521 #define CONFIG_SYS_I2C 522 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 523 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 524 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 525 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 526 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 527 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 528 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 529 530 #define I2C_PCA6408_BUS_NUM 1 531 #define I2C_PCA6408_ADDR 0x20 532 533 /* I2C bus multiplexer */ 534 #define I2C_MUX_CH_DEFAULT 0x8 535 536 /* 537 * RTC configuration 538 */ 539 #define RTC 540 #define CONFIG_RTC_DS1337 1 541 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 542 543 /* 544 * eSPI - Enhanced SPI 545 */ 546 #define CONFIG_SPI_FLASH_BAR 547 #define CONFIG_SF_DEFAULT_SPEED 10000000 548 #define CONFIG_SF_DEFAULT_MODE 0 549 550 /* 551 * General PCIe 552 * Memory space is mapped 1-1, but I/O space must start from 0. 553 */ 554 #define CONFIG_PCIE1 /* PCIE controller 1 */ 555 #define CONFIG_PCIE2 /* PCIE controller 2 */ 556 #define CONFIG_PCIE3 /* PCIE controller 3 */ 557 #ifdef CONFIG_ARCH_T1040 558 #define CONFIG_PCIE4 /* PCIE controller 4 */ 559 #endif 560 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 561 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 562 #define CONFIG_PCI_INDIRECT_BRIDGE 563 564 #ifdef CONFIG_PCI 565 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 566 #ifdef CONFIG_PCIE1 567 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 571 #else 572 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 573 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 574 #endif 575 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 576 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 577 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 580 #else 581 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 582 #endif 583 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 587 #ifdef CONFIG_PCIE2 588 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 592 #else 593 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 594 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 595 #endif 596 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 598 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 601 #else 602 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 603 #endif 604 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 608 #ifdef CONFIG_PCIE3 609 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 612 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 613 #else 614 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 615 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 616 #endif 617 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 618 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 619 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 622 #else 623 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 624 #endif 625 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 626 #endif 627 628 /* controller 4, Base address 203000, to be removed */ 629 #ifdef CONFIG_PCIE4 630 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 631 #ifdef CONFIG_PHYS_64BIT 632 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 633 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 634 #else 635 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 636 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 637 #endif 638 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 639 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 640 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 641 #ifdef CONFIG_PHYS_64BIT 642 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 643 #else 644 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 645 #endif 646 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 647 #endif 648 649 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 650 #define CONFIG_DOS_PARTITION 651 #endif /* CONFIG_PCI */ 652 653 /* 654 * USB 655 */ 656 #define CONFIG_HAS_FSL_DR_USB 657 658 #ifdef CONFIG_HAS_FSL_DR_USB 659 #define CONFIG_USB_EHCI 660 #define CONFIG_USB_EHCI_FSL 661 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 662 #endif 663 664 /* 665 * SDHC 666 */ 667 #ifdef CONFIG_MMC 668 #define CONFIG_FSL_ESDHC 669 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 670 #define CONFIG_GENERIC_MMC 671 #define CONFIG_DOS_PARTITION 672 #endif 673 674 /* Qman/Bman */ 675 #ifndef CONFIG_NOBQFMAN 676 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 677 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 678 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 679 #ifdef CONFIG_PHYS_64BIT 680 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 681 #else 682 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 683 #endif 684 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 685 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 686 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 687 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 688 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 689 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 690 CONFIG_SYS_BMAN_CENA_SIZE) 691 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 692 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 693 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 694 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 695 #ifdef CONFIG_PHYS_64BIT 696 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 697 #else 698 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 699 #endif 700 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 701 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 702 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 703 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 704 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 705 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 706 CONFIG_SYS_QMAN_CENA_SIZE) 707 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 708 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 709 710 #define CONFIG_SYS_DPAA_FMAN 711 712 #ifdef CONFIG_T1024RDB 713 #define CONFIG_QE 714 #define CONFIG_U_QE 715 #endif 716 /* Default address of microcode for the Linux FMan driver */ 717 #if defined(CONFIG_SPIFLASH) 718 /* 719 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 720 * env, so we got 0x110000. 721 */ 722 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 723 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 724 #define CONFIG_SYS_QE_FW_ADDR 0x130000 725 #elif defined(CONFIG_SDCARD) 726 /* 727 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 728 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 729 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 730 */ 731 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 732 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 733 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 734 #elif defined(CONFIG_NAND) 735 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 736 #if defined(CONFIG_T1024RDB) 737 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 738 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 739 #elif defined(CONFIG_T1023RDB) 740 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 741 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 742 #endif 743 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 744 /* 745 * Slave has no ucode locally, it can fetch this from remote. When implementing 746 * in two corenet boards, slave's ucode could be stored in master's memory 747 * space, the address can be mapped from slave TLB->slave LAW-> 748 * slave SRIO or PCIE outbound window->master inbound window-> 749 * master LAW->the ucode address in master's memory space. 750 */ 751 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 752 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 753 #else 754 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 755 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 756 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 757 #endif 758 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 759 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 760 #endif /* CONFIG_NOBQFMAN */ 761 762 #ifdef CONFIG_SYS_DPAA_FMAN 763 #define CONFIG_FMAN_ENET 764 #define CONFIG_PHYLIB_10G 765 #define CONFIG_PHY_REALTEK 766 #define CONFIG_PHY_AQUANTIA 767 #if defined(CONFIG_T1024RDB) 768 #define RGMII_PHY1_ADDR 0x2 769 #define RGMII_PHY2_ADDR 0x6 770 #define SGMII_AQR_PHY_ADDR 0x2 771 #define FM1_10GEC1_PHY_ADDR 0x1 772 #elif defined(CONFIG_T1023RDB) 773 #define RGMII_PHY1_ADDR 0x1 774 #define SGMII_RTK_PHY_ADDR 0x3 775 #define SGMII_AQR_PHY_ADDR 0x2 776 #endif 777 #endif 778 779 #ifdef CONFIG_FMAN_ENET 780 #define CONFIG_MII /* MII PHY management */ 781 #define CONFIG_ETHPRIME "FM1@DTSEC4" 782 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 783 #endif 784 785 /* 786 * Dynamic MTD Partition support with mtdparts 787 */ 788 #ifndef CONFIG_SYS_NO_FLASH 789 #define CONFIG_MTD_DEVICE 790 #define CONFIG_MTD_PARTITIONS 791 #define CONFIG_CMD_MTDPARTS 792 #define CONFIG_FLASH_CFI_MTD 793 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 794 "spi0=spife110000.1" 795 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 796 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 797 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 798 "1m(uboot),5m(kernel),128k(dtb),-(user)" 799 #endif 800 801 /* 802 * Environment 803 */ 804 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 805 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 806 807 /* 808 * Command line configuration. 809 */ 810 #define CONFIG_CMD_DATE 811 #define CONFIG_CMD_EEPROM 812 #define CONFIG_CMD_ERRATA 813 #define CONFIG_CMD_IRQ 814 #define CONFIG_CMD_REGINFO 815 816 #ifdef CONFIG_PCI 817 #define CONFIG_CMD_PCI 818 #endif 819 820 /* 821 * Miscellaneous configurable options 822 */ 823 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 824 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 825 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 826 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 827 #ifdef CONFIG_CMD_KGDB 828 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 829 #else 830 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 831 #endif 832 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 833 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 834 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 835 836 /* 837 * For booting Linux, the board info and command line data 838 * have to be in the first 64 MB of memory, since this is 839 * the maximum mapped by the Linux kernel during initialization. 840 */ 841 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 842 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 843 844 #ifdef CONFIG_CMD_KGDB 845 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 846 #endif 847 848 /* 849 * Environment Configuration 850 */ 851 #define CONFIG_ROOTPATH "/opt/nfsroot" 852 #define CONFIG_BOOTFILE "uImage" 853 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 854 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 855 #define CONFIG_BAUDRATE 115200 856 #define __USB_PHY_TYPE utmi 857 858 #ifdef CONFIG_ARCH_T1024 859 #define CONFIG_BOARDNAME t1024rdb 860 #define BANK_INTLV cs0_cs1 861 #else 862 #define CONFIG_BOARDNAME t1023rdb 863 #define BANK_INTLV null 864 #endif 865 866 #define CONFIG_EXTRA_ENV_SETTINGS \ 867 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 868 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 869 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 870 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 871 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 872 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 873 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 874 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 875 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 876 "netdev=eth0\0" \ 877 "tftpflash=tftpboot $loadaddr $uboot && " \ 878 "protect off $ubootaddr +$filesize && " \ 879 "erase $ubootaddr +$filesize && " \ 880 "cp.b $loadaddr $ubootaddr $filesize && " \ 881 "protect on $ubootaddr +$filesize && " \ 882 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 883 "consoledev=ttyS0\0" \ 884 "ramdiskaddr=2000000\0" \ 885 "fdtaddr=1e00000\0" \ 886 "bdev=sda3\0" 887 888 #define CONFIG_LINUX \ 889 "setenv bootargs root=/dev/ram rw " \ 890 "console=$consoledev,$baudrate $othbootargs;" \ 891 "setenv ramdiskaddr 0x02000000;" \ 892 "setenv fdtaddr 0x00c00000;" \ 893 "setenv loadaddr 0x1000000;" \ 894 "bootm $loadaddr $ramdiskaddr $fdtaddr" 895 896 #define CONFIG_NFSBOOTCOMMAND \ 897 "setenv bootargs root=/dev/nfs rw " \ 898 "nfsroot=$serverip:$rootpath " \ 899 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 900 "console=$consoledev,$baudrate $othbootargs;" \ 901 "tftp $loadaddr $bootfile;" \ 902 "tftp $fdtaddr $fdtfile;" \ 903 "bootm $loadaddr - $fdtaddr" 904 905 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 906 907 /* Hash command with SHA acceleration supported in hardware */ 908 #ifdef CONFIG_FSL_CAAM 909 #define CONFIG_CMD_HASH 910 #define CONFIG_SHA_HW_ACCEL 911 #endif 912 913 #include <asm/fsl_secure_boot.h> 914 915 #endif /* __T1024RDB_H */ 916