1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 37 /* support deep sleep */ 38 #ifdef CONFIG_PPC_T1024 39 #define CONFIG_DEEP_SLEEP 40 #endif 41 #if defined(CONFIG_DEEP_SLEEP) 42 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_BOARD_EARLY_INIT_F 44 #endif 45 46 #ifdef CONFIG_RAMBOOT_PBL 47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 48 #if defined(CONFIG_T1024RDB) 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 50 #elif defined(CONFIG_T1023RDB) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 52 #endif 53 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 54 #define CONFIG_SPL_ENV_SUPPORT 55 #define CONFIG_SPL_SERIAL_SUPPORT 56 #define CONFIG_SPL_FLUSH_IMAGE 57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 58 #define CONFIG_SPL_LIBGENERIC_SUPPORT 59 #define CONFIG_SPL_LIBCOMMON_SUPPORT 60 #define CONFIG_SPL_I2C_SUPPORT 61 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 #define CONFIG_SYS_TEXT_BASE 0x30001000 64 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 65 #define CONFIG_SPL_PAD_TO 0x40000 66 #define CONFIG_SPL_MAX_SIZE 0x28000 67 #define RESET_VECTOR_OFFSET 0x27FFC 68 #define BOOT_PAGE_OFFSET 0x27000 69 #ifdef CONFIG_SPL_BUILD 70 #define CONFIG_SPL_SKIP_RELOCATE 71 #define CONFIG_SPL_COMMON_INIT_DDR 72 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 73 #define CONFIG_SYS_NO_FLASH 74 #endif 75 76 #ifdef CONFIG_NAND 77 #define CONFIG_SPL_NAND_SUPPORT 78 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 80 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 81 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 83 #define CONFIG_SPL_NAND_BOOT 84 #endif 85 86 #ifdef CONFIG_SPIFLASH 87 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 88 #define CONFIG_SPL_SPI_SUPPORT 89 #define CONFIG_SPL_SPI_FLASH_SUPPORT 90 #define CONFIG_SPL_SPI_FLASH_MINIMAL 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 95 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 96 #ifndef CONFIG_SPL_BUILD 97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 98 #endif 99 #define CONFIG_SPL_SPI_BOOT 100 #endif 101 102 #ifdef CONFIG_SDCARD 103 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 104 #define CONFIG_SPL_MMC_SUPPORT 105 #define CONFIG_SPL_MMC_MINIMAL 106 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 107 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 108 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 109 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 110 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 111 #ifndef CONFIG_SPL_BUILD 112 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 113 #endif 114 #define CONFIG_SPL_MMC_BOOT 115 #endif 116 117 #endif /* CONFIG_RAMBOOT_PBL */ 118 119 #ifndef CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_TEXT_BASE 0xeff40000 121 #endif 122 123 #ifndef CONFIG_RESET_VECTOR_ADDRESS 124 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 125 #endif 126 127 #ifndef CONFIG_SYS_NO_FLASH 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 131 #endif 132 133 /* PCIe Boot - Master */ 134 #define CONFIG_SRIO_PCIE_BOOT_MASTER 135 /* 136 * for slave u-boot IMAGE instored in master memory space, 137 * PHYS must be aligned based on the SIZE 138 */ 139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 141 #ifdef CONFIG_PHYS_64BIT 142 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 143 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 144 #else 145 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 146 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 147 #endif 148 /* 149 * for slave UCODE and ENV instored in master memory space, 150 * PHYS must be aligned based on the SIZE 151 */ 152 #ifdef CONFIG_PHYS_64BIT 153 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 155 #else 156 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 157 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 158 #endif 159 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 160 /* slave core release by master*/ 161 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 162 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 163 164 /* PCIe Boot - Slave */ 165 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 166 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 167 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 168 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 169 /* Set 1M boot space for PCIe boot */ 170 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 171 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 172 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 173 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 174 #define CONFIG_SYS_NO_FLASH 175 #endif 176 177 #if defined(CONFIG_SPIFLASH) 178 #define CONFIG_SYS_EXTRA_ENV_RELOC 179 #define CONFIG_ENV_IS_IN_SPI_FLASH 180 #define CONFIG_ENV_SPI_BUS 0 181 #define CONFIG_ENV_SPI_CS 0 182 #define CONFIG_ENV_SPI_MAX_HZ 10000000 183 #define CONFIG_ENV_SPI_MODE 0 184 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 185 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 186 #if defined(CONFIG_T1024RDB) 187 #define CONFIG_ENV_SECT_SIZE 0x10000 188 #elif defined(CONFIG_T1023RDB) 189 #define CONFIG_ENV_SECT_SIZE 0x40000 190 #endif 191 #elif defined(CONFIG_SDCARD) 192 #define CONFIG_SYS_EXTRA_ENV_RELOC 193 #define CONFIG_ENV_IS_IN_MMC 194 #define CONFIG_SYS_MMC_ENV_DEV 0 195 #define CONFIG_ENV_SIZE 0x2000 196 #define CONFIG_ENV_OFFSET (512 * 0x800) 197 #elif defined(CONFIG_NAND) 198 #define CONFIG_SYS_EXTRA_ENV_RELOC 199 #define CONFIG_ENV_IS_IN_NAND 200 #define CONFIG_ENV_SIZE 0x2000 201 #if defined(CONFIG_T1024RDB) 202 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 203 #elif defined(CONFIG_T1023RDB) 204 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 205 #endif 206 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 207 #define CONFIG_ENV_IS_IN_REMOTE 208 #define CONFIG_ENV_ADDR 0xffe20000 209 #define CONFIG_ENV_SIZE 0x2000 210 #elif defined(CONFIG_ENV_IS_NOWHERE) 211 #define CONFIG_ENV_SIZE 0x2000 212 #else 213 #define CONFIG_ENV_IS_IN_FLASH 214 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 215 #define CONFIG_ENV_SIZE 0x2000 216 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 217 #endif 218 219 #ifndef __ASSEMBLY__ 220 unsigned long get_board_sys_clk(void); 221 unsigned long get_board_ddr_clk(void); 222 #endif 223 224 #define CONFIG_SYS_CLK_FREQ 100000000 225 #define CONFIG_DDR_CLK_FREQ 100000000 226 227 /* 228 * These can be toggled for performance analysis, otherwise use default. 229 */ 230 #define CONFIG_SYS_CACHE_STASHING 231 #define CONFIG_BACKSIDE_L2_CACHE 232 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 233 #define CONFIG_BTB /* toggle branch predition */ 234 #define CONFIG_DDR_ECC 235 #ifdef CONFIG_DDR_ECC 236 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 237 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 238 #endif 239 240 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 241 #define CONFIG_SYS_MEMTEST_END 0x00400000 242 #define CONFIG_SYS_ALT_MEMTEST 243 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 244 245 /* 246 * Config the L3 Cache as L3 SRAM 247 */ 248 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 249 #define CONFIG_SYS_L3_SIZE (256 << 10) 250 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 251 #ifdef CONFIG_RAMBOOT_PBL 252 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 253 #endif 254 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 255 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 256 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 257 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 258 259 #ifdef CONFIG_PHYS_64BIT 260 #define CONFIG_SYS_DCSRBAR 0xf0000000 261 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 262 #endif 263 264 /* EEPROM */ 265 #define CONFIG_ID_EEPROM 266 #define CONFIG_SYS_I2C_EEPROM_NXID 267 #define CONFIG_SYS_EEPROM_BUS_NUM 0 268 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 269 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 270 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 271 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 272 273 /* 274 * DDR Setup 275 */ 276 #define CONFIG_VERY_BIG_RAM 277 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 278 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 279 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 280 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 281 #define CONFIG_FSL_DDR_INTERACTIVE 282 #if defined(CONFIG_T1024RDB) 283 #define CONFIG_DDR_SPD 284 #define CONFIG_SYS_FSL_DDR3 285 #define CONFIG_SYS_SPD_BUS_NUM 0 286 #define SPD_EEPROM_ADDRESS 0x51 287 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 288 #elif defined(CONFIG_T1023RDB) 289 #define CONFIG_SYS_FSL_DDR4 290 #define CONFIG_SYS_DDR_RAW_TIMING 291 #define CONFIG_SYS_SDRAM_SIZE 2048 292 #endif 293 294 /* 295 * IFC Definitions 296 */ 297 #define CONFIG_SYS_FLASH_BASE 0xe8000000 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 300 #else 301 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 302 #endif 303 304 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 305 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 306 CSPR_PORT_SIZE_16 | \ 307 CSPR_MSEL_NOR | \ 308 CSPR_V) 309 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 310 311 /* NOR Flash Timing Params */ 312 #if defined(CONFIG_T1024RDB) 313 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 314 #elif defined(CONFIG_T1023RDB) 315 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 316 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 317 #endif 318 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 319 FTIM0_NOR_TEADC(0x5) | \ 320 FTIM0_NOR_TEAHC(0x5)) 321 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 322 FTIM1_NOR_TRAD_NOR(0x1A) |\ 323 FTIM1_NOR_TSEQRAD_NOR(0x13)) 324 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 325 FTIM2_NOR_TCH(0x4) | \ 326 FTIM2_NOR_TWPH(0x0E) | \ 327 FTIM2_NOR_TWP(0x1c)) 328 #define CONFIG_SYS_NOR_FTIM3 0x0 329 330 #define CONFIG_SYS_FLASH_QUIET_TEST 331 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 332 333 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 334 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 335 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 336 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 337 338 #define CONFIG_SYS_FLASH_EMPTY_INFO 339 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 340 341 #ifdef CONFIG_T1024RDB 342 /* CPLD on IFC */ 343 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 344 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 345 #define CONFIG_SYS_CSPR2_EXT (0xf) 346 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 347 | CSPR_PORT_SIZE_8 \ 348 | CSPR_MSEL_GPCM \ 349 | CSPR_V) 350 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 351 #define CONFIG_SYS_CSOR2 0x0 352 353 /* CPLD Timing parameters for IFC CS2 */ 354 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 355 FTIM0_GPCM_TEADC(0x0e) | \ 356 FTIM0_GPCM_TEAHC(0x0e)) 357 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 358 FTIM1_GPCM_TRAD(0x1f)) 359 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 360 FTIM2_GPCM_TCH(0x8) | \ 361 FTIM2_GPCM_TWP(0x1f)) 362 #define CONFIG_SYS_CS2_FTIM3 0x0 363 #endif 364 365 /* NAND Flash on IFC */ 366 #define CONFIG_NAND_FSL_IFC 367 #define CONFIG_SYS_NAND_BASE 0xff800000 368 #ifdef CONFIG_PHYS_64BIT 369 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 370 #else 371 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 372 #endif 373 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 374 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 375 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 376 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 377 | CSPR_V) 378 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 379 380 #if defined(CONFIG_T1024RDB) 381 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 382 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 383 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 384 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 385 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 386 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 387 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 388 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 389 #elif defined(CONFIG_T1023RDB) 390 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 391 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 392 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 393 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 394 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 395 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 396 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 397 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 398 #endif 399 400 #define CONFIG_SYS_NAND_ONFI_DETECTION 401 /* ONFI NAND Flash mode0 Timing Params */ 402 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 403 FTIM0_NAND_TWP(0x18) | \ 404 FTIM0_NAND_TWCHT(0x07) | \ 405 FTIM0_NAND_TWH(0x0a)) 406 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 407 FTIM1_NAND_TWBE(0x39) | \ 408 FTIM1_NAND_TRR(0x0e) | \ 409 FTIM1_NAND_TRP(0x18)) 410 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 411 FTIM2_NAND_TREH(0x0a) | \ 412 FTIM2_NAND_TWHRE(0x1e)) 413 #define CONFIG_SYS_NAND_FTIM3 0x0 414 415 #define CONFIG_SYS_NAND_DDR_LAW 11 416 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 417 #define CONFIG_SYS_MAX_NAND_DEVICE 1 418 #define CONFIG_CMD_NAND 419 420 #if defined(CONFIG_NAND) 421 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 422 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 423 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 424 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 425 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 426 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 427 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 428 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 429 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 430 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 431 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 432 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 433 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 434 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 435 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 436 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 437 #else 438 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 439 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 440 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 441 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 442 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 443 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 444 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 445 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 446 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 447 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 448 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 449 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 450 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 451 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 452 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 453 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 454 #endif 455 456 #ifdef CONFIG_SPL_BUILD 457 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 458 #else 459 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 460 #endif 461 462 #if defined(CONFIG_RAMBOOT_PBL) 463 #define CONFIG_SYS_RAMBOOT 464 #endif 465 466 #define CONFIG_BOARD_EARLY_INIT_R 467 #define CONFIG_MISC_INIT_R 468 469 #define CONFIG_HWCONFIG 470 471 /* define to use L1 as initial stack */ 472 #define CONFIG_L1_INIT_RAM 473 #define CONFIG_SYS_INIT_RAM_LOCK 474 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 475 #ifdef CONFIG_PHYS_64BIT 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 478 /* The assembler doesn't like typecast */ 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 480 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 481 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 482 #else 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 486 #endif 487 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 488 489 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 490 GENERATED_GBL_DATA_SIZE) 491 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 492 493 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 494 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 495 496 /* Serial Port */ 497 #define CONFIG_CONS_INDEX 1 498 #define CONFIG_SYS_NS16550_SERIAL 499 #define CONFIG_SYS_NS16550_REG_SIZE 1 500 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 501 502 #define CONFIG_SYS_BAUDRATE_TABLE \ 503 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 504 505 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 506 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 507 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 508 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 509 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 510 511 /* Video */ 512 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 513 #ifdef CONFIG_FSL_DIU_FB 514 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 515 #define CONFIG_VIDEO 516 #define CONFIG_CMD_BMP 517 #define CONFIG_CFB_CONSOLE 518 #define CONFIG_VIDEO_SW_CURSOR 519 #define CONFIG_VGA_AS_SINGLE_DEVICE 520 #define CONFIG_VIDEO_LOGO 521 #define CONFIG_VIDEO_BMP_LOGO 522 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 523 /* 524 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 525 * disable empty flash sector detection, which is I/O-intensive. 526 */ 527 #undef CONFIG_SYS_FLASH_EMPTY_INFO 528 #endif 529 530 /* I2C */ 531 #define CONFIG_SYS_I2C 532 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 533 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 534 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 535 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 536 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 537 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 538 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 539 540 #define I2C_PCA6408_BUS_NUM 1 541 #define I2C_PCA6408_ADDR 0x20 542 543 /* I2C bus multiplexer */ 544 #define I2C_MUX_CH_DEFAULT 0x8 545 546 /* 547 * RTC configuration 548 */ 549 #define RTC 550 #define CONFIG_RTC_DS1337 1 551 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 552 553 /* 554 * eSPI - Enhanced SPI 555 */ 556 #define CONFIG_SPI_FLASH_BAR 557 #define CONFIG_SF_DEFAULT_SPEED 10000000 558 #define CONFIG_SF_DEFAULT_MODE 0 559 560 /* 561 * General PCIe 562 * Memory space is mapped 1-1, but I/O space must start from 0. 563 */ 564 #define CONFIG_PCI /* Enable PCI/PCIE */ 565 #define CONFIG_PCIE1 /* PCIE controller 1 */ 566 #define CONFIG_PCIE2 /* PCIE controller 2 */ 567 #define CONFIG_PCIE3 /* PCIE controller 3 */ 568 #ifdef CONFIG_PPC_T1040 569 #define CONFIG_PCIE4 /* PCIE controller 4 */ 570 #endif 571 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 572 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 573 #define CONFIG_PCI_INDIRECT_BRIDGE 574 575 #ifdef CONFIG_PCI 576 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 577 #ifdef CONFIG_PCIE1 578 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 579 #ifdef CONFIG_PHYS_64BIT 580 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 582 #else 583 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 584 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 585 #endif 586 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 587 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 588 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 591 #else 592 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 593 #endif 594 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 595 #endif 596 597 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 598 #ifdef CONFIG_PCIE2 599 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 600 #ifdef CONFIG_PHYS_64BIT 601 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 602 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 603 #else 604 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 605 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 606 #endif 607 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 608 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 609 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 612 #else 613 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 614 #endif 615 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 616 #endif 617 618 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 619 #ifdef CONFIG_PCIE3 620 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 621 #ifdef CONFIG_PHYS_64BIT 622 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 623 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 624 #else 625 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 626 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 627 #endif 628 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 629 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 630 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 631 #ifdef CONFIG_PHYS_64BIT 632 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 633 #else 634 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 635 #endif 636 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 637 #endif 638 639 /* controller 4, Base address 203000, to be removed */ 640 #ifdef CONFIG_PCIE4 641 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 642 #ifdef CONFIG_PHYS_64BIT 643 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 644 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 645 #else 646 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 647 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 648 #endif 649 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 650 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 651 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 652 #ifdef CONFIG_PHYS_64BIT 653 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 654 #else 655 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 656 #endif 657 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 658 #endif 659 660 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 661 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 662 #define CONFIG_DOS_PARTITION 663 #endif /* CONFIG_PCI */ 664 665 /* 666 * USB 667 */ 668 #define CONFIG_HAS_FSL_DR_USB 669 670 #ifdef CONFIG_HAS_FSL_DR_USB 671 #define CONFIG_USB_EHCI 672 #define CONFIG_USB_STORAGE 673 #define CONFIG_USB_EHCI_FSL 674 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 675 #endif 676 677 /* 678 * SDHC 679 */ 680 #define CONFIG_MMC 681 #ifdef CONFIG_MMC 682 #define CONFIG_FSL_ESDHC 683 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 684 #define CONFIG_GENERIC_MMC 685 #define CONFIG_DOS_PARTITION 686 #endif 687 688 /* Qman/Bman */ 689 #ifndef CONFIG_NOBQFMAN 690 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 691 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 692 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 693 #ifdef CONFIG_PHYS_64BIT 694 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 695 #else 696 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 697 #endif 698 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 699 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 700 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 701 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 702 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 703 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 704 CONFIG_SYS_BMAN_CENA_SIZE) 705 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 706 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 707 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 708 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 711 #else 712 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 713 #endif 714 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 715 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 716 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 717 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 718 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 719 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 720 CONFIG_SYS_QMAN_CENA_SIZE) 721 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 722 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 723 724 #define CONFIG_SYS_DPAA_FMAN 725 726 #ifdef CONFIG_T1024RDB 727 #define CONFIG_QE 728 #define CONFIG_U_QE 729 #endif 730 /* Default address of microcode for the Linux FMan driver */ 731 #if defined(CONFIG_SPIFLASH) 732 /* 733 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 734 * env, so we got 0x110000. 735 */ 736 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 737 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 738 #define CONFIG_SYS_QE_FW_ADDR 0x130000 739 #elif defined(CONFIG_SDCARD) 740 /* 741 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 742 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 743 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 744 */ 745 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 746 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 747 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 748 #elif defined(CONFIG_NAND) 749 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 750 #if defined(CONFIG_T1024RDB) 751 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 752 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 753 #elif defined(CONFIG_T1023RDB) 754 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 755 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 756 #endif 757 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 758 /* 759 * Slave has no ucode locally, it can fetch this from remote. When implementing 760 * in two corenet boards, slave's ucode could be stored in master's memory 761 * space, the address can be mapped from slave TLB->slave LAW-> 762 * slave SRIO or PCIE outbound window->master inbound window-> 763 * master LAW->the ucode address in master's memory space. 764 */ 765 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 766 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 767 #else 768 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 769 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 770 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 771 #endif 772 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 773 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 774 #endif /* CONFIG_NOBQFMAN */ 775 776 #ifdef CONFIG_SYS_DPAA_FMAN 777 #define CONFIG_FMAN_ENET 778 #define CONFIG_PHYLIB_10G 779 #define CONFIG_PHY_REALTEK 780 #define CONFIG_PHY_AQUANTIA 781 #if defined(CONFIG_T1024RDB) 782 #define RGMII_PHY1_ADDR 0x2 783 #define RGMII_PHY2_ADDR 0x6 784 #define SGMII_AQR_PHY_ADDR 0x2 785 #define FM1_10GEC1_PHY_ADDR 0x1 786 #elif defined(CONFIG_T1023RDB) 787 #define RGMII_PHY1_ADDR 0x1 788 #define SGMII_RTK_PHY_ADDR 0x3 789 #define SGMII_AQR_PHY_ADDR 0x2 790 #endif 791 #endif 792 793 #ifdef CONFIG_FMAN_ENET 794 #define CONFIG_MII /* MII PHY management */ 795 #define CONFIG_ETHPRIME "FM1@DTSEC4" 796 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 797 #endif 798 799 /* 800 * Dynamic MTD Partition support with mtdparts 801 */ 802 #ifndef CONFIG_SYS_NO_FLASH 803 #define CONFIG_MTD_DEVICE 804 #define CONFIG_MTD_PARTITIONS 805 #define CONFIG_CMD_MTDPARTS 806 #define CONFIG_FLASH_CFI_MTD 807 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 808 "spi0=spife110000.1" 809 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 810 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 811 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 812 "1m(uboot),5m(kernel),128k(dtb),-(user)" 813 #endif 814 815 /* 816 * Environment 817 */ 818 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 819 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 820 821 /* 822 * Command line configuration. 823 */ 824 #define CONFIG_CMD_DATE 825 #define CONFIG_CMD_EEPROM 826 #define CONFIG_CMD_ERRATA 827 #define CONFIG_CMD_IRQ 828 #define CONFIG_CMD_REGINFO 829 830 #ifdef CONFIG_PCI 831 #define CONFIG_CMD_PCI 832 #endif 833 834 /* 835 * Miscellaneous configurable options 836 */ 837 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 838 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 839 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 840 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 841 #ifdef CONFIG_CMD_KGDB 842 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 843 #else 844 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 845 #endif 846 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 847 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 848 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 849 850 /* 851 * For booting Linux, the board info and command line data 852 * have to be in the first 64 MB of memory, since this is 853 * the maximum mapped by the Linux kernel during initialization. 854 */ 855 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 856 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 857 858 #ifdef CONFIG_CMD_KGDB 859 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 860 #endif 861 862 /* 863 * Environment Configuration 864 */ 865 #define CONFIG_ROOTPATH "/opt/nfsroot" 866 #define CONFIG_BOOTFILE "uImage" 867 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 868 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 869 #define CONFIG_BAUDRATE 115200 870 #define __USB_PHY_TYPE utmi 871 872 #ifdef CONFIG_PPC_T1024 873 #define CONFIG_BOARDNAME t1024rdb 874 #define BANK_INTLV cs0_cs1 875 #else 876 #define CONFIG_BOARDNAME t1023rdb 877 #define BANK_INTLV null 878 #endif 879 880 #define CONFIG_EXTRA_ENV_SETTINGS \ 881 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 882 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 883 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 884 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 885 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 886 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 887 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 888 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 889 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 890 "netdev=eth0\0" \ 891 "tftpflash=tftpboot $loadaddr $uboot && " \ 892 "protect off $ubootaddr +$filesize && " \ 893 "erase $ubootaddr +$filesize && " \ 894 "cp.b $loadaddr $ubootaddr $filesize && " \ 895 "protect on $ubootaddr +$filesize && " \ 896 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 897 "consoledev=ttyS0\0" \ 898 "ramdiskaddr=2000000\0" \ 899 "fdtaddr=1e00000\0" \ 900 "bdev=sda3\0" 901 902 #define CONFIG_LINUX \ 903 "setenv bootargs root=/dev/ram rw " \ 904 "console=$consoledev,$baudrate $othbootargs;" \ 905 "setenv ramdiskaddr 0x02000000;" \ 906 "setenv fdtaddr 0x00c00000;" \ 907 "setenv loadaddr 0x1000000;" \ 908 "bootm $loadaddr $ramdiskaddr $fdtaddr" 909 910 #define CONFIG_NFSBOOTCOMMAND \ 911 "setenv bootargs root=/dev/nfs rw " \ 912 "nfsroot=$serverip:$rootpath " \ 913 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 914 "console=$consoledev,$baudrate $othbootargs;" \ 915 "tftp $loadaddr $bootfile;" \ 916 "tftp $fdtaddr $fdtfile;" \ 917 "bootm $loadaddr - $fdtaddr" 918 919 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 920 921 /* Hash command with SHA acceleration supported in hardware */ 922 #ifdef CONFIG_FSL_CAAM 923 #define CONFIG_CMD_HASH 924 #define CONFIG_SHA_HW_ACCEL 925 #endif 926 927 #include <asm/fsl_secure_boot.h> 928 929 #endif /* __T1024RDB_H */ 930