1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 #define CONFIG_BOOKE 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #define CONFIG_E500MC /* BOOKE e500mc family */ 20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 21 #define CONFIG_MP /* support multiple processors */ 22 #define CONFIG_PHYS_64BIT 23 #define CONFIG_ENABLE_36BIT_PHYS 24 25 #ifdef CONFIG_PHYS_64BIT 26 #define CONFIG_ADDR_MAP 1 27 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 28 #endif 29 30 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 31 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 32 #define CONFIG_FSL_IFC /* Enable IFC Support */ 33 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_ENV_OVERWRITE 36 37 /* support deep sleep */ 38 #define CONFIG_DEEP_SLEEP 39 #if defined(CONFIG_DEEP_SLEEP) 40 #define CONFIG_SILENT_CONSOLE 41 #define CONFIG_BOARD_EARLY_INIT_F 42 #endif 43 44 #ifdef CONFIG_RAMBOOT_PBL 45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 46 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 48 #define CONFIG_SPL_ENV_SUPPORT 49 #define CONFIG_SPL_SERIAL_SUPPORT 50 #define CONFIG_SPL_FLUSH_IMAGE 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 #define CONFIG_SPL_LIBGENERIC_SUPPORT 53 #define CONFIG_SPL_LIBCOMMON_SUPPORT 54 #define CONFIG_SPL_I2C_SUPPORT 55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 56 #define CONFIG_FSL_LAW /* Use common FSL init code */ 57 #define CONFIG_SYS_TEXT_BASE 0x30001000 58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 59 #define CONFIG_SPL_PAD_TO 0x40000 60 #define CONFIG_SPL_MAX_SIZE 0x28000 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 #ifdef CONFIG_SPL_BUILD 64 #define CONFIG_SPL_SKIP_RELOCATE 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 67 #define CONFIG_SYS_NO_FLASH 68 #endif 69 70 #ifdef CONFIG_NAND 71 #define CONFIG_SPL_NAND_SUPPORT 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 74 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 77 #define CONFIG_SPL_NAND_BOOT 78 #endif 79 80 #ifdef CONFIG_SPIFLASH 81 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 82 #define CONFIG_SPL_SPI_SUPPORT 83 #define CONFIG_SPL_SPI_FLASH_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #define CONFIG_SPL_SPI_BOOT 94 #endif 95 96 #ifdef CONFIG_SDCARD 97 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 98 #define CONFIG_SPL_MMC_SUPPORT 99 #define CONFIG_SPL_MMC_MINIMAL 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 102 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 105 #ifndef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #endif 108 #define CONFIG_SPL_MMC_BOOT 109 #endif 110 111 #endif /* CONFIG_RAMBOOT_PBL */ 112 113 #ifndef CONFIG_SYS_TEXT_BASE 114 #define CONFIG_SYS_TEXT_BASE 0xeff40000 115 #endif 116 117 #ifndef CONFIG_RESET_VECTOR_ADDRESS 118 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 119 #endif 120 121 #ifndef CONFIG_SYS_NO_FLASH 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 125 #endif 126 127 /* PCIe Boot - Master */ 128 #define CONFIG_SRIO_PCIE_BOOT_MASTER 129 /* 130 * for slave u-boot IMAGE instored in master memory space, 131 * PHYS must be aligned based on the SIZE 132 */ 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 138 #else 139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 141 #endif 142 /* 143 * for slave UCODE and ENV instored in master memory space, 144 * PHYS must be aligned based on the SIZE 145 */ 146 #ifdef CONFIG_PHYS_64BIT 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 149 #else 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 152 #endif 153 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 154 /* slave core release by master*/ 155 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 156 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 157 158 /* PCIe Boot - Slave */ 159 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 162 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 163 /* Set 1M boot space for PCIe boot */ 164 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 165 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 166 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 167 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 168 #define CONFIG_SYS_NO_FLASH 169 #endif 170 171 #if defined(CONFIG_SPIFLASH) 172 #define CONFIG_SYS_EXTRA_ENV_RELOC 173 #define CONFIG_ENV_IS_IN_SPI_FLASH 174 #define CONFIG_ENV_SPI_BUS 0 175 #define CONFIG_ENV_SPI_CS 0 176 #define CONFIG_ENV_SPI_MAX_HZ 10000000 177 #define CONFIG_ENV_SPI_MODE 0 178 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 179 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 180 #define CONFIG_ENV_SECT_SIZE 0x10000 181 #elif defined(CONFIG_SDCARD) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_IS_IN_MMC 184 #define CONFIG_SYS_MMC_ENV_DEV 0 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_OFFSET (512 * 0x800) 187 #elif defined(CONFIG_NAND) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_ENV_IS_IN_NAND 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 192 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 193 #define CONFIG_ENV_IS_IN_REMOTE 194 #define CONFIG_ENV_ADDR 0xffe20000 195 #define CONFIG_ENV_SIZE 0x2000 196 #elif defined(CONFIG_ENV_IS_NOWHERE) 197 #define CONFIG_ENV_SIZE 0x2000 198 #else 199 #define CONFIG_ENV_IS_IN_FLASH 200 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 201 #define CONFIG_ENV_SIZE 0x2000 202 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 203 #endif 204 205 206 #ifndef __ASSEMBLY__ 207 unsigned long get_board_sys_clk(void); 208 unsigned long get_board_ddr_clk(void); 209 #endif 210 211 #define CONFIG_SYS_CLK_FREQ 100000000 212 #define CONFIG_DDR_CLK_FREQ 66660000 213 214 /* 215 * These can be toggled for performance analysis, otherwise use default. 216 */ 217 #define CONFIG_SYS_CACHE_STASHING 218 #define CONFIG_BACKSIDE_L2_CACHE 219 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 220 #define CONFIG_BTB /* toggle branch predition */ 221 #define CONFIG_DDR_ECC 222 #ifdef CONFIG_DDR_ECC 223 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 224 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 225 #endif 226 227 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 228 #define CONFIG_SYS_MEMTEST_END 0x00400000 229 #define CONFIG_SYS_ALT_MEMTEST 230 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 231 232 /* 233 * Config the L3 Cache as L3 SRAM 234 */ 235 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 236 #define CONFIG_SYS_L3_SIZE (256 << 10) 237 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 238 #ifdef CONFIG_RAMBOOT_PBL 239 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 240 #endif 241 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 242 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 243 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 244 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 245 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_SYS_DCSRBAR 0xf0000000 248 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 249 #endif 250 251 /* EEPROM */ 252 #define CONFIG_ID_EEPROM 253 #define CONFIG_SYS_I2C_EEPROM_NXID 254 #define CONFIG_SYS_EEPROM_BUS_NUM 0 255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 259 260 /* 261 * DDR Setup 262 */ 263 #define CONFIG_VERY_BIG_RAM 264 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 265 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 266 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 267 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 268 #define CONFIG_DDR_SPD 269 #define CONFIG_SYS_FSL_DDR3 270 271 #define CONFIG_SYS_SPD_BUS_NUM 0 272 #define SPD_EEPROM_ADDRESS 0x51 273 274 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 275 276 /* 277 * IFC Definitions 278 */ 279 #define CONFIG_SYS_FLASH_BASE 0xe8000000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 282 #else 283 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 284 #endif 285 286 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 287 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 288 CSPR_PORT_SIZE_16 | \ 289 CSPR_MSEL_NOR | \ 290 CSPR_V) 291 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 292 293 /* NOR Flash Timing Params */ 294 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 295 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 296 FTIM0_NOR_TEADC(0x5) | \ 297 FTIM0_NOR_TEAHC(0x5)) 298 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 299 FTIM1_NOR_TRAD_NOR(0x1A) |\ 300 FTIM1_NOR_TSEQRAD_NOR(0x13)) 301 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 302 FTIM2_NOR_TCH(0x4) | \ 303 FTIM2_NOR_TWPH(0x0E) | \ 304 FTIM2_NOR_TWP(0x1c)) 305 #define CONFIG_SYS_NOR_FTIM3 0x0 306 307 #define CONFIG_SYS_FLASH_QUIET_TEST 308 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 309 310 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 311 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 312 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 313 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 314 315 #define CONFIG_SYS_FLASH_EMPTY_INFO 316 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 317 318 /* CPLD on IFC */ 319 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 320 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 321 #define CONFIG_SYS_CSPR2_EXT (0xf) 322 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 323 | CSPR_PORT_SIZE_8 \ 324 | CSPR_MSEL_GPCM \ 325 | CSPR_V) 326 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 327 #define CONFIG_SYS_CSOR2 0x0 328 329 /* CPLD Timing parameters for IFC CS2 */ 330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 331 FTIM0_GPCM_TEADC(0x0e) | \ 332 FTIM0_GPCM_TEAHC(0x0e)) 333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 334 FTIM1_GPCM_TRAD(0x1f)) 335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 336 FTIM2_GPCM_TCH(0x8) | \ 337 FTIM2_GPCM_TWP(0x1f)) 338 #define CONFIG_SYS_CS2_FTIM3 0x0 339 340 /* NAND Flash on IFC */ 341 #define CONFIG_NAND_FSL_IFC 342 #define CONFIG_SYS_NAND_BASE 0xff800000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 345 #else 346 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 347 #endif 348 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 349 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 350 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 351 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 352 | CSPR_V) 353 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 354 355 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 356 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 357 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 358 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 359 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 360 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 361 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 362 363 #define CONFIG_SYS_NAND_ONFI_DETECTION 364 365 /* ONFI NAND Flash mode0 Timing Params */ 366 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 367 FTIM0_NAND_TWP(0x18) | \ 368 FTIM0_NAND_TWCHT(0x07) | \ 369 FTIM0_NAND_TWH(0x0a)) 370 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 371 FTIM1_NAND_TWBE(0x39) | \ 372 FTIM1_NAND_TRR(0x0e) | \ 373 FTIM1_NAND_TRP(0x18)) 374 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 375 FTIM2_NAND_TREH(0x0a) | \ 376 FTIM2_NAND_TWHRE(0x1e)) 377 #define CONFIG_SYS_NAND_FTIM3 0x0 378 379 #define CONFIG_SYS_NAND_DDR_LAW 11 380 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 381 #define CONFIG_SYS_MAX_NAND_DEVICE 1 382 #define CONFIG_MTD_NAND_VERIFY_WRITE 383 #define CONFIG_CMD_NAND 384 385 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 386 387 #if defined(CONFIG_NAND) 388 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 389 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 390 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 391 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 392 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 393 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 394 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 395 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 396 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 397 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 398 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 399 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 400 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 401 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 402 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 403 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 404 #else 405 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 406 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 407 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 421 #endif 422 423 #ifdef CONFIG_SPL_BUILD 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 425 #else 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 427 #endif 428 429 #if defined(CONFIG_RAMBOOT_PBL) 430 #define CONFIG_SYS_RAMBOOT 431 #endif 432 433 #define CONFIG_BOARD_EARLY_INIT_R 434 #define CONFIG_MISC_INIT_R 435 436 #define CONFIG_HWCONFIG 437 438 /* define to use L1 as initial stack */ 439 #define CONFIG_L1_INIT_RAM 440 #define CONFIG_SYS_INIT_RAM_LOCK 441 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 445 /* The assembler doesn't like typecast */ 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 447 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 448 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 449 #else 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 453 #endif 454 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 455 456 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 457 GENERATED_GBL_DATA_SIZE) 458 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 459 460 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 461 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 462 463 /* Serial Port */ 464 #define CONFIG_CONS_INDEX 1 465 #define CONFIG_SYS_NS16550 466 #define CONFIG_SYS_NS16550_SERIAL 467 #define CONFIG_SYS_NS16550_REG_SIZE 1 468 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 469 470 #define CONFIG_SYS_BAUDRATE_TABLE \ 471 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 472 473 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 474 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 475 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 476 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 477 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 478 479 /* Use the HUSH parser */ 480 #define CONFIG_SYS_HUSH_PARSER 481 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 482 483 /* Video */ 484 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 485 #ifdef CONFIG_FSL_DIU_FB 486 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 487 #define CONFIG_VIDEO 488 #define CONFIG_CMD_BMP 489 #define CONFIG_CFB_CONSOLE 490 #define CONFIG_VIDEO_SW_CURSOR 491 #define CONFIG_VGA_AS_SINGLE_DEVICE 492 #define CONFIG_VIDEO_LOGO 493 #define CONFIG_VIDEO_BMP_LOGO 494 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 495 /* 496 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 497 * disable empty flash sector detection, which is I/O-intensive. 498 */ 499 #undef CONFIG_SYS_FLASH_EMPTY_INFO 500 #endif 501 502 /* pass open firmware flat tree */ 503 #define CONFIG_OF_LIBFDT 504 #define CONFIG_OF_BOARD_SETUP 505 #define CONFIG_OF_STDOUT_VIA_ALIAS 506 507 /* new uImage format support */ 508 #define CONFIG_FIT 509 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 510 511 /* I2C */ 512 #define CONFIG_SYS_I2C 513 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 514 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 515 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 517 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 519 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 520 521 #define I2C_MUX_PCA_ADDR 0x77 522 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 523 524 525 /* I2C bus multiplexer */ 526 #define I2C_MUX_CH_DEFAULT 0x8 527 528 /* 529 * RTC configuration 530 */ 531 #define RTC 532 #define CONFIG_RTC_DS1337 1 533 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 534 535 /* 536 * eSPI - Enhanced SPI 537 */ 538 #define CONFIG_FSL_ESPI 539 #define CONFIG_SPI_FLASH 540 #define CONFIG_SPI_FLASH_STMICRO 541 #define CONFIG_CMD_SF 542 #define CONFIG_SPI_FLASH_BAR 543 #define CONFIG_SF_DEFAULT_SPEED 10000000 544 #define CONFIG_SF_DEFAULT_MODE 0 545 546 /* 547 * General PCIe 548 * Memory space is mapped 1-1, but I/O space must start from 0. 549 */ 550 #define CONFIG_PCI /* Enable PCI/PCIE */ 551 #define CONFIG_PCIE1 /* PCIE controler 1 */ 552 #define CONFIG_PCIE2 /* PCIE controler 2 */ 553 #define CONFIG_PCIE3 /* PCIE controler 3 */ 554 #ifdef CONFIG_PPC_T1040 555 #define CONFIG_PCIE4 /* PCIE controler 4 */ 556 #endif 557 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 558 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 559 #define CONFIG_PCI_INDIRECT_BRIDGE 560 561 #ifdef CONFIG_PCI 562 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 563 #ifdef CONFIG_PCIE1 564 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 565 #ifdef CONFIG_PHYS_64BIT 566 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 568 #else 569 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 570 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 571 #endif 572 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 573 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 574 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 575 #ifdef CONFIG_PHYS_64BIT 576 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 577 #else 578 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 579 #endif 580 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 581 #endif 582 583 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 584 #ifdef CONFIG_PCIE2 585 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 586 #ifdef CONFIG_PHYS_64BIT 587 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 588 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 589 #else 590 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 591 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 592 #endif 593 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 594 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 595 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 596 #ifdef CONFIG_PHYS_64BIT 597 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 598 #else 599 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 600 #endif 601 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 602 #endif 603 604 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 605 #ifdef CONFIG_PCIE3 606 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 607 #ifdef CONFIG_PHYS_64BIT 608 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 609 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 610 #else 611 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 612 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 613 #endif 614 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 615 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 616 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 617 #ifdef CONFIG_PHYS_64BIT 618 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 619 #else 620 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 621 #endif 622 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 623 #endif 624 625 /* controller 4, Base address 203000, to be removed */ 626 #ifdef CONFIG_PCIE4 627 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 628 #ifdef CONFIG_PHYS_64BIT 629 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 630 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 631 #else 632 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 633 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 634 #endif 635 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 636 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 637 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 638 #ifdef CONFIG_PHYS_64BIT 639 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 640 #else 641 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 642 #endif 643 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 644 #endif 645 646 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 647 #define CONFIG_E1000 648 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 649 #define CONFIG_DOS_PARTITION 650 #endif /* CONFIG_PCI */ 651 652 /* 653 * USB 654 */ 655 #define CONFIG_HAS_FSL_DR_USB 656 657 #ifdef CONFIG_HAS_FSL_DR_USB 658 #define CONFIG_USB_EHCI 659 #define CONFIG_CMD_USB 660 #define CONFIG_USB_STORAGE 661 #define CONFIG_USB_EHCI_FSL 662 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 663 #define CONFIG_CMD_EXT2 664 #endif 665 666 /* 667 * SDHC 668 */ 669 #define CONFIG_MMC 670 #ifdef CONFIG_MMC 671 #define CONFIG_FSL_ESDHC 672 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 673 #define CONFIG_CMD_MMC 674 #define CONFIG_GENERIC_MMC 675 #define CONFIG_CMD_EXT2 676 #define CONFIG_CMD_FAT 677 #define CONFIG_DOS_PARTITION 678 #endif 679 680 /* Qman/Bman */ 681 #ifndef CONFIG_NOBQFMAN 682 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 683 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 684 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 685 #ifdef CONFIG_PHYS_64BIT 686 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 687 #else 688 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 689 #endif 690 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 691 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 692 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 693 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 694 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 695 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 696 CONFIG_SYS_BMAN_CENA_SIZE) 697 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 698 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 699 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 700 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 701 #ifdef CONFIG_PHYS_64BIT 702 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 703 #else 704 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 705 #endif 706 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 707 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 708 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 709 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 710 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 711 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 712 CONFIG_SYS_QMAN_CENA_SIZE) 713 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 714 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 715 716 #define CONFIG_SYS_DPAA_FMAN 717 718 #define CONFIG_QE 719 #define CONFIG_U_QE 720 /* Default address of microcode for the Linux FMan driver */ 721 #if defined(CONFIG_SPIFLASH) 722 /* 723 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 724 * env, so we got 0x110000. 725 */ 726 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 727 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 728 #define CONFIG_SYS_QE_FW_ADDR 0x130000 729 #elif defined(CONFIG_SDCARD) 730 /* 731 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 732 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 733 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 734 */ 735 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 736 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 737 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 738 #elif defined(CONFIG_NAND) 739 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 740 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 741 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 742 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 743 /* 744 * Slave has no ucode locally, it can fetch this from remote. When implementing 745 * in two corenet boards, slave's ucode could be stored in master's memory 746 * space, the address can be mapped from slave TLB->slave LAW-> 747 * slave SRIO or PCIE outbound window->master inbound window-> 748 * master LAW->the ucode address in master's memory space. 749 */ 750 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 751 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 752 #else 753 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 754 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 755 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 756 #endif 757 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 758 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 759 #endif /* CONFIG_NOBQFMAN */ 760 761 #ifdef CONFIG_SYS_DPAA_FMAN 762 #define CONFIG_FMAN_ENET 763 #define CONFIG_PHYLIB_10G 764 #define CONFIG_PHY_REALTEK 765 #define CONFIG_PHY_AQUANTIA 766 #define RGMII_PHY1_ADDR 0x2 767 #define RGMII_PHY2_ADDR 0x6 768 #define SGMII_PHY1_ADDR 0x2 769 #define FM1_10GEC1_PHY_ADDR 0x1 770 #endif 771 772 #ifdef CONFIG_FMAN_ENET 773 #define CONFIG_MII /* MII PHY management */ 774 #define CONFIG_ETHPRIME "FM1@DTSEC4" 775 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 776 #endif 777 778 /* 779 * Dynamic MTD Partition support with mtdparts 780 */ 781 #ifndef CONFIG_SYS_NO_FLASH 782 #define CONFIG_MTD_DEVICE 783 #define CONFIG_MTD_PARTITIONS 784 #define CONFIG_CMD_MTDPARTS 785 #define CONFIG_FLASH_CFI_MTD 786 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 787 "spi0=spife110000.1" 788 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 789 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 790 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 791 "1m(uboot),5m(kernel),128k(dtb),-(user)" 792 #endif 793 794 /* 795 * Environment 796 */ 797 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 798 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 799 800 /* 801 * Command line configuration. 802 */ 803 #include <config_cmd_default.h> 804 805 #define CONFIG_CMD_DATE 806 #define CONFIG_CMD_DHCP 807 #define CONFIG_CMD_EEPROM 808 #define CONFIG_CMD_ELF 809 #define CONFIG_CMD_ERRATA 810 #define CONFIG_CMD_GREPENV 811 #define CONFIG_CMD_IRQ 812 #define CONFIG_CMD_I2C 813 #define CONFIG_CMD_MII 814 #define CONFIG_CMD_PING 815 #define CONFIG_CMD_ECHO 816 #define CONFIG_CMD_REGINFO 817 #define CONFIG_CMD_SETEXPR 818 #define CONFIG_CMD_BDI 819 820 #ifdef CONFIG_PCI 821 #define CONFIG_CMD_PCI 822 #define CONFIG_CMD_NET 823 #endif 824 825 /* 826 * Miscellaneous configurable options 827 */ 828 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 829 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 830 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 831 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 832 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 835 #else 836 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 837 #endif 838 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 839 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 840 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 841 842 /* 843 * For booting Linux, the board info and command line data 844 * have to be in the first 64 MB of memory, since this is 845 * the maximum mapped by the Linux kernel during initialization. 846 */ 847 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 848 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 849 850 #ifdef CONFIG_CMD_KGDB 851 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 852 #endif 853 854 /* 855 * Environment Configuration 856 */ 857 #define CONFIG_ROOTPATH "/opt/nfsroot" 858 #define CONFIG_BOOTFILE "uImage" 859 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 860 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 861 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 862 #define CONFIG_BAUDRATE 115200 863 #define __USB_PHY_TYPE utmi 864 865 #ifdef CONFIG_PPC_T1024 866 #define CONFIG_BOARDNAME "t1024rdb" 867 #else 868 #define CONFIG_BOARDNAME "t1023rdb" 869 #endif 870 871 #define CONFIG_EXTRA_ENV_SETTINGS \ 872 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 873 "bank_intlv=cs0_cs1\0" \ 874 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 875 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 876 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 877 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 878 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 879 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 880 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 881 "netdev=eth0\0" \ 882 "tftpflash=tftpboot $loadaddr $uboot && " \ 883 "protect off $ubootaddr +$filesize && " \ 884 "erase $ubootaddr +$filesize && " \ 885 "cp.b $loadaddr $ubootaddr $filesize && " \ 886 "protect on $ubootaddr +$filesize && " \ 887 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 888 "consoledev=ttyS0\0" \ 889 "ramdiskaddr=2000000\0" \ 890 "fdtaddr=c00000\0" \ 891 "bdev=sda3\0" 892 893 #define CONFIG_LINUX \ 894 "setenv bootargs root=/dev/ram rw " \ 895 "console=$consoledev,$baudrate $othbootargs;" \ 896 "setenv ramdiskaddr 0x02000000;" \ 897 "setenv fdtaddr 0x00c00000;" \ 898 "setenv loadaddr 0x1000000;" \ 899 "bootm $loadaddr $ramdiskaddr $fdtaddr" 900 901 902 #define CONFIG_NFSBOOTCOMMAND \ 903 "setenv bootargs root=/dev/nfs rw " \ 904 "nfsroot=$serverip:$rootpath " \ 905 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 906 "console=$consoledev,$baudrate $othbootargs;" \ 907 "tftp $loadaddr $bootfile;" \ 908 "tftp $fdtaddr $fdtfile;" \ 909 "bootm $loadaddr - $fdtaddr" 910 911 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 912 913 #ifdef CONFIG_SECURE_BOOT 914 #include <asm/fsl_secure_boot.h> 915 #endif 916 917 #endif /* __T1024RDB_H */ 918