1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 /* support deep sleep */ 30 #ifdef CONFIG_ARCH_T1024 31 #define CONFIG_DEEP_SLEEP 32 #endif 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_SKIP_RELOCATE 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 47 #endif 48 49 #ifdef CONFIG_NAND 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #if defined(CONFIG_TARGET_T1024RDB) 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 57 #elif defined(CONFIG_TARGET_T1023RDB) 58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 59 #endif 60 #define CONFIG_SPL_NAND_BOOT 61 #endif 62 63 #ifdef CONFIG_SPIFLASH 64 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 65 #define CONFIG_SPL_SPI_FLASH_MINIMAL 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #ifndef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 73 #endif 74 #if defined(CONFIG_TARGET_T1024RDB) 75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 76 #elif defined(CONFIG_TARGET_T1023RDB) 77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 78 #endif 79 #define CONFIG_SPL_SPI_BOOT 80 #endif 81 82 #ifdef CONFIG_SDCARD 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 85 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 86 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 87 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 89 #ifndef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 91 #endif 92 #if defined(CONFIG_TARGET_T1024RDB) 93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 94 #elif defined(CONFIG_TARGET_T1023RDB) 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 96 #endif 97 #define CONFIG_SPL_MMC_BOOT 98 #endif 99 100 #endif /* CONFIG_RAMBOOT_PBL */ 101 102 #ifndef CONFIG_RESET_VECTOR_ADDRESS 103 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 104 #endif 105 106 #ifdef CONFIG_MTD_NOR_FLASH 107 #define CONFIG_FLASH_CFI_DRIVER 108 #define CONFIG_SYS_FLASH_CFI 109 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 110 #endif 111 112 /* PCIe Boot - Master */ 113 #define CONFIG_SRIO_PCIE_BOOT_MASTER 114 /* 115 * for slave u-boot IMAGE instored in master memory space, 116 * PHYS must be aligned based on the SIZE 117 */ 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 123 #else 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 126 #endif 127 /* 128 * for slave UCODE and ENV instored in master memory space, 129 * PHYS must be aligned based on the SIZE 130 */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 134 #else 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 137 #endif 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 139 /* slave core release by master*/ 140 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 141 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 142 143 /* PCIe Boot - Slave */ 144 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 145 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 146 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 147 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 148 /* Set 1M boot space for PCIe boot */ 149 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 151 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 152 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 153 #endif 154 155 #if defined(CONFIG_SPIFLASH) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_ENV_SPI_BUS 0 158 #define CONFIG_ENV_SPI_CS 0 159 #define CONFIG_ENV_SPI_MAX_HZ 10000000 160 #define CONFIG_ENV_SPI_MODE 0 161 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 162 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 163 #if defined(CONFIG_TARGET_T1024RDB) 164 #define CONFIG_ENV_SECT_SIZE 0x10000 165 #elif defined(CONFIG_TARGET_T1023RDB) 166 #define CONFIG_ENV_SECT_SIZE 0x40000 167 #endif 168 #elif defined(CONFIG_SDCARD) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_SYS_MMC_ENV_DEV 0 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_OFFSET (512 * 0x800) 173 #elif defined(CONFIG_NAND) 174 #define CONFIG_SYS_EXTRA_ENV_RELOC 175 #define CONFIG_ENV_SIZE 0x2000 176 #if defined(CONFIG_TARGET_T1024RDB) 177 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 178 #elif defined(CONFIG_TARGET_T1023RDB) 179 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 180 #endif 181 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 182 #define CONFIG_ENV_ADDR 0xffe20000 183 #define CONFIG_ENV_SIZE 0x2000 184 #elif defined(CONFIG_ENV_IS_NOWHERE) 185 #define CONFIG_ENV_SIZE 0x2000 186 #else 187 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 188 #define CONFIG_ENV_SIZE 0x2000 189 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 190 #endif 191 192 #ifndef __ASSEMBLY__ 193 unsigned long get_board_sys_clk(void); 194 unsigned long get_board_ddr_clk(void); 195 #endif 196 197 #define CONFIG_SYS_CLK_FREQ 100000000 198 #define CONFIG_DDR_CLK_FREQ 100000000 199 200 /* 201 * These can be toggled for performance analysis, otherwise use default. 202 */ 203 #define CONFIG_SYS_CACHE_STASHING 204 #define CONFIG_BACKSIDE_L2_CACHE 205 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 206 #define CONFIG_BTB /* toggle branch predition */ 207 #define CONFIG_DDR_ECC 208 #ifdef CONFIG_DDR_ECC 209 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 210 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 211 #endif 212 213 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 214 #define CONFIG_SYS_MEMTEST_END 0x00400000 215 216 /* 217 * Config the L3 Cache as L3 SRAM 218 */ 219 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 220 #define CONFIG_SYS_L3_SIZE (256 << 10) 221 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 222 #ifdef CONFIG_RAMBOOT_PBL 223 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 224 #endif 225 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 226 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 227 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 228 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 229 230 #ifdef CONFIG_PHYS_64BIT 231 #define CONFIG_SYS_DCSRBAR 0xf0000000 232 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 233 #endif 234 235 /* EEPROM */ 236 #define CONFIG_ID_EEPROM 237 #define CONFIG_SYS_I2C_EEPROM_NXID 238 #define CONFIG_SYS_EEPROM_BUS_NUM 0 239 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 240 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 243 244 /* 245 * DDR Setup 246 */ 247 #define CONFIG_VERY_BIG_RAM 248 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 249 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 250 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 251 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 252 #define CONFIG_FSL_DDR_INTERACTIVE 253 #if defined(CONFIG_TARGET_T1024RDB) 254 #define CONFIG_DDR_SPD 255 #define CONFIG_SYS_SPD_BUS_NUM 0 256 #define SPD_EEPROM_ADDRESS 0x51 257 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 258 #elif defined(CONFIG_TARGET_T1023RDB) 259 #define CONFIG_SYS_DDR_RAW_TIMING 260 #define CONFIG_SYS_SDRAM_SIZE 2048 261 #endif 262 263 /* 264 * IFC Definitions 265 */ 266 #define CONFIG_SYS_FLASH_BASE 0xe8000000 267 #ifdef CONFIG_PHYS_64BIT 268 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 269 #else 270 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 271 #endif 272 273 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 274 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 275 CSPR_PORT_SIZE_16 | \ 276 CSPR_MSEL_NOR | \ 277 CSPR_V) 278 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 279 280 /* NOR Flash Timing Params */ 281 #if defined(CONFIG_TARGET_T1024RDB) 282 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 283 #elif defined(CONFIG_TARGET_T1023RDB) 284 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 285 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 286 #endif 287 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 288 FTIM0_NOR_TEADC(0x5) | \ 289 FTIM0_NOR_TEAHC(0x5)) 290 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 291 FTIM1_NOR_TRAD_NOR(0x1A) |\ 292 FTIM1_NOR_TSEQRAD_NOR(0x13)) 293 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 294 FTIM2_NOR_TCH(0x4) | \ 295 FTIM2_NOR_TWPH(0x0E) | \ 296 FTIM2_NOR_TWP(0x1c)) 297 #define CONFIG_SYS_NOR_FTIM3 0x0 298 299 #define CONFIG_SYS_FLASH_QUIET_TEST 300 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 301 302 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 303 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 304 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 305 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 306 307 #define CONFIG_SYS_FLASH_EMPTY_INFO 308 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 309 310 #ifdef CONFIG_TARGET_T1024RDB 311 /* CPLD on IFC */ 312 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 313 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 314 #define CONFIG_SYS_CSPR2_EXT (0xf) 315 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 316 | CSPR_PORT_SIZE_8 \ 317 | CSPR_MSEL_GPCM \ 318 | CSPR_V) 319 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 320 #define CONFIG_SYS_CSOR2 0x0 321 322 /* CPLD Timing parameters for IFC CS2 */ 323 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 324 FTIM0_GPCM_TEADC(0x0e) | \ 325 FTIM0_GPCM_TEAHC(0x0e)) 326 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 327 FTIM1_GPCM_TRAD(0x1f)) 328 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 329 FTIM2_GPCM_TCH(0x8) | \ 330 FTIM2_GPCM_TWP(0x1f)) 331 #define CONFIG_SYS_CS2_FTIM3 0x0 332 #endif 333 334 /* NAND Flash on IFC */ 335 #define CONFIG_NAND_FSL_IFC 336 #define CONFIG_SYS_NAND_BASE 0xff800000 337 #ifdef CONFIG_PHYS_64BIT 338 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 339 #else 340 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 341 #endif 342 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 343 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 344 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 345 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 346 | CSPR_V) 347 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 348 349 #if defined(CONFIG_TARGET_T1024RDB) 350 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 351 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 352 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 353 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 354 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 355 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 356 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 357 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 358 #elif defined(CONFIG_TARGET_T1023RDB) 359 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 360 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 361 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 362 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 363 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 364 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 365 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 366 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 367 #endif 368 369 #define CONFIG_SYS_NAND_ONFI_DETECTION 370 /* ONFI NAND Flash mode0 Timing Params */ 371 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 372 FTIM0_NAND_TWP(0x18) | \ 373 FTIM0_NAND_TWCHT(0x07) | \ 374 FTIM0_NAND_TWH(0x0a)) 375 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 376 FTIM1_NAND_TWBE(0x39) | \ 377 FTIM1_NAND_TRR(0x0e) | \ 378 FTIM1_NAND_TRP(0x18)) 379 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 380 FTIM2_NAND_TREH(0x0a) | \ 381 FTIM2_NAND_TWHRE(0x1e)) 382 #define CONFIG_SYS_NAND_FTIM3 0x0 383 384 #define CONFIG_SYS_NAND_DDR_LAW 11 385 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 386 #define CONFIG_SYS_MAX_NAND_DEVICE 1 387 388 #if defined(CONFIG_NAND) 389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 397 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #else 406 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 414 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 415 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 416 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 417 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 418 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 419 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 420 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 421 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 422 #endif 423 424 #ifdef CONFIG_SPL_BUILD 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 426 #else 427 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 428 #endif 429 430 #if defined(CONFIG_RAMBOOT_PBL) 431 #define CONFIG_SYS_RAMBOOT 432 #endif 433 434 #define CONFIG_MISC_INIT_R 435 436 #define CONFIG_HWCONFIG 437 438 /* define to use L1 as initial stack */ 439 #define CONFIG_L1_INIT_RAM 440 #define CONFIG_SYS_INIT_RAM_LOCK 441 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 445 /* The assembler doesn't like typecast */ 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 447 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 448 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 449 #else 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 453 #endif 454 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 455 456 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 457 GENERATED_GBL_DATA_SIZE) 458 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 459 460 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 461 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 462 463 /* Serial Port */ 464 #define CONFIG_SYS_NS16550_SERIAL 465 #define CONFIG_SYS_NS16550_REG_SIZE 1 466 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 467 468 #define CONFIG_SYS_BAUDRATE_TABLE \ 469 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 470 471 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 472 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 473 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 474 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 475 476 /* Video */ 477 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 478 #ifdef CONFIG_FSL_DIU_FB 479 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 480 #define CONFIG_VIDEO_LOGO 481 #define CONFIG_VIDEO_BMP_LOGO 482 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 483 /* 484 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 485 * disable empty flash sector detection, which is I/O-intensive. 486 */ 487 #undef CONFIG_SYS_FLASH_EMPTY_INFO 488 #endif 489 490 /* I2C */ 491 #define CONFIG_SYS_I2C 492 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 493 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 494 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 495 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 496 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 497 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 498 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 499 500 #define I2C_PCA6408_BUS_NUM 1 501 #define I2C_PCA6408_ADDR 0x20 502 503 /* I2C bus multiplexer */ 504 #define I2C_MUX_CH_DEFAULT 0x8 505 506 /* 507 * RTC configuration 508 */ 509 #define RTC 510 #define CONFIG_RTC_DS1337 1 511 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 512 513 /* 514 * eSPI - Enhanced SPI 515 */ 516 #define CONFIG_SPI_FLASH_BAR 517 #define CONFIG_SF_DEFAULT_SPEED 10000000 518 #define CONFIG_SF_DEFAULT_MODE 0 519 520 /* 521 * General PCIe 522 * Memory space is mapped 1-1, but I/O space must start from 0. 523 */ 524 #define CONFIG_PCIE1 /* PCIE controller 1 */ 525 #define CONFIG_PCIE2 /* PCIE controller 2 */ 526 #define CONFIG_PCIE3 /* PCIE controller 3 */ 527 #ifdef CONFIG_ARCH_T1040 528 #define CONFIG_PCIE4 /* PCIE controller 4 */ 529 #endif 530 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 531 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 532 #define CONFIG_PCI_INDIRECT_BRIDGE 533 534 #ifdef CONFIG_PCI 535 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 536 #ifdef CONFIG_PCIE1 537 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 540 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 541 #else 542 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 543 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 544 #endif 545 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 546 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 547 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 550 #else 551 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 552 #endif 553 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 554 #endif 555 556 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 557 #ifdef CONFIG_PCIE2 558 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 562 #else 563 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 564 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 565 #endif 566 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 568 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 569 #ifdef CONFIG_PHYS_64BIT 570 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 571 #else 572 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 573 #endif 574 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 575 #endif 576 577 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 578 #ifdef CONFIG_PCIE3 579 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 583 #else 584 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 585 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 586 #endif 587 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 589 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 592 #else 593 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 594 #endif 595 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 4, Base address 203000, to be removed */ 599 #ifdef CONFIG_PCIE4 600 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 604 #else 605 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 606 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 607 #endif 608 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 610 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 611 #ifdef CONFIG_PHYS_64BIT 612 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 613 #else 614 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 615 #endif 616 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 617 #endif 618 619 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 620 #endif /* CONFIG_PCI */ 621 622 /* 623 * USB 624 */ 625 #define CONFIG_HAS_FSL_DR_USB 626 627 #ifdef CONFIG_HAS_FSL_DR_USB 628 #define CONFIG_USB_EHCI_FSL 629 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 630 #endif 631 632 /* 633 * SDHC 634 */ 635 #ifdef CONFIG_MMC 636 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 637 #endif 638 639 /* Qman/Bman */ 640 #ifndef CONFIG_NOBQFMAN 641 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 642 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 643 #ifdef CONFIG_PHYS_64BIT 644 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 645 #else 646 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 647 #endif 648 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 649 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 650 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 651 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 652 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 653 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 654 CONFIG_SYS_BMAN_CENA_SIZE) 655 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 656 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 657 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 658 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 659 #ifdef CONFIG_PHYS_64BIT 660 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 661 #else 662 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 663 #endif 664 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 665 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 666 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 667 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 668 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 669 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 670 CONFIG_SYS_QMAN_CENA_SIZE) 671 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 672 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 673 674 #define CONFIG_SYS_DPAA_FMAN 675 676 #ifdef CONFIG_TARGET_T1024RDB 677 #define CONFIG_QE 678 #define CONFIG_U_QE 679 #endif 680 /* Default address of microcode for the Linux FMan driver */ 681 #if defined(CONFIG_SPIFLASH) 682 /* 683 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 684 * env, so we got 0x110000. 685 */ 686 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 687 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 688 #define CONFIG_SYS_QE_FW_ADDR 0x130000 689 #elif defined(CONFIG_SDCARD) 690 /* 691 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 692 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 693 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 694 */ 695 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 696 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 697 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 698 #elif defined(CONFIG_NAND) 699 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 700 #if defined(CONFIG_TARGET_T1024RDB) 701 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 702 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 703 #elif defined(CONFIG_TARGET_T1023RDB) 704 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 705 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 706 #endif 707 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 708 /* 709 * Slave has no ucode locally, it can fetch this from remote. When implementing 710 * in two corenet boards, slave's ucode could be stored in master's memory 711 * space, the address can be mapped from slave TLB->slave LAW-> 712 * slave SRIO or PCIE outbound window->master inbound window-> 713 * master LAW->the ucode address in master's memory space. 714 */ 715 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 716 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 717 #else 718 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 719 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 720 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 721 #endif 722 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 723 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 724 #endif /* CONFIG_NOBQFMAN */ 725 726 #ifdef CONFIG_SYS_DPAA_FMAN 727 #define CONFIG_FMAN_ENET 728 #define CONFIG_PHYLIB_10G 729 #define CONFIG_PHY_REALTEK 730 #define CONFIG_PHY_AQUANTIA 731 #if defined(CONFIG_TARGET_T1024RDB) 732 #define RGMII_PHY1_ADDR 0x2 733 #define RGMII_PHY2_ADDR 0x6 734 #define SGMII_AQR_PHY_ADDR 0x2 735 #define FM1_10GEC1_PHY_ADDR 0x1 736 #elif defined(CONFIG_TARGET_T1023RDB) 737 #define RGMII_PHY1_ADDR 0x1 738 #define SGMII_RTK_PHY_ADDR 0x3 739 #define SGMII_AQR_PHY_ADDR 0x2 740 #endif 741 #endif 742 743 #ifdef CONFIG_FMAN_ENET 744 #define CONFIG_MII /* MII PHY management */ 745 #define CONFIG_ETHPRIME "FM1@DTSEC4" 746 #endif 747 748 /* 749 * Dynamic MTD Partition support with mtdparts 750 */ 751 #ifdef CONFIG_MTD_NOR_FLASH 752 #define CONFIG_MTD_DEVICE 753 #define CONFIG_MTD_PARTITIONS 754 #define CONFIG_FLASH_CFI_MTD 755 #endif 756 757 /* 758 * Environment 759 */ 760 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 761 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 762 763 /* 764 * Miscellaneous configurable options 765 */ 766 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 767 768 /* 769 * For booting Linux, the board info and command line data 770 * have to be in the first 64 MB of memory, since this is 771 * the maximum mapped by the Linux kernel during initialization. 772 */ 773 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 774 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 775 776 #ifdef CONFIG_CMD_KGDB 777 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 778 #endif 779 780 /* 781 * Environment Configuration 782 */ 783 #define CONFIG_ROOTPATH "/opt/nfsroot" 784 #define CONFIG_BOOTFILE "uImage" 785 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 786 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 787 #define __USB_PHY_TYPE utmi 788 789 #ifdef CONFIG_ARCH_T1024 790 #define CONFIG_BOARDNAME t1024rdb 791 #define BANK_INTLV cs0_cs1 792 #else 793 #define CONFIG_BOARDNAME t1023rdb 794 #define BANK_INTLV null 795 #endif 796 797 #define CONFIG_EXTRA_ENV_SETTINGS \ 798 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 799 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 800 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 801 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 802 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 803 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 804 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 805 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 806 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 807 "netdev=eth0\0" \ 808 "tftpflash=tftpboot $loadaddr $uboot && " \ 809 "protect off $ubootaddr +$filesize && " \ 810 "erase $ubootaddr +$filesize && " \ 811 "cp.b $loadaddr $ubootaddr $filesize && " \ 812 "protect on $ubootaddr +$filesize && " \ 813 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 814 "consoledev=ttyS0\0" \ 815 "ramdiskaddr=2000000\0" \ 816 "fdtaddr=1e00000\0" \ 817 "bdev=sda3\0" 818 819 #define CONFIG_LINUX \ 820 "setenv bootargs root=/dev/ram rw " \ 821 "console=$consoledev,$baudrate $othbootargs;" \ 822 "setenv ramdiskaddr 0x02000000;" \ 823 "setenv fdtaddr 0x00c00000;" \ 824 "setenv loadaddr 0x1000000;" \ 825 "bootm $loadaddr $ramdiskaddr $fdtaddr" 826 827 #define CONFIG_NFSBOOTCOMMAND \ 828 "setenv bootargs root=/dev/nfs rw " \ 829 "nfsroot=$serverip:$rootpath " \ 830 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 831 "console=$consoledev,$baudrate $othbootargs;" \ 832 "tftp $loadaddr $bootfile;" \ 833 "tftp $fdtaddr $fdtfile;" \ 834 "bootm $loadaddr - $fdtaddr" 835 836 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 837 838 #include <asm/fsl_secure_boot.h> 839 840 #endif /* __T1024RDB_H */ 841