1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 #define CONFIG_BOOKE 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #define CONFIG_E500MC /* BOOKE e500mc family */ 20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 21 #define CONFIG_MP /* support multiple processors */ 22 #define CONFIG_PHYS_64BIT 23 #define CONFIG_ENABLE_36BIT_PHYS 24 25 #ifdef CONFIG_PHYS_64BIT 26 #define CONFIG_ADDR_MAP 1 27 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 28 #endif 29 30 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 31 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 32 #define CONFIG_FSL_IFC /* Enable IFC Support */ 33 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_ENV_OVERWRITE 36 37 /* support deep sleep */ 38 #define CONFIG_DEEP_SLEEP 39 #if defined(CONFIG_DEEP_SLEEP) 40 #define CONFIG_SILENT_CONSOLE 41 #define CONFIG_BOARD_EARLY_INIT_F 42 #endif 43 44 #ifdef CONFIG_RAMBOOT_PBL 45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 46 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 48 #define CONFIG_SPL_ENV_SUPPORT 49 #define CONFIG_SPL_SERIAL_SUPPORT 50 #define CONFIG_SPL_FLUSH_IMAGE 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 #define CONFIG_SPL_LIBGENERIC_SUPPORT 53 #define CONFIG_SPL_LIBCOMMON_SUPPORT 54 #define CONFIG_SPL_I2C_SUPPORT 55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 56 #define CONFIG_FSL_LAW /* Use common FSL init code */ 57 #define CONFIG_SYS_TEXT_BASE 0x30001000 58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 59 #define CONFIG_SPL_PAD_TO 0x40000 60 #define CONFIG_SPL_MAX_SIZE 0x28000 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 #ifdef CONFIG_SPL_BUILD 64 #define CONFIG_SPL_SKIP_RELOCATE 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 67 #define CONFIG_SYS_NO_FLASH 68 #endif 69 70 #ifdef CONFIG_NAND 71 #define CONFIG_SPL_NAND_SUPPORT 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 74 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 77 #define CONFIG_SPL_NAND_BOOT 78 #endif 79 80 #ifdef CONFIG_SPIFLASH 81 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 82 #define CONFIG_SPL_SPI_SUPPORT 83 #define CONFIG_SPL_SPI_FLASH_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #define CONFIG_SPL_SPI_BOOT 94 #endif 95 96 #ifdef CONFIG_SDCARD 97 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 98 #define CONFIG_SPL_MMC_SUPPORT 99 #define CONFIG_SPL_MMC_MINIMAL 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 102 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 105 #ifndef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #endif 108 #define CONFIG_SPL_MMC_BOOT 109 #endif 110 111 #endif /* CONFIG_RAMBOOT_PBL */ 112 113 #ifndef CONFIG_SYS_TEXT_BASE 114 #define CONFIG_SYS_TEXT_BASE 0xeff40000 115 #endif 116 117 #ifndef CONFIG_RESET_VECTOR_ADDRESS 118 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 119 #endif 120 121 #ifndef CONFIG_SYS_NO_FLASH 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 125 #endif 126 127 /* PCIe Boot - Master */ 128 #define CONFIG_SRIO_PCIE_BOOT_MASTER 129 /* 130 * for slave u-boot IMAGE instored in master memory space, 131 * PHYS must be aligned based on the SIZE 132 */ 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 138 #else 139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 141 #endif 142 /* 143 * for slave UCODE and ENV instored in master memory space, 144 * PHYS must be aligned based on the SIZE 145 */ 146 #ifdef CONFIG_PHYS_64BIT 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 149 #else 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 152 #endif 153 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 154 /* slave core release by master*/ 155 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 156 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 157 158 /* PCIe Boot - Slave */ 159 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 162 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 163 /* Set 1M boot space for PCIe boot */ 164 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 165 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 166 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 167 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 168 #define CONFIG_SYS_NO_FLASH 169 #endif 170 171 #if defined(CONFIG_SPIFLASH) 172 #define CONFIG_SYS_EXTRA_ENV_RELOC 173 #define CONFIG_ENV_IS_IN_SPI_FLASH 174 #define CONFIG_ENV_SPI_BUS 0 175 #define CONFIG_ENV_SPI_CS 0 176 #define CONFIG_ENV_SPI_MAX_HZ 10000000 177 #define CONFIG_ENV_SPI_MODE 0 178 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 179 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 180 #define CONFIG_ENV_SECT_SIZE 0x10000 181 #elif defined(CONFIG_SDCARD) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_IS_IN_MMC 184 #define CONFIG_SYS_MMC_ENV_DEV 0 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_OFFSET (512 * 0x800) 187 #elif defined(CONFIG_NAND) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_ENV_IS_IN_NAND 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 192 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 193 #define CONFIG_ENV_IS_IN_REMOTE 194 #define CONFIG_ENV_ADDR 0xffe20000 195 #define CONFIG_ENV_SIZE 0x2000 196 #elif defined(CONFIG_ENV_IS_NOWHERE) 197 #define CONFIG_ENV_SIZE 0x2000 198 #else 199 #define CONFIG_ENV_IS_IN_FLASH 200 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 201 #define CONFIG_ENV_SIZE 0x2000 202 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 203 #endif 204 205 206 #ifndef __ASSEMBLY__ 207 unsigned long get_board_sys_clk(void); 208 unsigned long get_board_ddr_clk(void); 209 #endif 210 211 #define CONFIG_SYS_CLK_FREQ 100000000 212 #define CONFIG_DDR_CLK_FREQ 66660000 213 214 /* 215 * These can be toggled for performance analysis, otherwise use default. 216 */ 217 #define CONFIG_SYS_CACHE_STASHING 218 #define CONFIG_BACKSIDE_L2_CACHE 219 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 220 #define CONFIG_BTB /* toggle branch predition */ 221 #define CONFIG_DDR_ECC 222 #ifdef CONFIG_DDR_ECC 223 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 224 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 225 #endif 226 227 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 228 #define CONFIG_SYS_MEMTEST_END 0x00400000 229 #define CONFIG_SYS_ALT_MEMTEST 230 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 231 232 /* 233 * Config the L3 Cache as L3 SRAM 234 */ 235 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 236 #define CONFIG_SYS_L3_SIZE (256 << 10) 237 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 238 #ifdef CONFIG_RAMBOOT_PBL 239 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 240 #endif 241 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 242 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 243 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 244 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 245 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_SYS_DCSRBAR 0xf0000000 248 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 249 #endif 250 251 /* EEPROM */ 252 #define CONFIG_ID_EEPROM 253 #define CONFIG_SYS_I2C_EEPROM_NXID 254 #define CONFIG_SYS_EEPROM_BUS_NUM 0 255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 259 260 /* 261 * DDR Setup 262 */ 263 #define CONFIG_VERY_BIG_RAM 264 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 265 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 266 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 267 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 268 #define CONFIG_DDR_SPD 269 #define CONFIG_SYS_FSL_DDR3 270 271 #define CONFIG_SYS_SPD_BUS_NUM 0 272 #define SPD_EEPROM_ADDRESS 0x51 273 274 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 275 276 /* 277 * IFC Definitions 278 */ 279 #define CONFIG_SYS_FLASH_BASE 0xe8000000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 282 #else 283 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 284 #endif 285 286 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 287 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 288 CSPR_PORT_SIZE_16 | \ 289 CSPR_MSEL_NOR | \ 290 CSPR_V) 291 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 292 293 /* NOR Flash Timing Params */ 294 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 295 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 296 FTIM0_NOR_TEADC(0x5) | \ 297 FTIM0_NOR_TEAHC(0x5)) 298 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 299 FTIM1_NOR_TRAD_NOR(0x1A) |\ 300 FTIM1_NOR_TSEQRAD_NOR(0x13)) 301 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 302 FTIM2_NOR_TCH(0x4) | \ 303 FTIM2_NOR_TWPH(0x0E) | \ 304 FTIM2_NOR_TWP(0x1c)) 305 #define CONFIG_SYS_NOR_FTIM3 0x0 306 307 #define CONFIG_SYS_FLASH_QUIET_TEST 308 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 309 310 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 311 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 312 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 313 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 314 315 #define CONFIG_SYS_FLASH_EMPTY_INFO 316 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 317 318 /* CPLD on IFC */ 319 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 320 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 321 #define CONFIG_SYS_CSPR2_EXT (0xf) 322 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 323 | CSPR_PORT_SIZE_8 \ 324 | CSPR_MSEL_GPCM \ 325 | CSPR_V) 326 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 327 #define CONFIG_SYS_CSOR2 0x0 328 329 /* CPLD Timing parameters for IFC CS2 */ 330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 331 FTIM0_GPCM_TEADC(0x0e) | \ 332 FTIM0_GPCM_TEAHC(0x0e)) 333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 334 FTIM1_GPCM_TRAD(0x1f)) 335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 336 FTIM2_GPCM_TCH(0x8) | \ 337 FTIM2_GPCM_TWP(0x1f)) 338 #define CONFIG_SYS_CS2_FTIM3 0x0 339 340 /* NAND Flash on IFC */ 341 #define CONFIG_NAND_FSL_IFC 342 #define CONFIG_SYS_NAND_BASE 0xff800000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 345 #else 346 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 347 #endif 348 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 349 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 350 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 351 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 352 | CSPR_V) 353 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 354 355 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 356 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 357 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 358 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 359 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 360 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 361 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 362 363 #define CONFIG_SYS_NAND_ONFI_DETECTION 364 365 /* ONFI NAND Flash mode0 Timing Params */ 366 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 367 FTIM0_NAND_TWP(0x18) | \ 368 FTIM0_NAND_TWCHT(0x07) | \ 369 FTIM0_NAND_TWH(0x0a)) 370 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 371 FTIM1_NAND_TWBE(0x39) | \ 372 FTIM1_NAND_TRR(0x0e) | \ 373 FTIM1_NAND_TRP(0x18)) 374 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 375 FTIM2_NAND_TREH(0x0a) | \ 376 FTIM2_NAND_TWHRE(0x1e)) 377 #define CONFIG_SYS_NAND_FTIM3 0x0 378 379 #define CONFIG_SYS_NAND_DDR_LAW 11 380 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 381 #define CONFIG_SYS_MAX_NAND_DEVICE 1 382 #define CONFIG_CMD_NAND 383 384 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 385 386 #if defined(CONFIG_NAND) 387 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 388 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 389 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 390 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 391 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 392 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 393 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 394 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 395 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 396 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 397 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 398 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 399 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 400 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 401 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 402 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 403 #else 404 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 405 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 406 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 407 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 408 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 409 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 410 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 411 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 412 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 413 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 414 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 415 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 416 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 417 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 418 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 419 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 420 #endif 421 422 #ifdef CONFIG_SPL_BUILD 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 424 #else 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 426 #endif 427 428 #if defined(CONFIG_RAMBOOT_PBL) 429 #define CONFIG_SYS_RAMBOOT 430 #endif 431 432 #define CONFIG_BOARD_EARLY_INIT_R 433 #define CONFIG_MISC_INIT_R 434 435 #define CONFIG_HWCONFIG 436 437 /* define to use L1 as initial stack */ 438 #define CONFIG_L1_INIT_RAM 439 #define CONFIG_SYS_INIT_RAM_LOCK 440 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 441 #ifdef CONFIG_PHYS_64BIT 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 444 /* The assembler doesn't like typecast */ 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 446 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 447 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 448 #else 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 452 #endif 453 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 454 455 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 456 GENERATED_GBL_DATA_SIZE) 457 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 458 459 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 460 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 461 462 /* Serial Port */ 463 #define CONFIG_CONS_INDEX 1 464 #define CONFIG_SYS_NS16550 465 #define CONFIG_SYS_NS16550_SERIAL 466 #define CONFIG_SYS_NS16550_REG_SIZE 1 467 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 468 469 #define CONFIG_SYS_BAUDRATE_TABLE \ 470 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 471 472 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 473 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 474 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 475 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 476 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 477 478 /* Use the HUSH parser */ 479 #define CONFIG_SYS_HUSH_PARSER 480 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 481 482 /* Video */ 483 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 484 #ifdef CONFIG_FSL_DIU_FB 485 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 486 #define CONFIG_VIDEO 487 #define CONFIG_CMD_BMP 488 #define CONFIG_CFB_CONSOLE 489 #define CONFIG_VIDEO_SW_CURSOR 490 #define CONFIG_VGA_AS_SINGLE_DEVICE 491 #define CONFIG_VIDEO_LOGO 492 #define CONFIG_VIDEO_BMP_LOGO 493 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 494 /* 495 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 496 * disable empty flash sector detection, which is I/O-intensive. 497 */ 498 #undef CONFIG_SYS_FLASH_EMPTY_INFO 499 #endif 500 501 /* pass open firmware flat tree */ 502 #define CONFIG_OF_LIBFDT 503 #define CONFIG_OF_BOARD_SETUP 504 #define CONFIG_OF_STDOUT_VIA_ALIAS 505 506 /* new uImage format support */ 507 #define CONFIG_FIT 508 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 509 510 /* I2C */ 511 #define CONFIG_SYS_I2C 512 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 513 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 515 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 516 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 518 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 519 520 #define I2C_MUX_PCA_ADDR 0x77 521 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 522 523 524 /* I2C bus multiplexer */ 525 #define I2C_MUX_CH_DEFAULT 0x8 526 527 /* 528 * RTC configuration 529 */ 530 #define RTC 531 #define CONFIG_RTC_DS1337 1 532 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 533 534 /* 535 * eSPI - Enhanced SPI 536 */ 537 #define CONFIG_FSL_ESPI 538 #define CONFIG_SPI_FLASH 539 #define CONFIG_SPI_FLASH_STMICRO 540 #define CONFIG_CMD_SF 541 #define CONFIG_SPI_FLASH_BAR 542 #define CONFIG_SF_DEFAULT_SPEED 10000000 543 #define CONFIG_SF_DEFAULT_MODE 0 544 545 /* 546 * General PCIe 547 * Memory space is mapped 1-1, but I/O space must start from 0. 548 */ 549 #define CONFIG_PCI /* Enable PCI/PCIE */ 550 #define CONFIG_PCIE1 /* PCIE controler 1 */ 551 #define CONFIG_PCIE2 /* PCIE controler 2 */ 552 #define CONFIG_PCIE3 /* PCIE controler 3 */ 553 #ifdef CONFIG_PPC_T1040 554 #define CONFIG_PCIE4 /* PCIE controler 4 */ 555 #endif 556 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 557 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 558 #define CONFIG_PCI_INDIRECT_BRIDGE 559 560 #ifdef CONFIG_PCI 561 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 562 #ifdef CONFIG_PCIE1 563 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 564 #ifdef CONFIG_PHYS_64BIT 565 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 567 #else 568 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 569 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 570 #endif 571 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 572 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 573 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 574 #ifdef CONFIG_PHYS_64BIT 575 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 576 #else 577 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 578 #endif 579 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 580 #endif 581 582 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 583 #ifdef CONFIG_PCIE2 584 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 585 #ifdef CONFIG_PHYS_64BIT 586 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 587 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 588 #else 589 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 590 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 591 #endif 592 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 593 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 594 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 595 #ifdef CONFIG_PHYS_64BIT 596 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 597 #else 598 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 599 #endif 600 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 601 #endif 602 603 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 604 #ifdef CONFIG_PCIE3 605 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 606 #ifdef CONFIG_PHYS_64BIT 607 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 608 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 609 #else 610 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 611 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 612 #endif 613 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 614 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 615 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 616 #ifdef CONFIG_PHYS_64BIT 617 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 618 #else 619 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 620 #endif 621 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 622 #endif 623 624 /* controller 4, Base address 203000, to be removed */ 625 #ifdef CONFIG_PCIE4 626 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 627 #ifdef CONFIG_PHYS_64BIT 628 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 629 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 630 #else 631 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 632 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 633 #endif 634 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 635 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 636 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 637 #ifdef CONFIG_PHYS_64BIT 638 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 639 #else 640 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 641 #endif 642 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 643 #endif 644 645 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 646 #define CONFIG_E1000 647 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 648 #define CONFIG_DOS_PARTITION 649 #endif /* CONFIG_PCI */ 650 651 /* 652 * USB 653 */ 654 #define CONFIG_HAS_FSL_DR_USB 655 656 #ifdef CONFIG_HAS_FSL_DR_USB 657 #define CONFIG_USB_EHCI 658 #define CONFIG_CMD_USB 659 #define CONFIG_USB_STORAGE 660 #define CONFIG_USB_EHCI_FSL 661 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 662 #define CONFIG_CMD_EXT2 663 #endif 664 665 /* 666 * SDHC 667 */ 668 #define CONFIG_MMC 669 #ifdef CONFIG_MMC 670 #define CONFIG_FSL_ESDHC 671 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 672 #define CONFIG_CMD_MMC 673 #define CONFIG_GENERIC_MMC 674 #define CONFIG_CMD_EXT2 675 #define CONFIG_CMD_FAT 676 #define CONFIG_DOS_PARTITION 677 #endif 678 679 /* Qman/Bman */ 680 #ifndef CONFIG_NOBQFMAN 681 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 682 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 683 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 684 #ifdef CONFIG_PHYS_64BIT 685 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 686 #else 687 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 688 #endif 689 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 690 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 691 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 692 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 693 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 694 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 695 CONFIG_SYS_BMAN_CENA_SIZE) 696 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 697 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 698 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 699 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 700 #ifdef CONFIG_PHYS_64BIT 701 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 702 #else 703 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 704 #endif 705 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 706 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 707 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 708 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 709 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 710 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 711 CONFIG_SYS_QMAN_CENA_SIZE) 712 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 713 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 714 715 #define CONFIG_SYS_DPAA_FMAN 716 717 #define CONFIG_QE 718 #define CONFIG_U_QE 719 /* Default address of microcode for the Linux FMan driver */ 720 #if defined(CONFIG_SPIFLASH) 721 /* 722 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 723 * env, so we got 0x110000. 724 */ 725 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 726 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 727 #define CONFIG_SYS_QE_FW_ADDR 0x130000 728 #elif defined(CONFIG_SDCARD) 729 /* 730 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 731 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 732 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 733 */ 734 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 735 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 736 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 737 #elif defined(CONFIG_NAND) 738 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 739 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 740 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 741 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 742 /* 743 * Slave has no ucode locally, it can fetch this from remote. When implementing 744 * in two corenet boards, slave's ucode could be stored in master's memory 745 * space, the address can be mapped from slave TLB->slave LAW-> 746 * slave SRIO or PCIE outbound window->master inbound window-> 747 * master LAW->the ucode address in master's memory space. 748 */ 749 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 750 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 751 #else 752 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 753 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 754 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 755 #endif 756 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 757 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 758 #endif /* CONFIG_NOBQFMAN */ 759 760 #ifdef CONFIG_SYS_DPAA_FMAN 761 #define CONFIG_FMAN_ENET 762 #define CONFIG_PHYLIB_10G 763 #define CONFIG_PHY_REALTEK 764 #define CONFIG_PHY_AQUANTIA 765 #define RGMII_PHY1_ADDR 0x2 766 #define RGMII_PHY2_ADDR 0x6 767 #define SGMII_PHY1_ADDR 0x2 768 #define FM1_10GEC1_PHY_ADDR 0x1 769 #endif 770 771 #ifdef CONFIG_FMAN_ENET 772 #define CONFIG_MII /* MII PHY management */ 773 #define CONFIG_ETHPRIME "FM1@DTSEC4" 774 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 775 #endif 776 777 /* 778 * Dynamic MTD Partition support with mtdparts 779 */ 780 #ifndef CONFIG_SYS_NO_FLASH 781 #define CONFIG_MTD_DEVICE 782 #define CONFIG_MTD_PARTITIONS 783 #define CONFIG_CMD_MTDPARTS 784 #define CONFIG_FLASH_CFI_MTD 785 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 786 "spi0=spife110000.1" 787 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 788 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 789 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 790 "1m(uboot),5m(kernel),128k(dtb),-(user)" 791 #endif 792 793 /* 794 * Environment 795 */ 796 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 797 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 798 799 /* 800 * Command line configuration. 801 */ 802 #include <config_cmd_default.h> 803 804 #define CONFIG_CMD_DATE 805 #define CONFIG_CMD_DHCP 806 #define CONFIG_CMD_EEPROM 807 #define CONFIG_CMD_ELF 808 #define CONFIG_CMD_ERRATA 809 #define CONFIG_CMD_GREPENV 810 #define CONFIG_CMD_IRQ 811 #define CONFIG_CMD_I2C 812 #define CONFIG_CMD_MII 813 #define CONFIG_CMD_PING 814 #define CONFIG_CMD_ECHO 815 #define CONFIG_CMD_REGINFO 816 #define CONFIG_CMD_SETEXPR 817 #define CONFIG_CMD_BDI 818 819 #ifdef CONFIG_PCI 820 #define CONFIG_CMD_PCI 821 #define CONFIG_CMD_NET 822 #endif 823 824 /* 825 * Miscellaneous configurable options 826 */ 827 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 828 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 829 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 830 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 831 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 832 #ifdef CONFIG_CMD_KGDB 833 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 834 #else 835 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 836 #endif 837 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 838 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 839 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 840 841 /* 842 * For booting Linux, the board info and command line data 843 * have to be in the first 64 MB of memory, since this is 844 * the maximum mapped by the Linux kernel during initialization. 845 */ 846 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 847 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 848 849 #ifdef CONFIG_CMD_KGDB 850 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 851 #endif 852 853 /* 854 * Environment Configuration 855 */ 856 #define CONFIG_ROOTPATH "/opt/nfsroot" 857 #define CONFIG_BOOTFILE "uImage" 858 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 859 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 860 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 861 #define CONFIG_BAUDRATE 115200 862 #define __USB_PHY_TYPE utmi 863 864 #ifdef CONFIG_PPC_T1024 865 #define CONFIG_BOARDNAME "t1024rdb" 866 #else 867 #define CONFIG_BOARDNAME "t1023rdb" 868 #endif 869 870 #define CONFIG_EXTRA_ENV_SETTINGS \ 871 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 872 "bank_intlv=cs0_cs1\0" \ 873 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 874 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 875 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 876 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 877 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 878 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 879 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 880 "netdev=eth0\0" \ 881 "tftpflash=tftpboot $loadaddr $uboot && " \ 882 "protect off $ubootaddr +$filesize && " \ 883 "erase $ubootaddr +$filesize && " \ 884 "cp.b $loadaddr $ubootaddr $filesize && " \ 885 "protect on $ubootaddr +$filesize && " \ 886 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 887 "consoledev=ttyS0\0" \ 888 "ramdiskaddr=2000000\0" \ 889 "fdtaddr=c00000\0" \ 890 "bdev=sda3\0" 891 892 #define CONFIG_LINUX \ 893 "setenv bootargs root=/dev/ram rw " \ 894 "console=$consoledev,$baudrate $othbootargs;" \ 895 "setenv ramdiskaddr 0x02000000;" \ 896 "setenv fdtaddr 0x00c00000;" \ 897 "setenv loadaddr 0x1000000;" \ 898 "bootm $loadaddr $ramdiskaddr $fdtaddr" 899 900 901 #define CONFIG_NFSBOOTCOMMAND \ 902 "setenv bootargs root=/dev/nfs rw " \ 903 "nfsroot=$serverip:$rootpath " \ 904 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 905 "console=$consoledev,$baudrate $othbootargs;" \ 906 "tftp $loadaddr $bootfile;" \ 907 "tftp $fdtaddr $fdtfile;" \ 908 "bootm $loadaddr - $fdtaddr" 909 910 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 911 912 #ifdef CONFIG_SECURE_BOOT 913 #include <asm/fsl_secure_boot.h> 914 #endif 915 916 #endif /* __T1024RDB_H */ 917