1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 /* support deep sleep */ 30 #ifdef CONFIG_ARCH_T1024 31 #define CONFIG_DEEP_SLEEP 32 #endif 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_SKIP_RELOCATE 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 47 #endif 48 49 #ifdef CONFIG_NAND 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #if defined(CONFIG_TARGET_T1024RDB) 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 57 #elif defined(CONFIG_TARGET_T1023RDB) 58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 59 #endif 60 #define CONFIG_SPL_NAND_BOOT 61 #endif 62 63 #ifdef CONFIG_SPIFLASH 64 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 65 #define CONFIG_SPL_SPI_FLASH_MINIMAL 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #ifndef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 73 #endif 74 #if defined(CONFIG_TARGET_T1024RDB) 75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 76 #elif defined(CONFIG_TARGET_T1023RDB) 77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 78 #endif 79 #define CONFIG_SPL_SPI_BOOT 80 #endif 81 82 #ifdef CONFIG_SDCARD 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 85 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 86 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 87 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 89 #ifndef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 91 #endif 92 #if defined(CONFIG_TARGET_T1024RDB) 93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 94 #elif defined(CONFIG_TARGET_T1023RDB) 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 96 #endif 97 #define CONFIG_SPL_MMC_BOOT 98 #endif 99 100 #endif /* CONFIG_RAMBOOT_PBL */ 101 102 #ifndef CONFIG_RESET_VECTOR_ADDRESS 103 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 104 #endif 105 106 #ifdef CONFIG_MTD_NOR_FLASH 107 #define CONFIG_FLASH_CFI_DRIVER 108 #define CONFIG_SYS_FLASH_CFI 109 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 110 #endif 111 112 /* PCIe Boot - Master */ 113 #define CONFIG_SRIO_PCIE_BOOT_MASTER 114 /* 115 * for slave u-boot IMAGE instored in master memory space, 116 * PHYS must be aligned based on the SIZE 117 */ 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 123 #else 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 126 #endif 127 /* 128 * for slave UCODE and ENV instored in master memory space, 129 * PHYS must be aligned based on the SIZE 130 */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 134 #else 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 137 #endif 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 139 /* slave core release by master*/ 140 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 141 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 142 143 /* PCIe Boot - Slave */ 144 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 145 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 146 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 147 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 148 /* Set 1M boot space for PCIe boot */ 149 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 151 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 152 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 153 #endif 154 155 #if defined(CONFIG_SPIFLASH) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_ENV_SPI_BUS 0 158 #define CONFIG_ENV_SPI_CS 0 159 #define CONFIG_ENV_SPI_MAX_HZ 10000000 160 #define CONFIG_ENV_SPI_MODE 0 161 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 162 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 163 #if defined(CONFIG_TARGET_T1024RDB) 164 #define CONFIG_ENV_SECT_SIZE 0x10000 165 #elif defined(CONFIG_TARGET_T1023RDB) 166 #define CONFIG_ENV_SECT_SIZE 0x40000 167 #endif 168 #elif defined(CONFIG_SDCARD) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_SYS_MMC_ENV_DEV 0 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_OFFSET (512 * 0x800) 173 #elif defined(CONFIG_NAND) 174 #define CONFIG_SYS_EXTRA_ENV_RELOC 175 #define CONFIG_ENV_SIZE 0x2000 176 #if defined(CONFIG_TARGET_T1024RDB) 177 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 178 #elif defined(CONFIG_TARGET_T1023RDB) 179 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 180 #endif 181 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 182 #define CONFIG_ENV_ADDR 0xffe20000 183 #define CONFIG_ENV_SIZE 0x2000 184 #elif defined(CONFIG_ENV_IS_NOWHERE) 185 #define CONFIG_ENV_SIZE 0x2000 186 #else 187 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 188 #define CONFIG_ENV_SIZE 0x2000 189 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 190 #endif 191 192 #ifndef __ASSEMBLY__ 193 unsigned long get_board_sys_clk(void); 194 unsigned long get_board_ddr_clk(void); 195 #endif 196 197 #define CONFIG_SYS_CLK_FREQ 100000000 198 #define CONFIG_DDR_CLK_FREQ 100000000 199 200 /* 201 * These can be toggled for performance analysis, otherwise use default. 202 */ 203 #define CONFIG_SYS_CACHE_STASHING 204 #define CONFIG_BACKSIDE_L2_CACHE 205 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 206 #define CONFIG_BTB /* toggle branch predition */ 207 #define CONFIG_DDR_ECC 208 #ifdef CONFIG_DDR_ECC 209 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 210 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 211 #endif 212 213 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 214 #define CONFIG_SYS_MEMTEST_END 0x00400000 215 #define CONFIG_SYS_ALT_MEMTEST 216 217 /* 218 * Config the L3 Cache as L3 SRAM 219 */ 220 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 221 #define CONFIG_SYS_L3_SIZE (256 << 10) 222 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 223 #ifdef CONFIG_RAMBOOT_PBL 224 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 225 #endif 226 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 227 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 228 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 229 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 230 231 #ifdef CONFIG_PHYS_64BIT 232 #define CONFIG_SYS_DCSRBAR 0xf0000000 233 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 234 #endif 235 236 /* EEPROM */ 237 #define CONFIG_ID_EEPROM 238 #define CONFIG_SYS_I2C_EEPROM_NXID 239 #define CONFIG_SYS_EEPROM_BUS_NUM 0 240 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 244 245 /* 246 * DDR Setup 247 */ 248 #define CONFIG_VERY_BIG_RAM 249 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 250 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 251 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 252 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 253 #define CONFIG_FSL_DDR_INTERACTIVE 254 #if defined(CONFIG_TARGET_T1024RDB) 255 #define CONFIG_DDR_SPD 256 #define CONFIG_SYS_SPD_BUS_NUM 0 257 #define SPD_EEPROM_ADDRESS 0x51 258 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 259 #elif defined(CONFIG_TARGET_T1023RDB) 260 #define CONFIG_SYS_DDR_RAW_TIMING 261 #define CONFIG_SYS_SDRAM_SIZE 2048 262 #endif 263 264 /* 265 * IFC Definitions 266 */ 267 #define CONFIG_SYS_FLASH_BASE 0xe8000000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 270 #else 271 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 272 #endif 273 274 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 275 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 276 CSPR_PORT_SIZE_16 | \ 277 CSPR_MSEL_NOR | \ 278 CSPR_V) 279 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 280 281 /* NOR Flash Timing Params */ 282 #if defined(CONFIG_TARGET_T1024RDB) 283 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 284 #elif defined(CONFIG_TARGET_T1023RDB) 285 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 286 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 287 #endif 288 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 289 FTIM0_NOR_TEADC(0x5) | \ 290 FTIM0_NOR_TEAHC(0x5)) 291 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 292 FTIM1_NOR_TRAD_NOR(0x1A) |\ 293 FTIM1_NOR_TSEQRAD_NOR(0x13)) 294 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 295 FTIM2_NOR_TCH(0x4) | \ 296 FTIM2_NOR_TWPH(0x0E) | \ 297 FTIM2_NOR_TWP(0x1c)) 298 #define CONFIG_SYS_NOR_FTIM3 0x0 299 300 #define CONFIG_SYS_FLASH_QUIET_TEST 301 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 302 303 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 304 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 305 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 306 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 307 308 #define CONFIG_SYS_FLASH_EMPTY_INFO 309 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 310 311 #ifdef CONFIG_TARGET_T1024RDB 312 /* CPLD on IFC */ 313 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 314 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 315 #define CONFIG_SYS_CSPR2_EXT (0xf) 316 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 317 | CSPR_PORT_SIZE_8 \ 318 | CSPR_MSEL_GPCM \ 319 | CSPR_V) 320 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 321 #define CONFIG_SYS_CSOR2 0x0 322 323 /* CPLD Timing parameters for IFC CS2 */ 324 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 325 FTIM0_GPCM_TEADC(0x0e) | \ 326 FTIM0_GPCM_TEAHC(0x0e)) 327 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 328 FTIM1_GPCM_TRAD(0x1f)) 329 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 330 FTIM2_GPCM_TCH(0x8) | \ 331 FTIM2_GPCM_TWP(0x1f)) 332 #define CONFIG_SYS_CS2_FTIM3 0x0 333 #endif 334 335 /* NAND Flash on IFC */ 336 #define CONFIG_NAND_FSL_IFC 337 #define CONFIG_SYS_NAND_BASE 0xff800000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 340 #else 341 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 342 #endif 343 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 344 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 345 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 346 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 347 | CSPR_V) 348 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 349 350 #if defined(CONFIG_TARGET_T1024RDB) 351 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 352 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 353 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 354 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 355 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 356 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 357 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 358 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 359 #elif defined(CONFIG_TARGET_T1023RDB) 360 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 361 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 362 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 363 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 364 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 365 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 366 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 367 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 368 #endif 369 370 #define CONFIG_SYS_NAND_ONFI_DETECTION 371 /* ONFI NAND Flash mode0 Timing Params */ 372 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 373 FTIM0_NAND_TWP(0x18) | \ 374 FTIM0_NAND_TWCHT(0x07) | \ 375 FTIM0_NAND_TWH(0x0a)) 376 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 377 FTIM1_NAND_TWBE(0x39) | \ 378 FTIM1_NAND_TRR(0x0e) | \ 379 FTIM1_NAND_TRP(0x18)) 380 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 381 FTIM2_NAND_TREH(0x0a) | \ 382 FTIM2_NAND_TWHRE(0x1e)) 383 #define CONFIG_SYS_NAND_FTIM3 0x0 384 385 #define CONFIG_SYS_NAND_DDR_LAW 11 386 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 387 #define CONFIG_SYS_MAX_NAND_DEVICE 1 388 389 #if defined(CONFIG_NAND) 390 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 391 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 392 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 393 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 394 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 395 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 396 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 397 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 398 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 399 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 400 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 401 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 402 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 403 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 404 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 405 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 406 #else 407 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 408 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 409 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 423 #endif 424 425 #ifdef CONFIG_SPL_BUILD 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 427 #else 428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 429 #endif 430 431 #if defined(CONFIG_RAMBOOT_PBL) 432 #define CONFIG_SYS_RAMBOOT 433 #endif 434 435 #define CONFIG_BOARD_EARLY_INIT_R 436 #define CONFIG_MISC_INIT_R 437 438 #define CONFIG_HWCONFIG 439 440 /* define to use L1 as initial stack */ 441 #define CONFIG_L1_INIT_RAM 442 #define CONFIG_SYS_INIT_RAM_LOCK 443 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 447 /* The assembler doesn't like typecast */ 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 449 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 450 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 451 #else 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 455 #endif 456 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 457 458 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 459 GENERATED_GBL_DATA_SIZE) 460 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 461 462 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 463 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 464 465 /* Serial Port */ 466 #define CONFIG_CONS_INDEX 1 467 #define CONFIG_SYS_NS16550_SERIAL 468 #define CONFIG_SYS_NS16550_REG_SIZE 1 469 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 470 471 #define CONFIG_SYS_BAUDRATE_TABLE \ 472 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 473 474 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 475 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 476 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 477 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 478 479 /* Video */ 480 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 481 #ifdef CONFIG_FSL_DIU_FB 482 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 483 #define CONFIG_VIDEO_LOGO 484 #define CONFIG_VIDEO_BMP_LOGO 485 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 486 /* 487 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 488 * disable empty flash sector detection, which is I/O-intensive. 489 */ 490 #undef CONFIG_SYS_FLASH_EMPTY_INFO 491 #endif 492 493 /* I2C */ 494 #define CONFIG_SYS_I2C 495 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 496 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 497 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 498 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 499 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 500 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 501 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 502 503 #define I2C_PCA6408_BUS_NUM 1 504 #define I2C_PCA6408_ADDR 0x20 505 506 /* I2C bus multiplexer */ 507 #define I2C_MUX_CH_DEFAULT 0x8 508 509 /* 510 * RTC configuration 511 */ 512 #define RTC 513 #define CONFIG_RTC_DS1337 1 514 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 515 516 /* 517 * eSPI - Enhanced SPI 518 */ 519 #define CONFIG_SPI_FLASH_BAR 520 #define CONFIG_SF_DEFAULT_SPEED 10000000 521 #define CONFIG_SF_DEFAULT_MODE 0 522 523 /* 524 * General PCIe 525 * Memory space is mapped 1-1, but I/O space must start from 0. 526 */ 527 #define CONFIG_PCIE1 /* PCIE controller 1 */ 528 #define CONFIG_PCIE2 /* PCIE controller 2 */ 529 #define CONFIG_PCIE3 /* PCIE controller 3 */ 530 #ifdef CONFIG_ARCH_T1040 531 #define CONFIG_PCIE4 /* PCIE controller 4 */ 532 #endif 533 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 534 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 535 #define CONFIG_PCI_INDIRECT_BRIDGE 536 537 #ifdef CONFIG_PCI 538 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 539 #ifdef CONFIG_PCIE1 540 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 541 #ifdef CONFIG_PHYS_64BIT 542 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 543 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 544 #else 545 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 546 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 547 #endif 548 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 549 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 550 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 551 #ifdef CONFIG_PHYS_64BIT 552 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 553 #else 554 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 555 #endif 556 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 557 #endif 558 559 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 560 #ifdef CONFIG_PCIE2 561 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 562 #ifdef CONFIG_PHYS_64BIT 563 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 564 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 565 #else 566 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 567 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 568 #endif 569 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 570 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 571 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 572 #ifdef CONFIG_PHYS_64BIT 573 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 574 #else 575 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 576 #endif 577 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 578 #endif 579 580 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 581 #ifdef CONFIG_PCIE3 582 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 583 #ifdef CONFIG_PHYS_64BIT 584 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 585 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 586 #else 587 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 588 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 589 #endif 590 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 591 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 592 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 593 #ifdef CONFIG_PHYS_64BIT 594 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 595 #else 596 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 597 #endif 598 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 599 #endif 600 601 /* controller 4, Base address 203000, to be removed */ 602 #ifdef CONFIG_PCIE4 603 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 606 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 607 #else 608 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 609 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 610 #endif 611 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 612 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 613 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 616 #else 617 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 618 #endif 619 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 620 #endif 621 622 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 623 #endif /* CONFIG_PCI */ 624 625 /* 626 * USB 627 */ 628 #define CONFIG_HAS_FSL_DR_USB 629 630 #ifdef CONFIG_HAS_FSL_DR_USB 631 #define CONFIG_USB_EHCI_FSL 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 633 #endif 634 635 /* 636 * SDHC 637 */ 638 #ifdef CONFIG_MMC 639 #define CONFIG_FSL_ESDHC 640 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 641 #endif 642 643 /* Qman/Bman */ 644 #ifndef CONFIG_NOBQFMAN 645 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 646 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 647 #ifdef CONFIG_PHYS_64BIT 648 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 649 #else 650 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 651 #endif 652 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 653 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 654 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 655 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 656 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 657 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 658 CONFIG_SYS_BMAN_CENA_SIZE) 659 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 660 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 661 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 662 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 663 #ifdef CONFIG_PHYS_64BIT 664 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 665 #else 666 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 667 #endif 668 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 669 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 670 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 671 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 672 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 674 CONFIG_SYS_QMAN_CENA_SIZE) 675 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 676 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 677 678 #define CONFIG_SYS_DPAA_FMAN 679 680 #ifdef CONFIG_TARGET_T1024RDB 681 #define CONFIG_QE 682 #define CONFIG_U_QE 683 #endif 684 /* Default address of microcode for the Linux FMan driver */ 685 #if defined(CONFIG_SPIFLASH) 686 /* 687 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 688 * env, so we got 0x110000. 689 */ 690 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 691 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 692 #define CONFIG_SYS_QE_FW_ADDR 0x130000 693 #elif defined(CONFIG_SDCARD) 694 /* 695 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 696 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 697 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 698 */ 699 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 700 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 701 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 702 #elif defined(CONFIG_NAND) 703 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 704 #if defined(CONFIG_TARGET_T1024RDB) 705 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 706 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 707 #elif defined(CONFIG_TARGET_T1023RDB) 708 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 709 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 710 #endif 711 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 712 /* 713 * Slave has no ucode locally, it can fetch this from remote. When implementing 714 * in two corenet boards, slave's ucode could be stored in master's memory 715 * space, the address can be mapped from slave TLB->slave LAW-> 716 * slave SRIO or PCIE outbound window->master inbound window-> 717 * master LAW->the ucode address in master's memory space. 718 */ 719 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 720 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 721 #else 722 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 723 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 724 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 725 #endif 726 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 727 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 728 #endif /* CONFIG_NOBQFMAN */ 729 730 #ifdef CONFIG_SYS_DPAA_FMAN 731 #define CONFIG_FMAN_ENET 732 #define CONFIG_PHYLIB_10G 733 #define CONFIG_PHY_REALTEK 734 #define CONFIG_PHY_AQUANTIA 735 #if defined(CONFIG_TARGET_T1024RDB) 736 #define RGMII_PHY1_ADDR 0x2 737 #define RGMII_PHY2_ADDR 0x6 738 #define SGMII_AQR_PHY_ADDR 0x2 739 #define FM1_10GEC1_PHY_ADDR 0x1 740 #elif defined(CONFIG_TARGET_T1023RDB) 741 #define RGMII_PHY1_ADDR 0x1 742 #define SGMII_RTK_PHY_ADDR 0x3 743 #define SGMII_AQR_PHY_ADDR 0x2 744 #endif 745 #endif 746 747 #ifdef CONFIG_FMAN_ENET 748 #define CONFIG_MII /* MII PHY management */ 749 #define CONFIG_ETHPRIME "FM1@DTSEC4" 750 #endif 751 752 /* 753 * Dynamic MTD Partition support with mtdparts 754 */ 755 #ifdef CONFIG_MTD_NOR_FLASH 756 #define CONFIG_MTD_DEVICE 757 #define CONFIG_MTD_PARTITIONS 758 #define CONFIG_FLASH_CFI_MTD 759 #endif 760 761 /* 762 * Environment 763 */ 764 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 765 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 766 767 /* 768 * Miscellaneous configurable options 769 */ 770 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 771 772 /* 773 * For booting Linux, the board info and command line data 774 * have to be in the first 64 MB of memory, since this is 775 * the maximum mapped by the Linux kernel during initialization. 776 */ 777 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 778 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 779 780 #ifdef CONFIG_CMD_KGDB 781 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 782 #endif 783 784 /* 785 * Environment Configuration 786 */ 787 #define CONFIG_ROOTPATH "/opt/nfsroot" 788 #define CONFIG_BOOTFILE "uImage" 789 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 790 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 791 #define __USB_PHY_TYPE utmi 792 793 #ifdef CONFIG_ARCH_T1024 794 #define CONFIG_BOARDNAME t1024rdb 795 #define BANK_INTLV cs0_cs1 796 #else 797 #define CONFIG_BOARDNAME t1023rdb 798 #define BANK_INTLV null 799 #endif 800 801 #define CONFIG_EXTRA_ENV_SETTINGS \ 802 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 803 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 804 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 805 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 806 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 807 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 808 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 809 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 810 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 811 "netdev=eth0\0" \ 812 "tftpflash=tftpboot $loadaddr $uboot && " \ 813 "protect off $ubootaddr +$filesize && " \ 814 "erase $ubootaddr +$filesize && " \ 815 "cp.b $loadaddr $ubootaddr $filesize && " \ 816 "protect on $ubootaddr +$filesize && " \ 817 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 818 "consoledev=ttyS0\0" \ 819 "ramdiskaddr=2000000\0" \ 820 "fdtaddr=1e00000\0" \ 821 "bdev=sda3\0" 822 823 #define CONFIG_LINUX \ 824 "setenv bootargs root=/dev/ram rw " \ 825 "console=$consoledev,$baudrate $othbootargs;" \ 826 "setenv ramdiskaddr 0x02000000;" \ 827 "setenv fdtaddr 0x00c00000;" \ 828 "setenv loadaddr 0x1000000;" \ 829 "bootm $loadaddr $ramdiskaddr $fdtaddr" 830 831 #define CONFIG_NFSBOOTCOMMAND \ 832 "setenv bootargs root=/dev/nfs rw " \ 833 "nfsroot=$serverip:$rootpath " \ 834 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 835 "console=$consoledev,$baudrate $othbootargs;" \ 836 "tftp $loadaddr $bootfile;" \ 837 "tftp $fdtaddr $fdtfile;" \ 838 "bootm $loadaddr - $fdtaddr" 839 840 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 841 842 #include <asm/fsl_secure_boot.h> 843 844 #endif /* __T1024RDB_H */ 845