1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 RDB board configuration file 8 */ 9 10 #ifndef __T1024RDB_H 11 #define __T1024RDB_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 /* support deep sleep */ 28 #ifdef CONFIG_ARCH_T1024 29 #define CONFIG_DEEP_SLEEP 30 #endif 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 #ifdef CONFIG_SPL_BUILD 41 #define CONFIG_SPL_SKIP_RELOCATE 42 #define CONFIG_SPL_COMMON_INIT_DDR 43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 44 #endif 45 46 #ifdef CONFIG_NAND 47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 52 #if defined(CONFIG_TARGET_T1024RDB) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 54 #elif defined(CONFIG_TARGET_T1023RDB) 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 56 #endif 57 #define CONFIG_SPL_NAND_BOOT 58 #endif 59 60 #ifdef CONFIG_SPIFLASH 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #if defined(CONFIG_TARGET_T1024RDB) 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 73 #elif defined(CONFIG_TARGET_T1023RDB) 74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 75 #endif 76 #define CONFIG_SPL_SPI_BOOT 77 #endif 78 79 #ifdef CONFIG_SDCARD 80 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 81 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #if defined(CONFIG_TARGET_T1024RDB) 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 91 #elif defined(CONFIG_TARGET_T1023RDB) 92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 93 #endif 94 #define CONFIG_SPL_MMC_BOOT 95 #endif 96 97 #endif /* CONFIG_RAMBOOT_PBL */ 98 99 #ifndef CONFIG_RESET_VECTOR_ADDRESS 100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 101 #endif 102 103 /* PCIe Boot - Master */ 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER 105 /* 106 * for slave u-boot IMAGE instored in master memory space, 107 * PHYS must be aligned based on the SIZE 108 */ 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 111 #ifdef CONFIG_PHYS_64BIT 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 114 #else 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 117 #endif 118 /* 119 * for slave UCODE and ENV instored in master memory space, 120 * PHYS must be aligned based on the SIZE 121 */ 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 125 #else 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 128 #endif 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 130 /* slave core release by master*/ 131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 133 134 /* PCIe Boot - Slave */ 135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 139 /* Set 1M boot space for PCIe boot */ 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 10000000 150 #define CONFIG_ENV_SPI_MODE 0 151 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 152 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 153 #if defined(CONFIG_TARGET_T1024RDB) 154 #define CONFIG_ENV_SECT_SIZE 0x10000 155 #elif defined(CONFIG_TARGET_T1023RDB) 156 #define CONFIG_ENV_SECT_SIZE 0x40000 157 #endif 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_MMC_ENV_DEV 0 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_OFFSET (512 * 0x800) 162 #elif defined(CONFIG_NAND) 163 #define CONFIG_ENV_SIZE 0x2000 164 #if defined(CONFIG_TARGET_T1024RDB) 165 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 166 #elif defined(CONFIG_TARGET_T1023RDB) 167 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 168 #endif 169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 170 #define CONFIG_ENV_ADDR 0xffe20000 171 #define CONFIG_ENV_SIZE 0x2000 172 #elif defined(CONFIG_ENV_IS_NOWHERE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #else 175 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 178 #endif 179 180 #ifndef __ASSEMBLY__ 181 unsigned long get_board_sys_clk(void); 182 unsigned long get_board_ddr_clk(void); 183 #endif 184 185 #define CONFIG_SYS_CLK_FREQ 100000000 186 #define CONFIG_DDR_CLK_FREQ 100000000 187 188 /* 189 * These can be toggled for performance analysis, otherwise use default. 190 */ 191 #define CONFIG_SYS_CACHE_STASHING 192 #define CONFIG_BACKSIDE_L2_CACHE 193 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 194 #define CONFIG_BTB /* toggle branch predition */ 195 #define CONFIG_DDR_ECC 196 #ifdef CONFIG_DDR_ECC 197 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 198 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 199 #endif 200 201 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 202 #define CONFIG_SYS_MEMTEST_END 0x00400000 203 204 /* 205 * Config the L3 Cache as L3 SRAM 206 */ 207 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 208 #define CONFIG_SYS_L3_SIZE (256 << 10) 209 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 210 #ifdef CONFIG_RAMBOOT_PBL 211 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 212 #endif 213 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 214 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 215 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 216 217 #ifdef CONFIG_PHYS_64BIT 218 #define CONFIG_SYS_DCSRBAR 0xf0000000 219 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 220 #endif 221 222 /* EEPROM */ 223 #define CONFIG_ID_EEPROM 224 #define CONFIG_SYS_I2C_EEPROM_NXID 225 #define CONFIG_SYS_EEPROM_BUS_NUM 0 226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 230 231 /* 232 * DDR Setup 233 */ 234 #define CONFIG_VERY_BIG_RAM 235 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 236 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 237 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 238 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 239 #if defined(CONFIG_TARGET_T1024RDB) 240 #define CONFIG_DDR_SPD 241 #define CONFIG_SYS_SPD_BUS_NUM 0 242 #define SPD_EEPROM_ADDRESS 0x51 243 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 244 #elif defined(CONFIG_TARGET_T1023RDB) 245 #define CONFIG_SYS_DDR_RAW_TIMING 246 #define CONFIG_SYS_SDRAM_SIZE 2048 247 #endif 248 249 /* 250 * IFC Definitions 251 */ 252 #define CONFIG_SYS_FLASH_BASE 0xe8000000 253 #ifdef CONFIG_PHYS_64BIT 254 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 255 #else 256 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 257 #endif 258 259 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 261 CSPR_PORT_SIZE_16 | \ 262 CSPR_MSEL_NOR | \ 263 CSPR_V) 264 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 265 266 /* NOR Flash Timing Params */ 267 #if defined(CONFIG_TARGET_T1024RDB) 268 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 269 #elif defined(CONFIG_TARGET_T1023RDB) 270 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 271 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 272 #endif 273 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 274 FTIM0_NOR_TEADC(0x5) | \ 275 FTIM0_NOR_TEAHC(0x5)) 276 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 277 FTIM1_NOR_TRAD_NOR(0x1A) |\ 278 FTIM1_NOR_TSEQRAD_NOR(0x13)) 279 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 280 FTIM2_NOR_TCH(0x4) | \ 281 FTIM2_NOR_TWPH(0x0E) | \ 282 FTIM2_NOR_TWP(0x1c)) 283 #define CONFIG_SYS_NOR_FTIM3 0x0 284 285 #define CONFIG_SYS_FLASH_QUIET_TEST 286 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 287 288 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 289 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 290 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 291 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 292 293 #define CONFIG_SYS_FLASH_EMPTY_INFO 294 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 295 296 #ifdef CONFIG_TARGET_T1024RDB 297 /* CPLD on IFC */ 298 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 299 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 300 #define CONFIG_SYS_CSPR2_EXT (0xf) 301 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 302 | CSPR_PORT_SIZE_8 \ 303 | CSPR_MSEL_GPCM \ 304 | CSPR_V) 305 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 306 #define CONFIG_SYS_CSOR2 0x0 307 308 /* CPLD Timing parameters for IFC CS2 */ 309 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 310 FTIM0_GPCM_TEADC(0x0e) | \ 311 FTIM0_GPCM_TEAHC(0x0e)) 312 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 313 FTIM1_GPCM_TRAD(0x1f)) 314 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 315 FTIM2_GPCM_TCH(0x8) | \ 316 FTIM2_GPCM_TWP(0x1f)) 317 #define CONFIG_SYS_CS2_FTIM3 0x0 318 #endif 319 320 /* NAND Flash on IFC */ 321 #define CONFIG_NAND_FSL_IFC 322 #define CONFIG_SYS_NAND_BASE 0xff800000 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 325 #else 326 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 327 #endif 328 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 329 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 330 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 331 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 332 | CSPR_V) 333 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 334 335 #if defined(CONFIG_TARGET_T1024RDB) 336 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 337 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 338 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 339 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 340 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 341 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 342 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 343 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 344 #elif defined(CONFIG_TARGET_T1023RDB) 345 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 346 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 347 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 348 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 349 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 350 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 351 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 352 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 353 #endif 354 355 #define CONFIG_SYS_NAND_ONFI_DETECTION 356 /* ONFI NAND Flash mode0 Timing Params */ 357 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 358 FTIM0_NAND_TWP(0x18) | \ 359 FTIM0_NAND_TWCHT(0x07) | \ 360 FTIM0_NAND_TWH(0x0a)) 361 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 362 FTIM1_NAND_TWBE(0x39) | \ 363 FTIM1_NAND_TRR(0x0e) | \ 364 FTIM1_NAND_TRP(0x18)) 365 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 366 FTIM2_NAND_TREH(0x0a) | \ 367 FTIM2_NAND_TWHRE(0x1e)) 368 #define CONFIG_SYS_NAND_FTIM3 0x0 369 370 #define CONFIG_SYS_NAND_DDR_LAW 11 371 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 372 #define CONFIG_SYS_MAX_NAND_DEVICE 1 373 374 #if defined(CONFIG_NAND) 375 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 376 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 377 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 378 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 379 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 380 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 381 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 382 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 383 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 384 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 385 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 386 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 387 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 388 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 389 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 390 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 391 #else 392 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 393 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 394 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 395 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 396 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 397 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 398 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 399 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 400 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 401 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 402 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 403 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 404 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 405 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 406 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 407 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 408 #endif 409 410 #ifdef CONFIG_SPL_BUILD 411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 412 #else 413 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 414 #endif 415 416 #if defined(CONFIG_RAMBOOT_PBL) 417 #define CONFIG_SYS_RAMBOOT 418 #endif 419 420 #define CONFIG_HWCONFIG 421 422 /* define to use L1 as initial stack */ 423 #define CONFIG_L1_INIT_RAM 424 #define CONFIG_SYS_INIT_RAM_LOCK 425 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 429 /* The assembler doesn't like typecast */ 430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 431 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 432 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 433 #else 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 437 #endif 438 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 439 440 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 441 GENERATED_GBL_DATA_SIZE) 442 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 443 444 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 445 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 446 447 /* Serial Port */ 448 #define CONFIG_SYS_NS16550_SERIAL 449 #define CONFIG_SYS_NS16550_REG_SIZE 1 450 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 451 452 #define CONFIG_SYS_BAUDRATE_TABLE \ 453 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 454 455 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 456 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 457 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 458 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 459 460 /* Video */ 461 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 462 #ifdef CONFIG_FSL_DIU_FB 463 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 464 #define CONFIG_VIDEO_LOGO 465 #define CONFIG_VIDEO_BMP_LOGO 466 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 467 /* 468 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 469 * disable empty flash sector detection, which is I/O-intensive. 470 */ 471 #undef CONFIG_SYS_FLASH_EMPTY_INFO 472 #endif 473 474 /* I2C */ 475 #define CONFIG_SYS_I2C 476 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 477 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 478 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 479 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 480 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 481 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 482 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 483 484 #define I2C_PCA6408_BUS_NUM 1 485 #define I2C_PCA6408_ADDR 0x20 486 487 /* I2C bus multiplexer */ 488 #define I2C_MUX_CH_DEFAULT 0x8 489 490 /* 491 * RTC configuration 492 */ 493 #define RTC 494 #define CONFIG_RTC_DS1337 1 495 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 496 497 /* 498 * eSPI - Enhanced SPI 499 */ 500 #define CONFIG_SF_DEFAULT_SPEED 10000000 501 #define CONFIG_SF_DEFAULT_MODE 0 502 503 /* 504 * General PCIe 505 * Memory space is mapped 1-1, but I/O space must start from 0. 506 */ 507 #define CONFIG_PCIE1 /* PCIE controller 1 */ 508 #define CONFIG_PCIE2 /* PCIE controller 2 */ 509 #define CONFIG_PCIE3 /* PCIE controller 3 */ 510 #ifdef CONFIG_ARCH_T1040 511 #define CONFIG_PCIE4 /* PCIE controller 4 */ 512 #endif 513 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 514 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 515 #define CONFIG_PCI_INDIRECT_BRIDGE 516 517 #ifdef CONFIG_PCI 518 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 519 #ifdef CONFIG_PCIE1 520 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 521 #ifdef CONFIG_PHYS_64BIT 522 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 523 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 524 #else 525 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 526 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 527 #endif 528 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 529 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 530 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 531 #ifdef CONFIG_PHYS_64BIT 532 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 533 #else 534 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 535 #endif 536 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 537 #endif 538 539 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 540 #ifdef CONFIG_PCIE2 541 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 542 #ifdef CONFIG_PHYS_64BIT 543 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 544 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 545 #else 546 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 547 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 548 #endif 549 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 550 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 551 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 554 #else 555 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 556 #endif 557 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 558 #endif 559 560 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 561 #ifdef CONFIG_PCIE3 562 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 563 #ifdef CONFIG_PHYS_64BIT 564 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 566 #else 567 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 568 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 569 #endif 570 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 571 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 572 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 573 #ifdef CONFIG_PHYS_64BIT 574 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 575 #else 576 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 577 #endif 578 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 579 #endif 580 581 /* controller 4, Base address 203000, to be removed */ 582 #ifdef CONFIG_PCIE4 583 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 584 #ifdef CONFIG_PHYS_64BIT 585 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 586 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 587 #else 588 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 589 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 590 #endif 591 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 592 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 593 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 596 #else 597 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 598 #endif 599 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 600 #endif 601 602 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 603 #endif /* CONFIG_PCI */ 604 605 /* 606 * USB 607 */ 608 #define CONFIG_HAS_FSL_DR_USB 609 610 #ifdef CONFIG_HAS_FSL_DR_USB 611 #define CONFIG_USB_EHCI_FSL 612 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 613 #endif 614 615 /* 616 * SDHC 617 */ 618 #ifdef CONFIG_MMC 619 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 620 #endif 621 622 /* Qman/Bman */ 623 #ifndef CONFIG_NOBQFMAN 624 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 625 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 626 #ifdef CONFIG_PHYS_64BIT 627 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 628 #else 629 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 630 #endif 631 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 632 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 633 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 634 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 635 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 636 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 637 CONFIG_SYS_BMAN_CENA_SIZE) 638 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 639 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 640 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 641 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 642 #ifdef CONFIG_PHYS_64BIT 643 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 644 #else 645 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 646 #endif 647 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 648 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 649 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 650 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 651 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 653 CONFIG_SYS_QMAN_CENA_SIZE) 654 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 655 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 656 657 #define CONFIG_SYS_DPAA_FMAN 658 659 #ifdef CONFIG_TARGET_T1024RDB 660 #define CONFIG_QE 661 #endif 662 /* Default address of microcode for the Linux FMan driver */ 663 #if defined(CONFIG_SPIFLASH) 664 /* 665 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 666 * env, so we got 0x110000. 667 */ 668 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 669 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 670 #define CONFIG_SYS_QE_FW_ADDR 0x130000 671 #elif defined(CONFIG_SDCARD) 672 /* 673 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 674 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 675 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 676 */ 677 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 678 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 679 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 680 #elif defined(CONFIG_NAND) 681 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 682 #if defined(CONFIG_TARGET_T1024RDB) 683 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 684 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 685 #elif defined(CONFIG_TARGET_T1023RDB) 686 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 687 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 688 #endif 689 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 690 /* 691 * Slave has no ucode locally, it can fetch this from remote. When implementing 692 * in two corenet boards, slave's ucode could be stored in master's memory 693 * space, the address can be mapped from slave TLB->slave LAW-> 694 * slave SRIO or PCIE outbound window->master inbound window-> 695 * master LAW->the ucode address in master's memory space. 696 */ 697 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 698 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 699 #else 700 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 701 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 702 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 703 #endif 704 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 705 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 706 #endif /* CONFIG_NOBQFMAN */ 707 708 #ifdef CONFIG_SYS_DPAA_FMAN 709 #define CONFIG_FMAN_ENET 710 #define CONFIG_PHY_REALTEK 711 #if defined(CONFIG_TARGET_T1024RDB) 712 #define RGMII_PHY1_ADDR 0x2 713 #define RGMII_PHY2_ADDR 0x6 714 #define SGMII_AQR_PHY_ADDR 0x2 715 #define FM1_10GEC1_PHY_ADDR 0x1 716 #elif defined(CONFIG_TARGET_T1023RDB) 717 #define RGMII_PHY1_ADDR 0x1 718 #define SGMII_RTK_PHY_ADDR 0x3 719 #define SGMII_AQR_PHY_ADDR 0x2 720 #endif 721 #endif 722 723 #ifdef CONFIG_FMAN_ENET 724 #define CONFIG_ETHPRIME "FM1@DTSEC4" 725 #endif 726 727 /* 728 * Dynamic MTD Partition support with mtdparts 729 */ 730 731 /* 732 * Environment 733 */ 734 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 735 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 736 737 /* 738 * Miscellaneous configurable options 739 */ 740 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 741 742 /* 743 * For booting Linux, the board info and command line data 744 * have to be in the first 64 MB of memory, since this is 745 * the maximum mapped by the Linux kernel during initialization. 746 */ 747 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 748 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 749 750 #ifdef CONFIG_CMD_KGDB 751 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 752 #endif 753 754 /* 755 * Environment Configuration 756 */ 757 #define CONFIG_ROOTPATH "/opt/nfsroot" 758 #define CONFIG_BOOTFILE "uImage" 759 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 760 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 761 #define __USB_PHY_TYPE utmi 762 763 #ifdef CONFIG_ARCH_T1024 764 #define CONFIG_BOARDNAME t1024rdb 765 #define BANK_INTLV cs0_cs1 766 #else 767 #define CONFIG_BOARDNAME t1023rdb 768 #define BANK_INTLV null 769 #endif 770 771 #define CONFIG_EXTRA_ENV_SETTINGS \ 772 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 773 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 774 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 775 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 776 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 777 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 778 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 779 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 780 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 781 "netdev=eth0\0" \ 782 "tftpflash=tftpboot $loadaddr $uboot && " \ 783 "protect off $ubootaddr +$filesize && " \ 784 "erase $ubootaddr +$filesize && " \ 785 "cp.b $loadaddr $ubootaddr $filesize && " \ 786 "protect on $ubootaddr +$filesize && " \ 787 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 788 "consoledev=ttyS0\0" \ 789 "ramdiskaddr=2000000\0" \ 790 "fdtaddr=1e00000\0" \ 791 "bdev=sda3\0" 792 793 #define CONFIG_LINUX \ 794 "setenv bootargs root=/dev/ram rw " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "setenv ramdiskaddr 0x02000000;" \ 797 "setenv fdtaddr 0x00c00000;" \ 798 "setenv loadaddr 0x1000000;" \ 799 "bootm $loadaddr $ramdiskaddr $fdtaddr" 800 801 #define CONFIG_NFSBOOTCOMMAND \ 802 "setenv bootargs root=/dev/nfs rw " \ 803 "nfsroot=$serverip:$rootpath " \ 804 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 805 "console=$consoledev,$baudrate $othbootargs;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr - $fdtaddr" 809 810 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 811 812 #include <asm/fsl_secure_boot.h> 813 814 #endif /* __T1024RDB_H */ 815