1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 RDB board configuration file 8 */ 9 10 #ifndef __T1024RDB_H 11 #define __T1024RDB_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 /* support deep sleep */ 28 #ifdef CONFIG_ARCH_T1024 29 #define CONFIG_DEEP_SLEEP 30 #endif 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define RESET_VECTOR_OFFSET 0x27FFC 40 #define BOOT_PAGE_OFFSET 0x27000 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SPL_SKIP_RELOCATE 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 45 #endif 46 47 #ifdef CONFIG_NAND 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 53 #if defined(CONFIG_TARGET_T1024RDB) 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 55 #elif defined(CONFIG_TARGET_T1023RDB) 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 57 #endif 58 #define CONFIG_SPL_NAND_BOOT 59 #endif 60 61 #ifdef CONFIG_SPIFLASH 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 63 #define CONFIG_SPL_SPI_FLASH_MINIMAL 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 69 #ifndef CONFIG_SPL_BUILD 70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 71 #endif 72 #if defined(CONFIG_TARGET_T1024RDB) 73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 74 #elif defined(CONFIG_TARGET_T1023RDB) 75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 76 #endif 77 #define CONFIG_SPL_SPI_BOOT 78 #endif 79 80 #ifdef CONFIG_SDCARD 81 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 82 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 83 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 84 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 85 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 86 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 87 #ifndef CONFIG_SPL_BUILD 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #endif 90 #if defined(CONFIG_TARGET_T1024RDB) 91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 92 #elif defined(CONFIG_TARGET_T1023RDB) 93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 94 #endif 95 #define CONFIG_SPL_MMC_BOOT 96 #endif 97 98 #endif /* CONFIG_RAMBOOT_PBL */ 99 100 #ifndef CONFIG_RESET_VECTOR_ADDRESS 101 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 102 #endif 103 104 #ifdef CONFIG_MTD_NOR_FLASH 105 #define CONFIG_FLASH_CFI_DRIVER 106 #define CONFIG_SYS_FLASH_CFI 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 108 #endif 109 110 /* PCIe Boot - Master */ 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER 112 /* 113 * for slave u-boot IMAGE instored in master memory space, 114 * PHYS must be aligned based on the SIZE 115 */ 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 118 #ifdef CONFIG_PHYS_64BIT 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 121 #else 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 124 #endif 125 /* 126 * for slave UCODE and ENV instored in master memory space, 127 * PHYS must be aligned based on the SIZE 128 */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 132 #else 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 135 #endif 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 137 /* slave core release by master*/ 138 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 139 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 140 141 /* PCIe Boot - Slave */ 142 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 145 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 146 /* Set 1M boot space for PCIe boot */ 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 149 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 151 #endif 152 153 #if defined(CONFIG_SPIFLASH) 154 #define CONFIG_SYS_EXTRA_ENV_RELOC 155 #define CONFIG_ENV_SPI_BUS 0 156 #define CONFIG_ENV_SPI_CS 0 157 #define CONFIG_ENV_SPI_MAX_HZ 10000000 158 #define CONFIG_ENV_SPI_MODE 0 159 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 160 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 161 #if defined(CONFIG_TARGET_T1024RDB) 162 #define CONFIG_ENV_SECT_SIZE 0x10000 163 #elif defined(CONFIG_TARGET_T1023RDB) 164 #define CONFIG_ENV_SECT_SIZE 0x40000 165 #endif 166 #elif defined(CONFIG_SDCARD) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_SYS_MMC_ENV_DEV 0 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_OFFSET (512 * 0x800) 171 #elif defined(CONFIG_NAND) 172 #define CONFIG_SYS_EXTRA_ENV_RELOC 173 #define CONFIG_ENV_SIZE 0x2000 174 #if defined(CONFIG_TARGET_T1024RDB) 175 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 176 #elif defined(CONFIG_TARGET_T1023RDB) 177 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 178 #endif 179 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 180 #define CONFIG_ENV_ADDR 0xffe20000 181 #define CONFIG_ENV_SIZE 0x2000 182 #elif defined(CONFIG_ENV_IS_NOWHERE) 183 #define CONFIG_ENV_SIZE 0x2000 184 #else 185 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 188 #endif 189 190 #ifndef __ASSEMBLY__ 191 unsigned long get_board_sys_clk(void); 192 unsigned long get_board_ddr_clk(void); 193 #endif 194 195 #define CONFIG_SYS_CLK_FREQ 100000000 196 #define CONFIG_DDR_CLK_FREQ 100000000 197 198 /* 199 * These can be toggled for performance analysis, otherwise use default. 200 */ 201 #define CONFIG_SYS_CACHE_STASHING 202 #define CONFIG_BACKSIDE_L2_CACHE 203 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 204 #define CONFIG_BTB /* toggle branch predition */ 205 #define CONFIG_DDR_ECC 206 #ifdef CONFIG_DDR_ECC 207 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 208 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 209 #endif 210 211 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 212 #define CONFIG_SYS_MEMTEST_END 0x00400000 213 214 /* 215 * Config the L3 Cache as L3 SRAM 216 */ 217 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 218 #define CONFIG_SYS_L3_SIZE (256 << 10) 219 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 220 #ifdef CONFIG_RAMBOOT_PBL 221 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 222 #endif 223 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 224 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 225 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 226 227 #ifdef CONFIG_PHYS_64BIT 228 #define CONFIG_SYS_DCSRBAR 0xf0000000 229 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 230 #endif 231 232 /* EEPROM */ 233 #define CONFIG_ID_EEPROM 234 #define CONFIG_SYS_I2C_EEPROM_NXID 235 #define CONFIG_SYS_EEPROM_BUS_NUM 0 236 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 237 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 240 241 /* 242 * DDR Setup 243 */ 244 #define CONFIG_VERY_BIG_RAM 245 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 246 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 247 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 248 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 249 #define CONFIG_FSL_DDR_INTERACTIVE 250 #if defined(CONFIG_TARGET_T1024RDB) 251 #define CONFIG_DDR_SPD 252 #define CONFIG_SYS_SPD_BUS_NUM 0 253 #define SPD_EEPROM_ADDRESS 0x51 254 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 255 #elif defined(CONFIG_TARGET_T1023RDB) 256 #define CONFIG_SYS_DDR_RAW_TIMING 257 #define CONFIG_SYS_SDRAM_SIZE 2048 258 #endif 259 260 /* 261 * IFC Definitions 262 */ 263 #define CONFIG_SYS_FLASH_BASE 0xe8000000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 266 #else 267 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 268 #endif 269 270 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 271 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 272 CSPR_PORT_SIZE_16 | \ 273 CSPR_MSEL_NOR | \ 274 CSPR_V) 275 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 276 277 /* NOR Flash Timing Params */ 278 #if defined(CONFIG_TARGET_T1024RDB) 279 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 280 #elif defined(CONFIG_TARGET_T1023RDB) 281 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 282 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 283 #endif 284 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 285 FTIM0_NOR_TEADC(0x5) | \ 286 FTIM0_NOR_TEAHC(0x5)) 287 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 288 FTIM1_NOR_TRAD_NOR(0x1A) |\ 289 FTIM1_NOR_TSEQRAD_NOR(0x13)) 290 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 291 FTIM2_NOR_TCH(0x4) | \ 292 FTIM2_NOR_TWPH(0x0E) | \ 293 FTIM2_NOR_TWP(0x1c)) 294 #define CONFIG_SYS_NOR_FTIM3 0x0 295 296 #define CONFIG_SYS_FLASH_QUIET_TEST 297 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 298 299 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 300 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 301 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 302 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 303 304 #define CONFIG_SYS_FLASH_EMPTY_INFO 305 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 306 307 #ifdef CONFIG_TARGET_T1024RDB 308 /* CPLD on IFC */ 309 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 310 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 311 #define CONFIG_SYS_CSPR2_EXT (0xf) 312 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 313 | CSPR_PORT_SIZE_8 \ 314 | CSPR_MSEL_GPCM \ 315 | CSPR_V) 316 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 317 #define CONFIG_SYS_CSOR2 0x0 318 319 /* CPLD Timing parameters for IFC CS2 */ 320 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 321 FTIM0_GPCM_TEADC(0x0e) | \ 322 FTIM0_GPCM_TEAHC(0x0e)) 323 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 324 FTIM1_GPCM_TRAD(0x1f)) 325 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 326 FTIM2_GPCM_TCH(0x8) | \ 327 FTIM2_GPCM_TWP(0x1f)) 328 #define CONFIG_SYS_CS2_FTIM3 0x0 329 #endif 330 331 /* NAND Flash on IFC */ 332 #define CONFIG_NAND_FSL_IFC 333 #define CONFIG_SYS_NAND_BASE 0xff800000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 336 #else 337 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 338 #endif 339 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 340 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 341 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 342 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 343 | CSPR_V) 344 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 345 346 #if defined(CONFIG_TARGET_T1024RDB) 347 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 348 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 349 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 350 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 351 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 352 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 353 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 354 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 355 #elif defined(CONFIG_TARGET_T1023RDB) 356 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 357 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 358 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 359 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 360 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 361 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 362 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 363 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 364 #endif 365 366 #define CONFIG_SYS_NAND_ONFI_DETECTION 367 /* ONFI NAND Flash mode0 Timing Params */ 368 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 369 FTIM0_NAND_TWP(0x18) | \ 370 FTIM0_NAND_TWCHT(0x07) | \ 371 FTIM0_NAND_TWH(0x0a)) 372 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 373 FTIM1_NAND_TWBE(0x39) | \ 374 FTIM1_NAND_TRR(0x0e) | \ 375 FTIM1_NAND_TRP(0x18)) 376 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 377 FTIM2_NAND_TREH(0x0a) | \ 378 FTIM2_NAND_TWHRE(0x1e)) 379 #define CONFIG_SYS_NAND_FTIM3 0x0 380 381 #define CONFIG_SYS_NAND_DDR_LAW 11 382 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 383 #define CONFIG_SYS_MAX_NAND_DEVICE 1 384 385 #if defined(CONFIG_NAND) 386 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 387 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 388 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 389 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 390 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 391 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 392 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 393 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 394 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 395 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 396 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 397 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 398 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 399 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 400 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 401 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 402 #else 403 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 404 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 405 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 406 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 407 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 408 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 409 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 410 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 411 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 412 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 413 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 414 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 415 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 416 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 417 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 418 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 419 #endif 420 421 #ifdef CONFIG_SPL_BUILD 422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 423 #else 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 425 #endif 426 427 #if defined(CONFIG_RAMBOOT_PBL) 428 #define CONFIG_SYS_RAMBOOT 429 #endif 430 431 #define CONFIG_MISC_INIT_R 432 433 #define CONFIG_HWCONFIG 434 435 /* define to use L1 as initial stack */ 436 #define CONFIG_L1_INIT_RAM 437 #define CONFIG_SYS_INIT_RAM_LOCK 438 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 442 /* The assembler doesn't like typecast */ 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 444 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 445 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 446 #else 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 450 #endif 451 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 452 453 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 454 GENERATED_GBL_DATA_SIZE) 455 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 456 457 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 458 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 459 460 /* Serial Port */ 461 #define CONFIG_SYS_NS16550_SERIAL 462 #define CONFIG_SYS_NS16550_REG_SIZE 1 463 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 464 465 #define CONFIG_SYS_BAUDRATE_TABLE \ 466 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 467 468 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 469 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 470 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 471 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 472 473 /* Video */ 474 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 475 #ifdef CONFIG_FSL_DIU_FB 476 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 477 #define CONFIG_VIDEO_LOGO 478 #define CONFIG_VIDEO_BMP_LOGO 479 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 480 /* 481 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 482 * disable empty flash sector detection, which is I/O-intensive. 483 */ 484 #undef CONFIG_SYS_FLASH_EMPTY_INFO 485 #endif 486 487 /* I2C */ 488 #define CONFIG_SYS_I2C 489 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 490 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 491 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 492 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 493 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 494 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 495 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 496 497 #define I2C_PCA6408_BUS_NUM 1 498 #define I2C_PCA6408_ADDR 0x20 499 500 /* I2C bus multiplexer */ 501 #define I2C_MUX_CH_DEFAULT 0x8 502 503 /* 504 * RTC configuration 505 */ 506 #define RTC 507 #define CONFIG_RTC_DS1337 1 508 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 509 510 /* 511 * eSPI - Enhanced SPI 512 */ 513 #define CONFIG_SPI_FLASH_BAR 514 #define CONFIG_SF_DEFAULT_SPEED 10000000 515 #define CONFIG_SF_DEFAULT_MODE 0 516 517 /* 518 * General PCIe 519 * Memory space is mapped 1-1, but I/O space must start from 0. 520 */ 521 #define CONFIG_PCIE1 /* PCIE controller 1 */ 522 #define CONFIG_PCIE2 /* PCIE controller 2 */ 523 #define CONFIG_PCIE3 /* PCIE controller 3 */ 524 #ifdef CONFIG_ARCH_T1040 525 #define CONFIG_PCIE4 /* PCIE controller 4 */ 526 #endif 527 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 528 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 529 #define CONFIG_PCI_INDIRECT_BRIDGE 530 531 #ifdef CONFIG_PCI 532 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 533 #ifdef CONFIG_PCIE1 534 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 535 #ifdef CONFIG_PHYS_64BIT 536 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 537 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 538 #else 539 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 540 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 541 #endif 542 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 543 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 544 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 545 #ifdef CONFIG_PHYS_64BIT 546 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 547 #else 548 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 549 #endif 550 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 551 #endif 552 553 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 554 #ifdef CONFIG_PCIE2 555 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 556 #ifdef CONFIG_PHYS_64BIT 557 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 558 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 559 #else 560 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 561 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 562 #endif 563 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 564 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 565 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 566 #ifdef CONFIG_PHYS_64BIT 567 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 568 #else 569 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 570 #endif 571 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 572 #endif 573 574 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 575 #ifdef CONFIG_PCIE3 576 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 577 #ifdef CONFIG_PHYS_64BIT 578 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 580 #else 581 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 582 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 583 #endif 584 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 585 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 586 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 587 #ifdef CONFIG_PHYS_64BIT 588 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 589 #else 590 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 591 #endif 592 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 593 #endif 594 595 /* controller 4, Base address 203000, to be removed */ 596 #ifdef CONFIG_PCIE4 597 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 598 #ifdef CONFIG_PHYS_64BIT 599 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 600 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 601 #else 602 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 603 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 604 #endif 605 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 606 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 607 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 608 #ifdef CONFIG_PHYS_64BIT 609 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 610 #else 611 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 612 #endif 613 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 614 #endif 615 616 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 617 #endif /* CONFIG_PCI */ 618 619 /* 620 * USB 621 */ 622 #define CONFIG_HAS_FSL_DR_USB 623 624 #ifdef CONFIG_HAS_FSL_DR_USB 625 #define CONFIG_USB_EHCI_FSL 626 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 627 #endif 628 629 /* 630 * SDHC 631 */ 632 #ifdef CONFIG_MMC 633 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 634 #endif 635 636 /* Qman/Bman */ 637 #ifndef CONFIG_NOBQFMAN 638 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 639 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 640 #ifdef CONFIG_PHYS_64BIT 641 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 642 #else 643 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 644 #endif 645 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 646 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 647 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 648 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 649 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 650 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 651 CONFIG_SYS_BMAN_CENA_SIZE) 652 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 653 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 654 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 655 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 656 #ifdef CONFIG_PHYS_64BIT 657 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 658 #else 659 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 660 #endif 661 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 662 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 663 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 664 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 665 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 666 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 667 CONFIG_SYS_QMAN_CENA_SIZE) 668 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 669 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 670 671 #define CONFIG_SYS_DPAA_FMAN 672 673 #ifdef CONFIG_TARGET_T1024RDB 674 #define CONFIG_QE 675 #define CONFIG_U_QE 676 #endif 677 /* Default address of microcode for the Linux FMan driver */ 678 #if defined(CONFIG_SPIFLASH) 679 /* 680 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 681 * env, so we got 0x110000. 682 */ 683 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 684 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 685 #define CONFIG_SYS_QE_FW_ADDR 0x130000 686 #elif defined(CONFIG_SDCARD) 687 /* 688 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 689 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 690 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 691 */ 692 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 693 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 694 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 695 #elif defined(CONFIG_NAND) 696 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 697 #if defined(CONFIG_TARGET_T1024RDB) 698 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 699 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 700 #elif defined(CONFIG_TARGET_T1023RDB) 701 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 702 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 703 #endif 704 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 705 /* 706 * Slave has no ucode locally, it can fetch this from remote. When implementing 707 * in two corenet boards, slave's ucode could be stored in master's memory 708 * space, the address can be mapped from slave TLB->slave LAW-> 709 * slave SRIO or PCIE outbound window->master inbound window-> 710 * master LAW->the ucode address in master's memory space. 711 */ 712 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 713 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 714 #else 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 716 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 717 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 718 #endif 719 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 720 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 721 #endif /* CONFIG_NOBQFMAN */ 722 723 #ifdef CONFIG_SYS_DPAA_FMAN 724 #define CONFIG_FMAN_ENET 725 #define CONFIG_PHYLIB_10G 726 #define CONFIG_PHY_REALTEK 727 #define CONFIG_PHY_AQUANTIA 728 #if defined(CONFIG_TARGET_T1024RDB) 729 #define RGMII_PHY1_ADDR 0x2 730 #define RGMII_PHY2_ADDR 0x6 731 #define SGMII_AQR_PHY_ADDR 0x2 732 #define FM1_10GEC1_PHY_ADDR 0x1 733 #elif defined(CONFIG_TARGET_T1023RDB) 734 #define RGMII_PHY1_ADDR 0x1 735 #define SGMII_RTK_PHY_ADDR 0x3 736 #define SGMII_AQR_PHY_ADDR 0x2 737 #endif 738 #endif 739 740 #ifdef CONFIG_FMAN_ENET 741 #define CONFIG_MII /* MII PHY management */ 742 #define CONFIG_ETHPRIME "FM1@DTSEC4" 743 #endif 744 745 /* 746 * Dynamic MTD Partition support with mtdparts 747 */ 748 #ifdef CONFIG_MTD_NOR_FLASH 749 #define CONFIG_FLASH_CFI_MTD 750 #endif 751 752 /* 753 * Environment 754 */ 755 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 756 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 757 758 /* 759 * Miscellaneous configurable options 760 */ 761 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 762 763 /* 764 * For booting Linux, the board info and command line data 765 * have to be in the first 64 MB of memory, since this is 766 * the maximum mapped by the Linux kernel during initialization. 767 */ 768 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 769 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 770 771 #ifdef CONFIG_CMD_KGDB 772 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 773 #endif 774 775 /* 776 * Environment Configuration 777 */ 778 #define CONFIG_ROOTPATH "/opt/nfsroot" 779 #define CONFIG_BOOTFILE "uImage" 780 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 781 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 782 #define __USB_PHY_TYPE utmi 783 784 #ifdef CONFIG_ARCH_T1024 785 #define CONFIG_BOARDNAME t1024rdb 786 #define BANK_INTLV cs0_cs1 787 #else 788 #define CONFIG_BOARDNAME t1023rdb 789 #define BANK_INTLV null 790 #endif 791 792 #define CONFIG_EXTRA_ENV_SETTINGS \ 793 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 794 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 795 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 796 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 797 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 798 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 799 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 800 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 801 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 802 "netdev=eth0\0" \ 803 "tftpflash=tftpboot $loadaddr $uboot && " \ 804 "protect off $ubootaddr +$filesize && " \ 805 "erase $ubootaddr +$filesize && " \ 806 "cp.b $loadaddr $ubootaddr $filesize && " \ 807 "protect on $ubootaddr +$filesize && " \ 808 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 809 "consoledev=ttyS0\0" \ 810 "ramdiskaddr=2000000\0" \ 811 "fdtaddr=1e00000\0" \ 812 "bdev=sda3\0" 813 814 #define CONFIG_LINUX \ 815 "setenv bootargs root=/dev/ram rw " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "setenv ramdiskaddr 0x02000000;" \ 818 "setenv fdtaddr 0x00c00000;" \ 819 "setenv loadaddr 0x1000000;" \ 820 "bootm $loadaddr $ramdiskaddr $fdtaddr" 821 822 #define CONFIG_NFSBOOTCOMMAND \ 823 "setenv bootargs root=/dev/nfs rw " \ 824 "nfsroot=$serverip:$rootpath " \ 825 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 826 "console=$consoledev,$baudrate $othbootargs;" \ 827 "tftp $loadaddr $bootfile;" \ 828 "tftp $fdtaddr $fdtfile;" \ 829 "bootm $loadaddr - $fdtaddr" 830 831 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 832 833 #include <asm/fsl_secure_boot.h> 834 835 #endif /* __T1024RDB_H */ 836