148c6f328SShengzhou Liu /* 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 348c6f328SShengzhou Liu * 448c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 548c6f328SShengzhou Liu */ 648c6f328SShengzhou Liu 748c6f328SShengzhou Liu /* 848c6f328SShengzhou Liu * T1024/T1023 RDB board configuration file 948c6f328SShengzhou Liu */ 1048c6f328SShengzhou Liu 1148c6f328SShengzhou Liu #ifndef __T1024RDB_H 1248c6f328SShengzhou Liu #define __T1024RDB_H 1348c6f328SShengzhou Liu 1448c6f328SShengzhou Liu /* High Level Configuration Options */ 1548c6f328SShengzhou Liu #define CONFIG_SYS_GENERIC_BOARD 1648c6f328SShengzhou Liu #define CONFIG_DISPLAY_BOARDINFO 1748c6f328SShengzhou Liu #define CONFIG_BOOKE 1848c6f328SShengzhou Liu #define CONFIG_E500 /* BOOKE e500 family */ 1948c6f328SShengzhou Liu #define CONFIG_E500MC /* BOOKE e500mc family */ 2048c6f328SShengzhou Liu #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 2148c6f328SShengzhou Liu #define CONFIG_MP /* support multiple processors */ 2248c6f328SShengzhou Liu #define CONFIG_PHYS_64BIT 2348c6f328SShengzhou Liu #define CONFIG_ENABLE_36BIT_PHYS 2448c6f328SShengzhou Liu 2548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 2648c6f328SShengzhou Liu #define CONFIG_ADDR_MAP 1 2748c6f328SShengzhou Liu #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 2848c6f328SShengzhou Liu #endif 2948c6f328SShengzhou Liu 3048c6f328SShengzhou Liu #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 3148c6f328SShengzhou Liu #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 3248c6f328SShengzhou Liu #define CONFIG_FSL_IFC /* Enable IFC Support */ 3348c6f328SShengzhou Liu 3448c6f328SShengzhou Liu #define CONFIG_FSL_LAW /* Use common FSL init code */ 3548c6f328SShengzhou Liu #define CONFIG_ENV_OVERWRITE 3648c6f328SShengzhou Liu 3748c6f328SShengzhou Liu /* support deep sleep */ 3848c6f328SShengzhou Liu #define CONFIG_DEEP_SLEEP 39*f49b8c1bStang yuantian #if defined(CONFIG_DEEP_SLEEP) 4048c6f328SShengzhou Liu #define CONFIG_SILENT_CONSOLE 41*f49b8c1bStang yuantian #define CONFIG_BOARD_EARLY_INIT_F 42*f49b8c1bStang yuantian #endif 4348c6f328SShengzhou Liu 4448c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 4548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 4648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 4748c6f328SShengzhou Liu #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 4848c6f328SShengzhou Liu #define CONFIG_SPL_ENV_SUPPORT 4948c6f328SShengzhou Liu #define CONFIG_SPL_SERIAL_SUPPORT 5048c6f328SShengzhou Liu #define CONFIG_SPL_FLUSH_IMAGE 5148c6f328SShengzhou Liu #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 5248c6f328SShengzhou Liu #define CONFIG_SPL_LIBGENERIC_SUPPORT 5348c6f328SShengzhou Liu #define CONFIG_SPL_LIBCOMMON_SUPPORT 5448c6f328SShengzhou Liu #define CONFIG_SPL_I2C_SUPPORT 5548c6f328SShengzhou Liu #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 5648c6f328SShengzhou Liu #define CONFIG_FSL_LAW /* Use common FSL init code */ 57*f49b8c1bStang yuantian #define CONFIG_SYS_TEXT_BASE 0x30001000 5848c6f328SShengzhou Liu #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 5948c6f328SShengzhou Liu #define CONFIG_SPL_PAD_TO 0x40000 6048c6f328SShengzhou Liu #define CONFIG_SPL_MAX_SIZE 0x28000 6148c6f328SShengzhou Liu #define RESET_VECTOR_OFFSET 0x27FFC 6248c6f328SShengzhou Liu #define BOOT_PAGE_OFFSET 0x27000 6348c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 6448c6f328SShengzhou Liu #define CONFIG_SPL_SKIP_RELOCATE 6548c6f328SShengzhou Liu #define CONFIG_SPL_COMMON_INIT_DDR 6648c6f328SShengzhou Liu #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 6748c6f328SShengzhou Liu #define CONFIG_SYS_NO_FLASH 6848c6f328SShengzhou Liu #endif 6948c6f328SShengzhou Liu 7048c6f328SShengzhou Liu #ifdef CONFIG_NAND 7148c6f328SShengzhou Liu #define CONFIG_SPL_NAND_SUPPORT 7248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 73*f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 74*f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 7548c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 7648c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 7748c6f328SShengzhou Liu #define CONFIG_SPL_NAND_BOOT 7848c6f328SShengzhou Liu #endif 7948c6f328SShengzhou Liu 8048c6f328SShengzhou Liu #ifdef CONFIG_SPIFLASH 81*f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 8248c6f328SShengzhou Liu #define CONFIG_SPL_SPI_SUPPORT 8348c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_SUPPORT 8448c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_MINIMAL 8548c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86*f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87*f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 8848c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 8948c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 9048c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 9148c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 9248c6f328SShengzhou Liu #endif 9348c6f328SShengzhou Liu #define CONFIG_SPL_SPI_BOOT 9448c6f328SShengzhou Liu #endif 9548c6f328SShengzhou Liu 9648c6f328SShengzhou Liu #ifdef CONFIG_SDCARD 97*f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 9848c6f328SShengzhou Liu #define CONFIG_SPL_MMC_SUPPORT 9948c6f328SShengzhou Liu #define CONFIG_SPL_MMC_MINIMAL 10048c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101*f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 102*f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 10348c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 10448c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 10548c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 10648c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 10748c6f328SShengzhou Liu #endif 10848c6f328SShengzhou Liu #define CONFIG_SPL_MMC_BOOT 10948c6f328SShengzhou Liu #endif 11048c6f328SShengzhou Liu 11148c6f328SShengzhou Liu #endif /* CONFIG_RAMBOOT_PBL */ 11248c6f328SShengzhou Liu 11348c6f328SShengzhou Liu #ifndef CONFIG_SYS_TEXT_BASE 11448c6f328SShengzhou Liu #define CONFIG_SYS_TEXT_BASE 0xeff40000 11548c6f328SShengzhou Liu #endif 11648c6f328SShengzhou Liu 11748c6f328SShengzhou Liu #ifndef CONFIG_RESET_VECTOR_ADDRESS 11848c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 11948c6f328SShengzhou Liu #endif 12048c6f328SShengzhou Liu 12148c6f328SShengzhou Liu #ifndef CONFIG_SYS_NO_FLASH 12248c6f328SShengzhou Liu #define CONFIG_FLASH_CFI_DRIVER 12348c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_CFI 12448c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 12548c6f328SShengzhou Liu #endif 12648c6f328SShengzhou Liu 12748c6f328SShengzhou Liu /* PCIe Boot - Master */ 12848c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_MASTER 12948c6f328SShengzhou Liu /* 13048c6f328SShengzhou Liu * for slave u-boot IMAGE instored in master memory space, 13148c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 13248c6f328SShengzhou Liu */ 13348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 13448c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 13548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 13648c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 13748c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 13848c6f328SShengzhou Liu #else 13948c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 14048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 14148c6f328SShengzhou Liu #endif 14248c6f328SShengzhou Liu /* 14348c6f328SShengzhou Liu * for slave UCODE and ENV instored in master memory space, 14448c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 14548c6f328SShengzhou Liu */ 14648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 14748c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 14848c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 14948c6f328SShengzhou Liu #else 15048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 15148c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 15248c6f328SShengzhou Liu #endif 15348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 15448c6f328SShengzhou Liu /* slave core release by master*/ 15548c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 15648c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 15748c6f328SShengzhou Liu 15848c6f328SShengzhou Liu /* PCIe Boot - Slave */ 15948c6f328SShengzhou Liu #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 16048c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 16148c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 16248c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 16348c6f328SShengzhou Liu /* Set 1M boot space for PCIe boot */ 16448c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 16548c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 16648c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 16748c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16848c6f328SShengzhou Liu #define CONFIG_SYS_NO_FLASH 16948c6f328SShengzhou Liu #endif 17048c6f328SShengzhou Liu 17148c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 17248c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 17348c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_SPI_FLASH 17448c6f328SShengzhou Liu #define CONFIG_ENV_SPI_BUS 0 17548c6f328SShengzhou Liu #define CONFIG_ENV_SPI_CS 0 17648c6f328SShengzhou Liu #define CONFIG_ENV_SPI_MAX_HZ 10000000 17748c6f328SShengzhou Liu #define CONFIG_ENV_SPI_MODE 0 17848c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 17948c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 18048c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x10000 18148c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 18248c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 18348c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_MMC 18448c6f328SShengzhou Liu #define CONFIG_SYS_MMC_ENV_DEV 0 18548c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 18648c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (512 * 0x800) 18748c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 18848c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 18948c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_NAND 19048c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 19148c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 19248c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 19348c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_REMOTE 19448c6f328SShengzhou Liu #define CONFIG_ENV_ADDR 0xffe20000 19548c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 19648c6f328SShengzhou Liu #elif defined(CONFIG_ENV_IS_NOWHERE) 19748c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 19848c6f328SShengzhou Liu #else 19948c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_FLASH 20048c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 20148c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 20248c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 20348c6f328SShengzhou Liu #endif 20448c6f328SShengzhou Liu 20548c6f328SShengzhou Liu 20648c6f328SShengzhou Liu #ifndef __ASSEMBLY__ 20748c6f328SShengzhou Liu unsigned long get_board_sys_clk(void); 20848c6f328SShengzhou Liu unsigned long get_board_ddr_clk(void); 20948c6f328SShengzhou Liu #endif 21048c6f328SShengzhou Liu 21148c6f328SShengzhou Liu #define CONFIG_SYS_CLK_FREQ 100000000 21248c6f328SShengzhou Liu #define CONFIG_DDR_CLK_FREQ 66660000 21348c6f328SShengzhou Liu 21448c6f328SShengzhou Liu /* 21548c6f328SShengzhou Liu * These can be toggled for performance analysis, otherwise use default. 21648c6f328SShengzhou Liu */ 21748c6f328SShengzhou Liu #define CONFIG_SYS_CACHE_STASHING 21848c6f328SShengzhou Liu #define CONFIG_BACKSIDE_L2_CACHE 21948c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 22048c6f328SShengzhou Liu #define CONFIG_BTB /* toggle branch predition */ 22148c6f328SShengzhou Liu #define CONFIG_DDR_ECC 22248c6f328SShengzhou Liu #ifdef CONFIG_DDR_ECC 22348c6f328SShengzhou Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 22448c6f328SShengzhou Liu #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 22548c6f328SShengzhou Liu #endif 22648c6f328SShengzhou Liu 22748c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 22848c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_END 0x00400000 22948c6f328SShengzhou Liu #define CONFIG_SYS_ALT_MEMTEST 23048c6f328SShengzhou Liu #define CONFIG_PANIC_HANG /* do not reset board on panic */ 23148c6f328SShengzhou Liu 23248c6f328SShengzhou Liu /* 23348c6f328SShengzhou Liu * Config the L3 Cache as L3 SRAM 23448c6f328SShengzhou Liu */ 23548c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 23648c6f328SShengzhou Liu #define CONFIG_SYS_L3_SIZE (256 << 10) 23748c6f328SShengzhou Liu #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 23848c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 23948c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 24048c6f328SShengzhou Liu #endif 24148c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 24248c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 24348c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 24448c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 24548c6f328SShengzhou Liu 24648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 24748c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR 0xf0000000 24848c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 24948c6f328SShengzhou Liu #endif 25048c6f328SShengzhou Liu 25148c6f328SShengzhou Liu /* EEPROM */ 25248c6f328SShengzhou Liu #define CONFIG_ID_EEPROM 25348c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_NXID 25448c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_BUS_NUM 0 25548c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 25648c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 25748c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 25848c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 25948c6f328SShengzhou Liu 26048c6f328SShengzhou Liu /* 26148c6f328SShengzhou Liu * DDR Setup 26248c6f328SShengzhou Liu */ 26348c6f328SShengzhou Liu #define CONFIG_VERY_BIG_RAM 26448c6f328SShengzhou Liu #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 26548c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 26648c6f328SShengzhou Liu #define CONFIG_DIMM_SLOTS_PER_CTLR 1 26748c6f328SShengzhou Liu #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 26848c6f328SShengzhou Liu #define CONFIG_DDR_SPD 26948c6f328SShengzhou Liu #define CONFIG_SYS_FSL_DDR3 27048c6f328SShengzhou Liu 27148c6f328SShengzhou Liu #define CONFIG_SYS_SPD_BUS_NUM 0 27248c6f328SShengzhou Liu #define SPD_EEPROM_ADDRESS 0x51 27348c6f328SShengzhou Liu 27448c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 27548c6f328SShengzhou Liu 27648c6f328SShengzhou Liu /* 27748c6f328SShengzhou Liu * IFC Definitions 27848c6f328SShengzhou Liu */ 27948c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE 0xe8000000 28048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 28148c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 28248c6f328SShengzhou Liu #else 28348c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 28448c6f328SShengzhou Liu #endif 28548c6f328SShengzhou Liu 28648c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 28748c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 28848c6f328SShengzhou Liu CSPR_PORT_SIZE_16 | \ 28948c6f328SShengzhou Liu CSPR_MSEL_NOR | \ 29048c6f328SShengzhou Liu CSPR_V) 29148c6f328SShengzhou Liu #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 29248c6f328SShengzhou Liu 29348c6f328SShengzhou Liu /* NOR Flash Timing Params */ 29448c6f328SShengzhou Liu #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 29548c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 29648c6f328SShengzhou Liu FTIM0_NOR_TEADC(0x5) | \ 29748c6f328SShengzhou Liu FTIM0_NOR_TEAHC(0x5)) 29848c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 29948c6f328SShengzhou Liu FTIM1_NOR_TRAD_NOR(0x1A) |\ 30048c6f328SShengzhou Liu FTIM1_NOR_TSEQRAD_NOR(0x13)) 30148c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 30248c6f328SShengzhou Liu FTIM2_NOR_TCH(0x4) | \ 30348c6f328SShengzhou Liu FTIM2_NOR_TWPH(0x0E) | \ 30448c6f328SShengzhou Liu FTIM2_NOR_TWP(0x1c)) 30548c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM3 0x0 30648c6f328SShengzhou Liu 30748c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_QUIET_TEST 30848c6f328SShengzhou Liu #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 30948c6f328SShengzhou Liu 31048c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 31148c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 31248c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 31348c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 31448c6f328SShengzhou Liu 31548c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_EMPTY_INFO 31648c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 31748c6f328SShengzhou Liu 31848c6f328SShengzhou Liu /* CPLD on IFC */ 31948c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE 0xffdf0000 32048c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 32148c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2_EXT (0xf) 32248c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 32348c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 \ 32448c6f328SShengzhou Liu | CSPR_MSEL_GPCM \ 32548c6f328SShengzhou Liu | CSPR_V) 32648c6f328SShengzhou Liu #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 32748c6f328SShengzhou Liu #define CONFIG_SYS_CSOR2 0x0 32848c6f328SShengzhou Liu 32948c6f328SShengzhou Liu /* CPLD Timing parameters for IFC CS2 */ 33048c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 33148c6f328SShengzhou Liu FTIM0_GPCM_TEADC(0x0e) | \ 33248c6f328SShengzhou Liu FTIM0_GPCM_TEAHC(0x0e)) 33348c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 33448c6f328SShengzhou Liu FTIM1_GPCM_TRAD(0x1f)) 33548c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 33648c6f328SShengzhou Liu FTIM2_GPCM_TCH(0x8) | \ 33748c6f328SShengzhou Liu FTIM2_GPCM_TWP(0x1f)) 33848c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM3 0x0 33948c6f328SShengzhou Liu 34048c6f328SShengzhou Liu /* NAND Flash on IFC */ 34148c6f328SShengzhou Liu #define CONFIG_NAND_FSL_IFC 34248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE 0xff800000 34348c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 34448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 34548c6f328SShengzhou Liu #else 34648c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 34748c6f328SShengzhou Liu #endif 34848c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 34948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 35048c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 35148c6f328SShengzhou Liu | CSPR_MSEL_NAND /* MSEL = NAND */ \ 35248c6f328SShengzhou Liu | CSPR_V) 35348c6f328SShengzhou Liu #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 35448c6f328SShengzhou Liu 35548c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 35648c6f328SShengzhou Liu | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 35748c6f328SShengzhou Liu | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 35848c6f328SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 35948c6f328SShengzhou Liu | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 36048c6f328SShengzhou Liu | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 36148c6f328SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 36248c6f328SShengzhou Liu 36348c6f328SShengzhou Liu #define CONFIG_SYS_NAND_ONFI_DETECTION 36448c6f328SShengzhou Liu 36548c6f328SShengzhou Liu /* ONFI NAND Flash mode0 Timing Params */ 36648c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 36748c6f328SShengzhou Liu FTIM0_NAND_TWP(0x18) | \ 36848c6f328SShengzhou Liu FTIM0_NAND_TWCHT(0x07) | \ 36948c6f328SShengzhou Liu FTIM0_NAND_TWH(0x0a)) 37048c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 37148c6f328SShengzhou Liu FTIM1_NAND_TWBE(0x39) | \ 37248c6f328SShengzhou Liu FTIM1_NAND_TRR(0x0e) | \ 37348c6f328SShengzhou Liu FTIM1_NAND_TRP(0x18)) 37448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 37548c6f328SShengzhou Liu FTIM2_NAND_TREH(0x0a) | \ 37648c6f328SShengzhou Liu FTIM2_NAND_TWHRE(0x1e)) 37748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM3 0x0 37848c6f328SShengzhou Liu 37948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_DDR_LAW 11 38048c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 38148c6f328SShengzhou Liu #define CONFIG_SYS_MAX_NAND_DEVICE 1 38248c6f328SShengzhou Liu #define CONFIG_MTD_NAND_VERIFY_WRITE 38348c6f328SShengzhou Liu #define CONFIG_CMD_NAND 38448c6f328SShengzhou Liu 38548c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 38648c6f328SShengzhou Liu 38748c6f328SShengzhou Liu #if defined(CONFIG_NAND) 38848c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 38948c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 39048c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 39148c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 39248c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 39348c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 39448c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 39548c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 39648c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 39748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 39848c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 39948c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 40048c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 40148c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 40248c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 40348c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 40448c6f328SShengzhou Liu #else 40548c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 40648c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 40748c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 40848c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 40948c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 41048c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 41148c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 41248c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 41348c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 41448c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 41548c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 41648c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 41748c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 41848c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 41948c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 42048c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 42148c6f328SShengzhou Liu #endif 42248c6f328SShengzhou Liu 42348c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 42448c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 42548c6f328SShengzhou Liu #else 42648c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 42748c6f328SShengzhou Liu #endif 42848c6f328SShengzhou Liu 42948c6f328SShengzhou Liu #if defined(CONFIG_RAMBOOT_PBL) 43048c6f328SShengzhou Liu #define CONFIG_SYS_RAMBOOT 43148c6f328SShengzhou Liu #endif 43248c6f328SShengzhou Liu 43348c6f328SShengzhou Liu #define CONFIG_BOARD_EARLY_INIT_R 43448c6f328SShengzhou Liu #define CONFIG_MISC_INIT_R 43548c6f328SShengzhou Liu 43648c6f328SShengzhou Liu #define CONFIG_HWCONFIG 43748c6f328SShengzhou Liu 43848c6f328SShengzhou Liu /* define to use L1 as initial stack */ 43948c6f328SShengzhou Liu #define CONFIG_L1_INIT_RAM 44048c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_LOCK 44148c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 44248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 44348c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 44448c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 44548c6f328SShengzhou Liu /* The assembler doesn't like typecast */ 44648c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 44748c6f328SShengzhou Liu ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 44848c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 44948c6f328SShengzhou Liu #else 45048c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 45148c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 45248c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 45348c6f328SShengzhou Liu #endif 45448c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 45548c6f328SShengzhou Liu 45648c6f328SShengzhou Liu #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 45748c6f328SShengzhou Liu GENERATED_GBL_DATA_SIZE) 45848c6f328SShengzhou Liu #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 45948c6f328SShengzhou Liu 46048c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 46148c6f328SShengzhou Liu #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 46248c6f328SShengzhou Liu 46348c6f328SShengzhou Liu /* Serial Port */ 46448c6f328SShengzhou Liu #define CONFIG_CONS_INDEX 1 46548c6f328SShengzhou Liu #define CONFIG_SYS_NS16550 46648c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_SERIAL 46748c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_REG_SIZE 1 46848c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 46948c6f328SShengzhou Liu 47048c6f328SShengzhou Liu #define CONFIG_SYS_BAUDRATE_TABLE \ 47148c6f328SShengzhou Liu {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 47248c6f328SShengzhou Liu 47348c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 47448c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 47548c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 47648c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 47748c6f328SShengzhou Liu #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 47848c6f328SShengzhou Liu 47948c6f328SShengzhou Liu /* Use the HUSH parser */ 48048c6f328SShengzhou Liu #define CONFIG_SYS_HUSH_PARSER 48148c6f328SShengzhou Liu #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 48248c6f328SShengzhou Liu 48348c6f328SShengzhou Liu /* Video */ 48448c6f328SShengzhou Liu #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 48548c6f328SShengzhou Liu #ifdef CONFIG_FSL_DIU_FB 48648c6f328SShengzhou Liu #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 48748c6f328SShengzhou Liu #define CONFIG_VIDEO 48848c6f328SShengzhou Liu #define CONFIG_CMD_BMP 48948c6f328SShengzhou Liu #define CONFIG_CFB_CONSOLE 49048c6f328SShengzhou Liu #define CONFIG_VIDEO_SW_CURSOR 49148c6f328SShengzhou Liu #define CONFIG_VGA_AS_SINGLE_DEVICE 49248c6f328SShengzhou Liu #define CONFIG_VIDEO_LOGO 49348c6f328SShengzhou Liu #define CONFIG_VIDEO_BMP_LOGO 49448c6f328SShengzhou Liu #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 49548c6f328SShengzhou Liu /* 49648c6f328SShengzhou Liu * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 49748c6f328SShengzhou Liu * disable empty flash sector detection, which is I/O-intensive. 49848c6f328SShengzhou Liu */ 49948c6f328SShengzhou Liu #undef CONFIG_SYS_FLASH_EMPTY_INFO 50048c6f328SShengzhou Liu #endif 50148c6f328SShengzhou Liu 50248c6f328SShengzhou Liu /* pass open firmware flat tree */ 50348c6f328SShengzhou Liu #define CONFIG_OF_LIBFDT 50448c6f328SShengzhou Liu #define CONFIG_OF_BOARD_SETUP 50548c6f328SShengzhou Liu #define CONFIG_OF_STDOUT_VIA_ALIAS 50648c6f328SShengzhou Liu 50748c6f328SShengzhou Liu /* new uImage format support */ 50848c6f328SShengzhou Liu #define CONFIG_FIT 50948c6f328SShengzhou Liu #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 51048c6f328SShengzhou Liu 51148c6f328SShengzhou Liu /* I2C */ 51248c6f328SShengzhou Liu #define CONFIG_SYS_I2C 51348c6f328SShengzhou Liu #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 51448c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 51548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 51648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 51748c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 51848c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 51948c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 52048c6f328SShengzhou Liu 52148c6f328SShengzhou Liu #define I2C_MUX_PCA_ADDR 0x77 52248c6f328SShengzhou Liu #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 52348c6f328SShengzhou Liu 52448c6f328SShengzhou Liu 52548c6f328SShengzhou Liu /* I2C bus multiplexer */ 52648c6f328SShengzhou Liu #define I2C_MUX_CH_DEFAULT 0x8 52748c6f328SShengzhou Liu 52848c6f328SShengzhou Liu /* 52948c6f328SShengzhou Liu * RTC configuration 53048c6f328SShengzhou Liu */ 53148c6f328SShengzhou Liu #define RTC 53248c6f328SShengzhou Liu #define CONFIG_RTC_DS1337 1 53348c6f328SShengzhou Liu #define CONFIG_SYS_I2C_RTC_ADDR 0x68 53448c6f328SShengzhou Liu 53548c6f328SShengzhou Liu /* 53648c6f328SShengzhou Liu * eSPI - Enhanced SPI 53748c6f328SShengzhou Liu */ 53848c6f328SShengzhou Liu #define CONFIG_FSL_ESPI 53948c6f328SShengzhou Liu #define CONFIG_SPI_FLASH 54048c6f328SShengzhou Liu #define CONFIG_SPI_FLASH_STMICRO 54148c6f328SShengzhou Liu #define CONFIG_CMD_SF 54248c6f328SShengzhou Liu #define CONFIG_SPI_FLASH_BAR 54348c6f328SShengzhou Liu #define CONFIG_SF_DEFAULT_SPEED 10000000 54448c6f328SShengzhou Liu #define CONFIG_SF_DEFAULT_MODE 0 54548c6f328SShengzhou Liu 54648c6f328SShengzhou Liu /* 54748c6f328SShengzhou Liu * General PCIe 54848c6f328SShengzhou Liu * Memory space is mapped 1-1, but I/O space must start from 0. 54948c6f328SShengzhou Liu */ 55048c6f328SShengzhou Liu #define CONFIG_PCI /* Enable PCI/PCIE */ 55148c6f328SShengzhou Liu #define CONFIG_PCIE1 /* PCIE controler 1 */ 55248c6f328SShengzhou Liu #define CONFIG_PCIE2 /* PCIE controler 2 */ 55348c6f328SShengzhou Liu #define CONFIG_PCIE3 /* PCIE controler 3 */ 55448c6f328SShengzhou Liu #ifdef CONFIG_PPC_T1040 55548c6f328SShengzhou Liu #define CONFIG_PCIE4 /* PCIE controler 4 */ 55648c6f328SShengzhou Liu #endif 55748c6f328SShengzhou Liu #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 55848c6f328SShengzhou Liu #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 55948c6f328SShengzhou Liu #define CONFIG_PCI_INDIRECT_BRIDGE 56048c6f328SShengzhou Liu 56148c6f328SShengzhou Liu #ifdef CONFIG_PCI 56248c6f328SShengzhou Liu /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 56348c6f328SShengzhou Liu #ifdef CONFIG_PCIE1 56448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 56548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 56648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 56748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 56848c6f328SShengzhou Liu #else 56948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 57048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 57148c6f328SShengzhou Liu #endif 57248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 57348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 57448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 57548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 57648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 57748c6f328SShengzhou Liu #else 57848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 57948c6f328SShengzhou Liu #endif 58048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 58148c6f328SShengzhou Liu #endif 58248c6f328SShengzhou Liu 58348c6f328SShengzhou Liu /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 58448c6f328SShengzhou Liu #ifdef CONFIG_PCIE2 58548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 58648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 58748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 58848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 58948c6f328SShengzhou Liu #else 59048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 59148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 59248c6f328SShengzhou Liu #endif 59348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 59448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 59548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 59648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 59748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 59848c6f328SShengzhou Liu #else 59948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 60048c6f328SShengzhou Liu #endif 60148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 60248c6f328SShengzhou Liu #endif 60348c6f328SShengzhou Liu 60448c6f328SShengzhou Liu /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 60548c6f328SShengzhou Liu #ifdef CONFIG_PCIE3 60648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 60748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 60848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 60948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 61048c6f328SShengzhou Liu #else 61148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 61248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 61348c6f328SShengzhou Liu #endif 61448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 61548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 61648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 61748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 61848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 61948c6f328SShengzhou Liu #else 62048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 62148c6f328SShengzhou Liu #endif 62248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 62348c6f328SShengzhou Liu #endif 62448c6f328SShengzhou Liu 62548c6f328SShengzhou Liu /* controller 4, Base address 203000, to be removed */ 62648c6f328SShengzhou Liu #ifdef CONFIG_PCIE4 62748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 62848c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 62948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 63048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 63148c6f328SShengzhou Liu #else 63248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 63348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 63448c6f328SShengzhou Liu #endif 63548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 63648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 63748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 63848c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 63948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 64048c6f328SShengzhou Liu #else 64148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 64248c6f328SShengzhou Liu #endif 64348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 64448c6f328SShengzhou Liu #endif 64548c6f328SShengzhou Liu 64648c6f328SShengzhou Liu #define CONFIG_PCI_PNP /* do pci plug-and-play */ 64748c6f328SShengzhou Liu #define CONFIG_E1000 64848c6f328SShengzhou Liu #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 64948c6f328SShengzhou Liu #define CONFIG_DOS_PARTITION 65048c6f328SShengzhou Liu #endif /* CONFIG_PCI */ 65148c6f328SShengzhou Liu 65248c6f328SShengzhou Liu /* 65348c6f328SShengzhou Liu * USB 65448c6f328SShengzhou Liu */ 65548c6f328SShengzhou Liu #define CONFIG_HAS_FSL_DR_USB 65648c6f328SShengzhou Liu 65748c6f328SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 65848c6f328SShengzhou Liu #define CONFIG_USB_EHCI 65948c6f328SShengzhou Liu #define CONFIG_CMD_USB 66048c6f328SShengzhou Liu #define CONFIG_USB_STORAGE 66148c6f328SShengzhou Liu #define CONFIG_USB_EHCI_FSL 66248c6f328SShengzhou Liu #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 66348c6f328SShengzhou Liu #define CONFIG_CMD_EXT2 66448c6f328SShengzhou Liu #endif 66548c6f328SShengzhou Liu 66648c6f328SShengzhou Liu /* 66748c6f328SShengzhou Liu * SDHC 66848c6f328SShengzhou Liu */ 66948c6f328SShengzhou Liu #define CONFIG_MMC 67048c6f328SShengzhou Liu #ifdef CONFIG_MMC 67148c6f328SShengzhou Liu #define CONFIG_FSL_ESDHC 67248c6f328SShengzhou Liu #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 67348c6f328SShengzhou Liu #define CONFIG_CMD_MMC 67448c6f328SShengzhou Liu #define CONFIG_GENERIC_MMC 67548c6f328SShengzhou Liu #define CONFIG_CMD_EXT2 67648c6f328SShengzhou Liu #define CONFIG_CMD_FAT 67748c6f328SShengzhou Liu #define CONFIG_DOS_PARTITION 67848c6f328SShengzhou Liu #endif 67948c6f328SShengzhou Liu 68048c6f328SShengzhou Liu /* Qman/Bman */ 68148c6f328SShengzhou Liu #ifndef CONFIG_NOBQFMAN 68248c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 6832a8b3422SJeffrey Ladouceur #define CONFIG_SYS_BMAN_NUM_PORTALS 10 68448c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 68548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 68648c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 68748c6f328SShengzhou Liu #else 68848c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 68948c6f328SShengzhou Liu #endif 69048c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 6913fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 6923fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 6933fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 6943fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 6953fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 6963fa66db4SJeffrey Ladouceur CONFIG_SYS_BMAN_CENA_SIZE) 6973fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 6983fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 6992a8b3422SJeffrey Ladouceur #define CONFIG_SYS_QMAN_NUM_PORTALS 10 70048c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 70148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 70248c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 70348c6f328SShengzhou Liu #else 70448c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 70548c6f328SShengzhou Liu #endif 70648c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 7073fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 7083fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 7093fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 7103fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 7113fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 7123fa66db4SJeffrey Ladouceur CONFIG_SYS_QMAN_CENA_SIZE) 7133fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 7143fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 71548c6f328SShengzhou Liu 71648c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_FMAN 71748c6f328SShengzhou Liu 71848c6f328SShengzhou Liu #define CONFIG_QE 71948c6f328SShengzhou Liu #define CONFIG_U_QE 72048c6f328SShengzhou Liu /* Default address of microcode for the Linux FMan driver */ 72148c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 72248c6f328SShengzhou Liu /* 72348c6f328SShengzhou Liu * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 72448c6f328SShengzhou Liu * env, so we got 0x110000. 72548c6f328SShengzhou Liu */ 72648c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_IN_SPIFLASH 72748c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 72848c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0x130000 72948c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 73048c6f328SShengzhou Liu /* 73148c6f328SShengzhou Liu * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 73248c6f328SShengzhou Liu * about 1MB (2048 blocks), Env is stored after the image, and the env size is 73348c6f328SShengzhou Liu * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 73448c6f328SShengzhou Liu */ 73548c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 73648c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 73748c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 73848c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 73948c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 74048c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 74148c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 74248c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 74348c6f328SShengzhou Liu /* 74448c6f328SShengzhou Liu * Slave has no ucode locally, it can fetch this from remote. When implementing 74548c6f328SShengzhou Liu * in two corenet boards, slave's ucode could be stored in master's memory 74648c6f328SShengzhou Liu * space, the address can be mapped from slave TLB->slave LAW-> 74748c6f328SShengzhou Liu * slave SRIO or PCIE outbound window->master inbound window-> 74848c6f328SShengzhou Liu * master LAW->the ucode address in master's memory space. 74948c6f328SShengzhou Liu */ 75048c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 75148c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 75248c6f328SShengzhou Liu #else 75348c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 75448c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 75548c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 75648c6f328SShengzhou Liu #endif 75748c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 75848c6f328SShengzhou Liu #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 75948c6f328SShengzhou Liu #endif /* CONFIG_NOBQFMAN */ 76048c6f328SShengzhou Liu 76148c6f328SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 76248c6f328SShengzhou Liu #define CONFIG_FMAN_ENET 76348c6f328SShengzhou Liu #define CONFIG_PHYLIB_10G 76448c6f328SShengzhou Liu #define CONFIG_PHY_REALTEK 76548c6f328SShengzhou Liu #define RGMII_PHY1_ADDR 0x2 76648c6f328SShengzhou Liu #define RGMII_PHY2_ADDR 0x6 76748c6f328SShengzhou Liu #define FM1_10GEC1_PHY_ADDR 0x1 76848c6f328SShengzhou Liu #endif 76948c6f328SShengzhou Liu 77048c6f328SShengzhou Liu #ifdef CONFIG_FMAN_ENET 77148c6f328SShengzhou Liu #define CONFIG_MII /* MII PHY management */ 77248c6f328SShengzhou Liu #define CONFIG_ETHPRIME "FM1@DTSEC4" 77348c6f328SShengzhou Liu #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 77448c6f328SShengzhou Liu #endif 77548c6f328SShengzhou Liu 77648c6f328SShengzhou Liu /* 77748c6f328SShengzhou Liu * Dynamic MTD Partition support with mtdparts 77848c6f328SShengzhou Liu */ 77948c6f328SShengzhou Liu #ifndef CONFIG_SYS_NO_FLASH 78048c6f328SShengzhou Liu #define CONFIG_MTD_DEVICE 78148c6f328SShengzhou Liu #define CONFIG_MTD_PARTITIONS 78248c6f328SShengzhou Liu #define CONFIG_CMD_MTDPARTS 78348c6f328SShengzhou Liu #define CONFIG_FLASH_CFI_MTD 78448c6f328SShengzhou Liu #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 78548c6f328SShengzhou Liu "spi0=spife110000.1" 78648c6f328SShengzhou Liu #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 78748c6f328SShengzhou Liu "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 78848c6f328SShengzhou Liu "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 78948c6f328SShengzhou Liu "1m(uboot),5m(kernel),128k(dtb),-(user)" 79048c6f328SShengzhou Liu #endif 79148c6f328SShengzhou Liu 79248c6f328SShengzhou Liu /* 79348c6f328SShengzhou Liu * Environment 79448c6f328SShengzhou Liu */ 79548c6f328SShengzhou Liu #define CONFIG_LOADS_ECHO /* echo on for serial download */ 79648c6f328SShengzhou Liu #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 79748c6f328SShengzhou Liu 79848c6f328SShengzhou Liu /* 79948c6f328SShengzhou Liu * Command line configuration. 80048c6f328SShengzhou Liu */ 80148c6f328SShengzhou Liu #include <config_cmd_default.h> 80248c6f328SShengzhou Liu 80348c6f328SShengzhou Liu #define CONFIG_CMD_DATE 80448c6f328SShengzhou Liu #define CONFIG_CMD_DHCP 80548c6f328SShengzhou Liu #define CONFIG_CMD_EEPROM 80648c6f328SShengzhou Liu #define CONFIG_CMD_ELF 80748c6f328SShengzhou Liu #define CONFIG_CMD_ERRATA 80848c6f328SShengzhou Liu #define CONFIG_CMD_GREPENV 80948c6f328SShengzhou Liu #define CONFIG_CMD_IRQ 81048c6f328SShengzhou Liu #define CONFIG_CMD_I2C 81148c6f328SShengzhou Liu #define CONFIG_CMD_MII 81248c6f328SShengzhou Liu #define CONFIG_CMD_PING 81348c6f328SShengzhou Liu #define CONFIG_CMD_ECHO 81448c6f328SShengzhou Liu #define CONFIG_CMD_REGINFO 81548c6f328SShengzhou Liu #define CONFIG_CMD_SETEXPR 81648c6f328SShengzhou Liu #define CONFIG_CMD_BDI 81748c6f328SShengzhou Liu 81848c6f328SShengzhou Liu #ifdef CONFIG_PCI 81948c6f328SShengzhou Liu #define CONFIG_CMD_PCI 82048c6f328SShengzhou Liu #define CONFIG_CMD_NET 82148c6f328SShengzhou Liu #endif 82248c6f328SShengzhou Liu 82348c6f328SShengzhou Liu /* 82448c6f328SShengzhou Liu * Miscellaneous configurable options 82548c6f328SShengzhou Liu */ 82648c6f328SShengzhou Liu #define CONFIG_SYS_LONGHELP /* undef to save memory */ 82748c6f328SShengzhou Liu #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 82848c6f328SShengzhou Liu #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 82948c6f328SShengzhou Liu #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 83048c6f328SShengzhou Liu #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 83148c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 83248c6f328SShengzhou Liu #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 83348c6f328SShengzhou Liu #else 83448c6f328SShengzhou Liu #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 83548c6f328SShengzhou Liu #endif 83648c6f328SShengzhou Liu #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 83748c6f328SShengzhou Liu #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 83848c6f328SShengzhou Liu #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 83948c6f328SShengzhou Liu 84048c6f328SShengzhou Liu /* 84148c6f328SShengzhou Liu * For booting Linux, the board info and command line data 84248c6f328SShengzhou Liu * have to be in the first 64 MB of memory, since this is 84348c6f328SShengzhou Liu * the maximum mapped by the Linux kernel during initialization. 84448c6f328SShengzhou Liu */ 84548c6f328SShengzhou Liu #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 84648c6f328SShengzhou Liu #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 84748c6f328SShengzhou Liu 84848c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 84948c6f328SShengzhou Liu #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 85048c6f328SShengzhou Liu #endif 85148c6f328SShengzhou Liu 85248c6f328SShengzhou Liu /* 85348c6f328SShengzhou Liu * Environment Configuration 85448c6f328SShengzhou Liu */ 85548c6f328SShengzhou Liu #define CONFIG_ROOTPATH "/opt/nfsroot" 85648c6f328SShengzhou Liu #define CONFIG_BOOTFILE "uImage" 85748c6f328SShengzhou Liu #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 85848c6f328SShengzhou Liu #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 85948c6f328SShengzhou Liu #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 86048c6f328SShengzhou Liu #define CONFIG_BAUDRATE 115200 86148c6f328SShengzhou Liu #define __USB_PHY_TYPE utmi 86248c6f328SShengzhou Liu 86348c6f328SShengzhou Liu #ifdef CONFIG_PPC_T1024 86448c6f328SShengzhou Liu #define CONFIG_BOARDNAME "t1024rdb" 86548c6f328SShengzhou Liu #else 86648c6f328SShengzhou Liu #define CONFIG_BOARDNAME "t1023rdb" 86748c6f328SShengzhou Liu #endif 86848c6f328SShengzhou Liu 86948c6f328SShengzhou Liu #define CONFIG_EXTRA_ENV_SETTINGS \ 87048c6f328SShengzhou Liu "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 87148c6f328SShengzhou Liu "bank_intlv=cs0_cs1\0" \ 87248c6f328SShengzhou Liu "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 87348c6f328SShengzhou Liu "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 87448c6f328SShengzhou Liu "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 87548c6f328SShengzhou Liu __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 87648c6f328SShengzhou Liu "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 87748c6f328SShengzhou Liu "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 87848c6f328SShengzhou Liu "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 87948c6f328SShengzhou Liu "netdev=eth0\0" \ 88048c6f328SShengzhou Liu "tftpflash=tftpboot $loadaddr $uboot && " \ 88148c6f328SShengzhou Liu "protect off $ubootaddr +$filesize && " \ 88248c6f328SShengzhou Liu "erase $ubootaddr +$filesize && " \ 88348c6f328SShengzhou Liu "cp.b $loadaddr $ubootaddr $filesize && " \ 88448c6f328SShengzhou Liu "protect on $ubootaddr +$filesize && " \ 88548c6f328SShengzhou Liu "cmp.b $loadaddr $ubootaddr $filesize\0" \ 88648c6f328SShengzhou Liu "consoledev=ttyS0\0" \ 88748c6f328SShengzhou Liu "ramdiskaddr=2000000\0" \ 88848c6f328SShengzhou Liu "fdtaddr=c00000\0" \ 88948c6f328SShengzhou Liu "bdev=sda3\0" 89048c6f328SShengzhou Liu 89148c6f328SShengzhou Liu #define CONFIG_LINUX \ 89248c6f328SShengzhou Liu "setenv bootargs root=/dev/ram rw " \ 89348c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 89448c6f328SShengzhou Liu "setenv ramdiskaddr 0x02000000;" \ 89548c6f328SShengzhou Liu "setenv fdtaddr 0x00c00000;" \ 89648c6f328SShengzhou Liu "setenv loadaddr 0x1000000;" \ 89748c6f328SShengzhou Liu "bootm $loadaddr $ramdiskaddr $fdtaddr" 89848c6f328SShengzhou Liu 89948c6f328SShengzhou Liu 90048c6f328SShengzhou Liu #define CONFIG_NFSBOOTCOMMAND \ 90148c6f328SShengzhou Liu "setenv bootargs root=/dev/nfs rw " \ 90248c6f328SShengzhou Liu "nfsroot=$serverip:$rootpath " \ 90348c6f328SShengzhou Liu "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 90448c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 90548c6f328SShengzhou Liu "tftp $loadaddr $bootfile;" \ 90648c6f328SShengzhou Liu "tftp $fdtaddr $fdtfile;" \ 90748c6f328SShengzhou Liu "bootm $loadaddr - $fdtaddr" 90848c6f328SShengzhou Liu 90948c6f328SShengzhou Liu #define CONFIG_BOOTCOMMAND CONFIG_LINUX 91048c6f328SShengzhou Liu 91148c6f328SShengzhou Liu #ifdef CONFIG_SECURE_BOOT 91248c6f328SShengzhou Liu #include <asm/fsl_secure_boot.h> 91348c6f328SShengzhou Liu #endif 91448c6f328SShengzhou Liu 91548c6f328SShengzhou Liu #endif /* __T1024RDB_H */ 916