148c6f328SShengzhou Liu /* 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 348c6f328SShengzhou Liu * 448c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 548c6f328SShengzhou Liu */ 648c6f328SShengzhou Liu 748c6f328SShengzhou Liu /* 848c6f328SShengzhou Liu * T1024/T1023 RDB board configuration file 948c6f328SShengzhou Liu */ 1048c6f328SShengzhou Liu 1148c6f328SShengzhou Liu #ifndef __T1024RDB_H 1248c6f328SShengzhou Liu #define __T1024RDB_H 1348c6f328SShengzhou Liu 1448c6f328SShengzhou Liu /* High Level Configuration Options */ 1548c6f328SShengzhou Liu #define CONFIG_DISPLAY_BOARDINFO 1648c6f328SShengzhou Liu #define CONFIG_BOOKE 1748c6f328SShengzhou Liu #define CONFIG_E500 /* BOOKE e500 family */ 1848c6f328SShengzhou Liu #define CONFIG_E500MC /* BOOKE e500mc family */ 1948c6f328SShengzhou Liu #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 2048c6f328SShengzhou Liu #define CONFIG_MP /* support multiple processors */ 2148c6f328SShengzhou Liu #define CONFIG_PHYS_64BIT 2248c6f328SShengzhou Liu #define CONFIG_ENABLE_36BIT_PHYS 2348c6f328SShengzhou Liu 2448c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 2548c6f328SShengzhou Liu #define CONFIG_ADDR_MAP 1 2648c6f328SShengzhou Liu #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 2748c6f328SShengzhou Liu #endif 2848c6f328SShengzhou Liu 2948c6f328SShengzhou Liu #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 3048c6f328SShengzhou Liu #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 3148c6f328SShengzhou Liu #define CONFIG_FSL_IFC /* Enable IFC Support */ 3248c6f328SShengzhou Liu 3348c6f328SShengzhou Liu #define CONFIG_FSL_LAW /* Use common FSL init code */ 3448c6f328SShengzhou Liu #define CONFIG_ENV_OVERWRITE 3548c6f328SShengzhou Liu 36ef6c55a2SAneesh Bansal #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37ef6c55a2SAneesh Bansal 3848c6f328SShengzhou Liu /* support deep sleep */ 39e8a7f1c3SShengzhou Liu #ifdef CONFIG_PPC_T1024 4048c6f328SShengzhou Liu #define CONFIG_DEEP_SLEEP 41e8a7f1c3SShengzhou Liu #endif 42f49b8c1bStang yuantian #if defined(CONFIG_DEEP_SLEEP) 4348c6f328SShengzhou Liu #define CONFIG_SILENT_CONSOLE 44f49b8c1bStang yuantian #define CONFIG_BOARD_EARLY_INIT_F 45f49b8c1bStang yuantian #endif 4648c6f328SShengzhou Liu 4748c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 4848c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 49e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 5048c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 51e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 52e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 53e8a7f1c3SShengzhou Liu #endif 5448c6f328SShengzhou Liu #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 5548c6f328SShengzhou Liu #define CONFIG_SPL_ENV_SUPPORT 5648c6f328SShengzhou Liu #define CONFIG_SPL_SERIAL_SUPPORT 5748c6f328SShengzhou Liu #define CONFIG_SPL_FLUSH_IMAGE 5848c6f328SShengzhou Liu #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 5948c6f328SShengzhou Liu #define CONFIG_SPL_LIBGENERIC_SUPPORT 6048c6f328SShengzhou Liu #define CONFIG_SPL_LIBCOMMON_SUPPORT 6148c6f328SShengzhou Liu #define CONFIG_SPL_I2C_SUPPORT 6248c6f328SShengzhou Liu #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 6348c6f328SShengzhou Liu #define CONFIG_FSL_LAW /* Use common FSL init code */ 64f49b8c1bStang yuantian #define CONFIG_SYS_TEXT_BASE 0x30001000 6548c6f328SShengzhou Liu #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 6648c6f328SShengzhou Liu #define CONFIG_SPL_PAD_TO 0x40000 6748c6f328SShengzhou Liu #define CONFIG_SPL_MAX_SIZE 0x28000 6848c6f328SShengzhou Liu #define RESET_VECTOR_OFFSET 0x27FFC 6948c6f328SShengzhou Liu #define BOOT_PAGE_OFFSET 0x27000 7048c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 7148c6f328SShengzhou Liu #define CONFIG_SPL_SKIP_RELOCATE 7248c6f328SShengzhou Liu #define CONFIG_SPL_COMMON_INIT_DDR 7348c6f328SShengzhou Liu #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 7448c6f328SShengzhou Liu #define CONFIG_SYS_NO_FLASH 7548c6f328SShengzhou Liu #endif 7648c6f328SShengzhou Liu 7748c6f328SShengzhou Liu #ifdef CONFIG_NAND 7848c6f328SShengzhou Liu #define CONFIG_SPL_NAND_SUPPORT 7948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 80f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 81f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 8248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 8348c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 8448c6f328SShengzhou Liu #define CONFIG_SPL_NAND_BOOT 8548c6f328SShengzhou Liu #endif 8648c6f328SShengzhou Liu 8748c6f328SShengzhou Liu #ifdef CONFIG_SPIFLASH 88f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 8948c6f328SShengzhou Liu #define CONFIG_SPL_SPI_SUPPORT 9048c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_SUPPORT 9148c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_MINIMAL 9248c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 93f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 94f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 9548c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 9648c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 9748c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 9848c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 9948c6f328SShengzhou Liu #endif 10048c6f328SShengzhou Liu #define CONFIG_SPL_SPI_BOOT 10148c6f328SShengzhou Liu #endif 10248c6f328SShengzhou Liu 10348c6f328SShengzhou Liu #ifdef CONFIG_SDCARD 104f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 10548c6f328SShengzhou Liu #define CONFIG_SPL_MMC_SUPPORT 10648c6f328SShengzhou Liu #define CONFIG_SPL_MMC_MINIMAL 10748c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 108f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 109f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 11048c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 11148c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 11248c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 11348c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 11448c6f328SShengzhou Liu #endif 11548c6f328SShengzhou Liu #define CONFIG_SPL_MMC_BOOT 11648c6f328SShengzhou Liu #endif 11748c6f328SShengzhou Liu 11848c6f328SShengzhou Liu #endif /* CONFIG_RAMBOOT_PBL */ 11948c6f328SShengzhou Liu 12048c6f328SShengzhou Liu #ifndef CONFIG_SYS_TEXT_BASE 12148c6f328SShengzhou Liu #define CONFIG_SYS_TEXT_BASE 0xeff40000 12248c6f328SShengzhou Liu #endif 12348c6f328SShengzhou Liu 12448c6f328SShengzhou Liu #ifndef CONFIG_RESET_VECTOR_ADDRESS 12548c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 12648c6f328SShengzhou Liu #endif 12748c6f328SShengzhou Liu 12848c6f328SShengzhou Liu #ifndef CONFIG_SYS_NO_FLASH 12948c6f328SShengzhou Liu #define CONFIG_FLASH_CFI_DRIVER 13048c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_CFI 13148c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 13248c6f328SShengzhou Liu #endif 13348c6f328SShengzhou Liu 13448c6f328SShengzhou Liu /* PCIe Boot - Master */ 13548c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_MASTER 13648c6f328SShengzhou Liu /* 13748c6f328SShengzhou Liu * for slave u-boot IMAGE instored in master memory space, 13848c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 13948c6f328SShengzhou Liu */ 14048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 14148c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 14248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 14348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 14448c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 14548c6f328SShengzhou Liu #else 14648c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 14748c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 14848c6f328SShengzhou Liu #endif 14948c6f328SShengzhou Liu /* 15048c6f328SShengzhou Liu * for slave UCODE and ENV instored in master memory space, 15148c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 15248c6f328SShengzhou Liu */ 15348c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 15448c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 15548c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 15648c6f328SShengzhou Liu #else 15748c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 15848c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 15948c6f328SShengzhou Liu #endif 16048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 16148c6f328SShengzhou Liu /* slave core release by master*/ 16248c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 16348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 16448c6f328SShengzhou Liu 16548c6f328SShengzhou Liu /* PCIe Boot - Slave */ 16648c6f328SShengzhou Liu #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 16748c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 16848c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 16948c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 17048c6f328SShengzhou Liu /* Set 1M boot space for PCIe boot */ 17148c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 17248c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 17348c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 17448c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17548c6f328SShengzhou Liu #define CONFIG_SYS_NO_FLASH 17648c6f328SShengzhou Liu #endif 17748c6f328SShengzhou Liu 17848c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 17948c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 18048c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_SPI_FLASH 18148c6f328SShengzhou Liu #define CONFIG_ENV_SPI_BUS 0 18248c6f328SShengzhou Liu #define CONFIG_ENV_SPI_CS 0 18348c6f328SShengzhou Liu #define CONFIG_ENV_SPI_MAX_HZ 10000000 18448c6f328SShengzhou Liu #define CONFIG_ENV_SPI_MODE 0 18548c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 18648c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 187e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 18848c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x10000 189e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 190e8a7f1c3SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x40000 191e8a7f1c3SShengzhou Liu #endif 19248c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 19348c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 19448c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_MMC 19548c6f328SShengzhou Liu #define CONFIG_SYS_MMC_ENV_DEV 0 19648c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 19748c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (512 * 0x800) 19848c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 19948c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 20048c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_NAND 20148c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 202e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 20348c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 204e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 205e8a7f1c3SShengzhou Liu #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 206e8a7f1c3SShengzhou Liu #endif 20748c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 20848c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_REMOTE 20948c6f328SShengzhou Liu #define CONFIG_ENV_ADDR 0xffe20000 21048c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 21148c6f328SShengzhou Liu #elif defined(CONFIG_ENV_IS_NOWHERE) 21248c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 21348c6f328SShengzhou Liu #else 21448c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_FLASH 21548c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 21648c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 21748c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 21848c6f328SShengzhou Liu #endif 21948c6f328SShengzhou Liu 22048c6f328SShengzhou Liu #ifndef __ASSEMBLY__ 22148c6f328SShengzhou Liu unsigned long get_board_sys_clk(void); 22248c6f328SShengzhou Liu unsigned long get_board_ddr_clk(void); 22348c6f328SShengzhou Liu #endif 22448c6f328SShengzhou Liu 22548c6f328SShengzhou Liu #define CONFIG_SYS_CLK_FREQ 100000000 226e8a7f1c3SShengzhou Liu #define CONFIG_DDR_CLK_FREQ 100000000 22748c6f328SShengzhou Liu 22848c6f328SShengzhou Liu /* 22948c6f328SShengzhou Liu * These can be toggled for performance analysis, otherwise use default. 23048c6f328SShengzhou Liu */ 23148c6f328SShengzhou Liu #define CONFIG_SYS_CACHE_STASHING 23248c6f328SShengzhou Liu #define CONFIG_BACKSIDE_L2_CACHE 23348c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 23448c6f328SShengzhou Liu #define CONFIG_BTB /* toggle branch predition */ 23548c6f328SShengzhou Liu #define CONFIG_DDR_ECC 23648c6f328SShengzhou Liu #ifdef CONFIG_DDR_ECC 23748c6f328SShengzhou Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 23848c6f328SShengzhou Liu #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 23948c6f328SShengzhou Liu #endif 24048c6f328SShengzhou Liu 24148c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 24248c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_END 0x00400000 24348c6f328SShengzhou Liu #define CONFIG_SYS_ALT_MEMTEST 24448c6f328SShengzhou Liu #define CONFIG_PANIC_HANG /* do not reset board on panic */ 24548c6f328SShengzhou Liu 24648c6f328SShengzhou Liu /* 24748c6f328SShengzhou Liu * Config the L3 Cache as L3 SRAM 24848c6f328SShengzhou Liu */ 24948c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 25048c6f328SShengzhou Liu #define CONFIG_SYS_L3_SIZE (256 << 10) 25148c6f328SShengzhou Liu #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 25248c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 25348c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 25448c6f328SShengzhou Liu #endif 25548c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 25648c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 25748c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 25848c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 25948c6f328SShengzhou Liu 26048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 26148c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR 0xf0000000 26248c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 26348c6f328SShengzhou Liu #endif 26448c6f328SShengzhou Liu 26548c6f328SShengzhou Liu /* EEPROM */ 26648c6f328SShengzhou Liu #define CONFIG_ID_EEPROM 26748c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_NXID 26848c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_BUS_NUM 0 26948c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 27048c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 27148c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 27248c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 27348c6f328SShengzhou Liu 27448c6f328SShengzhou Liu /* 27548c6f328SShengzhou Liu * DDR Setup 27648c6f328SShengzhou Liu */ 27748c6f328SShengzhou Liu #define CONFIG_VERY_BIG_RAM 27848c6f328SShengzhou Liu #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 27948c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 28048c6f328SShengzhou Liu #define CONFIG_DIMM_SLOTS_PER_CTLR 1 28148c6f328SShengzhou Liu #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 282e8a7f1c3SShengzhou Liu #define CONFIG_FSL_DDR_INTERACTIVE 283e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 28448c6f328SShengzhou Liu #define CONFIG_DDR_SPD 28548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_DDR3 28648c6f328SShengzhou Liu #define CONFIG_SYS_SPD_BUS_NUM 0 28748c6f328SShengzhou Liu #define SPD_EEPROM_ADDRESS 0x51 28848c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 289e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 290e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FSL_DDR4 291e8a7f1c3SShengzhou Liu #define CONFIG_SYS_DDR_RAW_TIMING 292e8a7f1c3SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 2048 293e8a7f1c3SShengzhou Liu #endif 29448c6f328SShengzhou Liu 29548c6f328SShengzhou Liu /* 29648c6f328SShengzhou Liu * IFC Definitions 29748c6f328SShengzhou Liu */ 29848c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE 0xe8000000 29948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 30048c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 30148c6f328SShengzhou Liu #else 30248c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 30348c6f328SShengzhou Liu #endif 30448c6f328SShengzhou Liu 30548c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 30648c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 30748c6f328SShengzhou Liu CSPR_PORT_SIZE_16 | \ 30848c6f328SShengzhou Liu CSPR_MSEL_NOR | \ 30948c6f328SShengzhou Liu CSPR_V) 31048c6f328SShengzhou Liu #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 31148c6f328SShengzhou Liu 31248c6f328SShengzhou Liu /* NOR Flash Timing Params */ 313e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 31448c6f328SShengzhou Liu #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 315e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 316ff7ea2d1SShengzhou Liu #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 317e8a7f1c3SShengzhou Liu CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 318e8a7f1c3SShengzhou Liu #endif 31948c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 32048c6f328SShengzhou Liu FTIM0_NOR_TEADC(0x5) | \ 32148c6f328SShengzhou Liu FTIM0_NOR_TEAHC(0x5)) 32248c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 32348c6f328SShengzhou Liu FTIM1_NOR_TRAD_NOR(0x1A) |\ 32448c6f328SShengzhou Liu FTIM1_NOR_TSEQRAD_NOR(0x13)) 32548c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 32648c6f328SShengzhou Liu FTIM2_NOR_TCH(0x4) | \ 32748c6f328SShengzhou Liu FTIM2_NOR_TWPH(0x0E) | \ 32848c6f328SShengzhou Liu FTIM2_NOR_TWP(0x1c)) 32948c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM3 0x0 33048c6f328SShengzhou Liu 33148c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_QUIET_TEST 33248c6f328SShengzhou Liu #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 33348c6f328SShengzhou Liu 33448c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 33548c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 33648c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 33748c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 33848c6f328SShengzhou Liu 33948c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_EMPTY_INFO 34048c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 34148c6f328SShengzhou Liu 342e8a7f1c3SShengzhou Liu #ifdef CONFIG_T1024RDB 34348c6f328SShengzhou Liu /* CPLD on IFC */ 34448c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE 0xffdf0000 34548c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 34648c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2_EXT (0xf) 34748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 34848c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 \ 34948c6f328SShengzhou Liu | CSPR_MSEL_GPCM \ 35048c6f328SShengzhou Liu | CSPR_V) 35148c6f328SShengzhou Liu #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 35248c6f328SShengzhou Liu #define CONFIG_SYS_CSOR2 0x0 35348c6f328SShengzhou Liu 35448c6f328SShengzhou Liu /* CPLD Timing parameters for IFC CS2 */ 35548c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 35648c6f328SShengzhou Liu FTIM0_GPCM_TEADC(0x0e) | \ 35748c6f328SShengzhou Liu FTIM0_GPCM_TEAHC(0x0e)) 35848c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 35948c6f328SShengzhou Liu FTIM1_GPCM_TRAD(0x1f)) 36048c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 36148c6f328SShengzhou Liu FTIM2_GPCM_TCH(0x8) | \ 36248c6f328SShengzhou Liu FTIM2_GPCM_TWP(0x1f)) 36348c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM3 0x0 364e8a7f1c3SShengzhou Liu #endif 36548c6f328SShengzhou Liu 36648c6f328SShengzhou Liu /* NAND Flash on IFC */ 36748c6f328SShengzhou Liu #define CONFIG_NAND_FSL_IFC 36848c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE 0xff800000 36948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 37048c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 37148c6f328SShengzhou Liu #else 37248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 37348c6f328SShengzhou Liu #endif 37448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 37548c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 37648c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 37748c6f328SShengzhou Liu | CSPR_MSEL_NAND /* MSEL = NAND */ \ 37848c6f328SShengzhou Liu | CSPR_V) 37948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 38048c6f328SShengzhou Liu 381e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 38248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 38348c6f328SShengzhou Liu | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 38448c6f328SShengzhou Liu | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 38548c6f328SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 38648c6f328SShengzhou Liu | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 38748c6f328SShengzhou Liu | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 38848c6f328SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 389e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 390e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 3917842950fSJaiprakash Singh #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 3927842950fSJaiprakash Singh | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 3937842950fSJaiprakash Singh | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 394e8a7f1c3SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 395e8a7f1c3SShengzhou Liu | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 396e8a7f1c3SShengzhou Liu | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 397e8a7f1c3SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 398e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 399e8a7f1c3SShengzhou Liu #endif 40048c6f328SShengzhou Liu 40148c6f328SShengzhou Liu #define CONFIG_SYS_NAND_ONFI_DETECTION 40248c6f328SShengzhou Liu /* ONFI NAND Flash mode0 Timing Params */ 40348c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 40448c6f328SShengzhou Liu FTIM0_NAND_TWP(0x18) | \ 40548c6f328SShengzhou Liu FTIM0_NAND_TWCHT(0x07) | \ 40648c6f328SShengzhou Liu FTIM0_NAND_TWH(0x0a)) 40748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 40848c6f328SShengzhou Liu FTIM1_NAND_TWBE(0x39) | \ 40948c6f328SShengzhou Liu FTIM1_NAND_TRR(0x0e) | \ 41048c6f328SShengzhou Liu FTIM1_NAND_TRP(0x18)) 41148c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 41248c6f328SShengzhou Liu FTIM2_NAND_TREH(0x0a) | \ 41348c6f328SShengzhou Liu FTIM2_NAND_TWHRE(0x1e)) 41448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM3 0x0 41548c6f328SShengzhou Liu 41648c6f328SShengzhou Liu #define CONFIG_SYS_NAND_DDR_LAW 11 41748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 41848c6f328SShengzhou Liu #define CONFIG_SYS_MAX_NAND_DEVICE 1 41948c6f328SShengzhou Liu #define CONFIG_CMD_NAND 42048c6f328SShengzhou Liu 42148c6f328SShengzhou Liu #if defined(CONFIG_NAND) 42248c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 42348c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 42448c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 42548c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 42648c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 42748c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 42848c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 42948c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 43048c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 43148c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 43248c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 43348c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 43448c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 43548c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 43648c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 43748c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 43848c6f328SShengzhou Liu #else 43948c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 44048c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 44148c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 44248c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 44348c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 44448c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 44548c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 44648c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 44748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 44848c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 44948c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 45048c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 45148c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 45248c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 45348c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 45448c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 45548c6f328SShengzhou Liu #endif 45648c6f328SShengzhou Liu 45748c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 45848c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 45948c6f328SShengzhou Liu #else 46048c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 46148c6f328SShengzhou Liu #endif 46248c6f328SShengzhou Liu 46348c6f328SShengzhou Liu #if defined(CONFIG_RAMBOOT_PBL) 46448c6f328SShengzhou Liu #define CONFIG_SYS_RAMBOOT 46548c6f328SShengzhou Liu #endif 46648c6f328SShengzhou Liu 46748c6f328SShengzhou Liu #define CONFIG_BOARD_EARLY_INIT_R 46848c6f328SShengzhou Liu #define CONFIG_MISC_INIT_R 46948c6f328SShengzhou Liu 47048c6f328SShengzhou Liu #define CONFIG_HWCONFIG 47148c6f328SShengzhou Liu 47248c6f328SShengzhou Liu /* define to use L1 as initial stack */ 47348c6f328SShengzhou Liu #define CONFIG_L1_INIT_RAM 47448c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_LOCK 47548c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 47648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 47748c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 478b3142e2cSYork Sun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 47948c6f328SShengzhou Liu /* The assembler doesn't like typecast */ 48048c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 48148c6f328SShengzhou Liu ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 48248c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 48348c6f328SShengzhou Liu #else 484b3142e2cSYork Sun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 48548c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 48648c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 48748c6f328SShengzhou Liu #endif 48848c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 48948c6f328SShengzhou Liu 49048c6f328SShengzhou Liu #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 49148c6f328SShengzhou Liu GENERATED_GBL_DATA_SIZE) 49248c6f328SShengzhou Liu #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 49348c6f328SShengzhou Liu 49448c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 49548c6f328SShengzhou Liu #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 49648c6f328SShengzhou Liu 49748c6f328SShengzhou Liu /* Serial Port */ 49848c6f328SShengzhou Liu #define CONFIG_CONS_INDEX 1 49948c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_SERIAL 50048c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_REG_SIZE 1 50148c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 50248c6f328SShengzhou Liu 50348c6f328SShengzhou Liu #define CONFIG_SYS_BAUDRATE_TABLE \ 50448c6f328SShengzhou Liu {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 50548c6f328SShengzhou Liu 50648c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 50748c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 50848c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 50948c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 51048c6f328SShengzhou Liu #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 51148c6f328SShengzhou Liu 51248c6f328SShengzhou Liu /* Video */ 51348c6f328SShengzhou Liu #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 51448c6f328SShengzhou Liu #ifdef CONFIG_FSL_DIU_FB 51548c6f328SShengzhou Liu #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 51648c6f328SShengzhou Liu #define CONFIG_VIDEO 51748c6f328SShengzhou Liu #define CONFIG_CMD_BMP 51848c6f328SShengzhou Liu #define CONFIG_CFB_CONSOLE 51948c6f328SShengzhou Liu #define CONFIG_VIDEO_SW_CURSOR 52048c6f328SShengzhou Liu #define CONFIG_VGA_AS_SINGLE_DEVICE 52148c6f328SShengzhou Liu #define CONFIG_VIDEO_LOGO 52248c6f328SShengzhou Liu #define CONFIG_VIDEO_BMP_LOGO 52348c6f328SShengzhou Liu #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 52448c6f328SShengzhou Liu /* 52548c6f328SShengzhou Liu * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 52648c6f328SShengzhou Liu * disable empty flash sector detection, which is I/O-intensive. 52748c6f328SShengzhou Liu */ 52848c6f328SShengzhou Liu #undef CONFIG_SYS_FLASH_EMPTY_INFO 52948c6f328SShengzhou Liu #endif 53048c6f328SShengzhou Liu 53148c6f328SShengzhou Liu /* I2C */ 53248c6f328SShengzhou Liu #define CONFIG_SYS_I2C 53348c6f328SShengzhou Liu #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 53448c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 53548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 53648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 53748c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 53848c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 53948c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 54048c6f328SShengzhou Liu 541ff7ea2d1SShengzhou Liu #define I2C_PCA6408_BUS_NUM 1 542ff7ea2d1SShengzhou Liu #define I2C_PCA6408_ADDR 0x20 54348c6f328SShengzhou Liu 54448c6f328SShengzhou Liu /* I2C bus multiplexer */ 54548c6f328SShengzhou Liu #define I2C_MUX_CH_DEFAULT 0x8 54648c6f328SShengzhou Liu 54748c6f328SShengzhou Liu /* 54848c6f328SShengzhou Liu * RTC configuration 54948c6f328SShengzhou Liu */ 55048c6f328SShengzhou Liu #define RTC 55148c6f328SShengzhou Liu #define CONFIG_RTC_DS1337 1 55248c6f328SShengzhou Liu #define CONFIG_SYS_I2C_RTC_ADDR 0x68 55348c6f328SShengzhou Liu 55448c6f328SShengzhou Liu /* 55548c6f328SShengzhou Liu * eSPI - Enhanced SPI 55648c6f328SShengzhou Liu */ 55748c6f328SShengzhou Liu #define CONFIG_SPI_FLASH_BAR 55848c6f328SShengzhou Liu #define CONFIG_SF_DEFAULT_SPEED 10000000 55948c6f328SShengzhou Liu #define CONFIG_SF_DEFAULT_MODE 0 56048c6f328SShengzhou Liu 56148c6f328SShengzhou Liu /* 56248c6f328SShengzhou Liu * General PCIe 56348c6f328SShengzhou Liu * Memory space is mapped 1-1, but I/O space must start from 0. 56448c6f328SShengzhou Liu */ 56548c6f328SShengzhou Liu #define CONFIG_PCI /* Enable PCI/PCIE */ 566b38eaec5SRobert P. J. Day #define CONFIG_PCIE1 /* PCIE controller 1 */ 567b38eaec5SRobert P. J. Day #define CONFIG_PCIE2 /* PCIE controller 2 */ 568b38eaec5SRobert P. J. Day #define CONFIG_PCIE3 /* PCIE controller 3 */ 56948c6f328SShengzhou Liu #ifdef CONFIG_PPC_T1040 570b38eaec5SRobert P. J. Day #define CONFIG_PCIE4 /* PCIE controller 4 */ 57148c6f328SShengzhou Liu #endif 57248c6f328SShengzhou Liu #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 57348c6f328SShengzhou Liu #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57448c6f328SShengzhou Liu #define CONFIG_PCI_INDIRECT_BRIDGE 57548c6f328SShengzhou Liu 57648c6f328SShengzhou Liu #ifdef CONFIG_PCI 57748c6f328SShengzhou Liu /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 57848c6f328SShengzhou Liu #ifdef CONFIG_PCIE1 57948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 58048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 58148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 58248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 58348c6f328SShengzhou Liu #else 58448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 58548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 58648c6f328SShengzhou Liu #endif 58748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 58848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 58948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 59048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 59148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 59248c6f328SShengzhou Liu #else 59348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 59448c6f328SShengzhou Liu #endif 59548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 59648c6f328SShengzhou Liu #endif 59748c6f328SShengzhou Liu 59848c6f328SShengzhou Liu /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 59948c6f328SShengzhou Liu #ifdef CONFIG_PCIE2 60048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 60148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 60248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 60348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 60448c6f328SShengzhou Liu #else 60548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 60648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 60748c6f328SShengzhou Liu #endif 60848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 60948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 61048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 61148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 61248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 61348c6f328SShengzhou Liu #else 61448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 61548c6f328SShengzhou Liu #endif 61648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 61748c6f328SShengzhou Liu #endif 61848c6f328SShengzhou Liu 61948c6f328SShengzhou Liu /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 62048c6f328SShengzhou Liu #ifdef CONFIG_PCIE3 62148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 62248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 62348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 62448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 62548c6f328SShengzhou Liu #else 62648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 62748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 62848c6f328SShengzhou Liu #endif 62948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 63048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 63148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 63248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 63348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 63448c6f328SShengzhou Liu #else 63548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 63648c6f328SShengzhou Liu #endif 63748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 63848c6f328SShengzhou Liu #endif 63948c6f328SShengzhou Liu 64048c6f328SShengzhou Liu /* controller 4, Base address 203000, to be removed */ 64148c6f328SShengzhou Liu #ifdef CONFIG_PCIE4 64248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 64348c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 64448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 64548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 64648c6f328SShengzhou Liu #else 64748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 64848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 64948c6f328SShengzhou Liu #endif 65048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 65148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 65248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 65348c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 65448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 65548c6f328SShengzhou Liu #else 65648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 65748c6f328SShengzhou Liu #endif 65848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 65948c6f328SShengzhou Liu #endif 66048c6f328SShengzhou Liu 66148c6f328SShengzhou Liu #define CONFIG_PCI_PNP /* do pci plug-and-play */ 66248c6f328SShengzhou Liu #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 66348c6f328SShengzhou Liu #define CONFIG_DOS_PARTITION 66448c6f328SShengzhou Liu #endif /* CONFIG_PCI */ 66548c6f328SShengzhou Liu 66648c6f328SShengzhou Liu /* 66748c6f328SShengzhou Liu * USB 66848c6f328SShengzhou Liu */ 66948c6f328SShengzhou Liu #define CONFIG_HAS_FSL_DR_USB 67048c6f328SShengzhou Liu 67148c6f328SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 67248c6f328SShengzhou Liu #define CONFIG_USB_EHCI 67348c6f328SShengzhou Liu #define CONFIG_USB_STORAGE 67448c6f328SShengzhou Liu #define CONFIG_USB_EHCI_FSL 67548c6f328SShengzhou Liu #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 67648c6f328SShengzhou Liu #endif 67748c6f328SShengzhou Liu 67848c6f328SShengzhou Liu /* 67948c6f328SShengzhou Liu * SDHC 68048c6f328SShengzhou Liu */ 68148c6f328SShengzhou Liu #define CONFIG_MMC 68248c6f328SShengzhou Liu #ifdef CONFIG_MMC 68348c6f328SShengzhou Liu #define CONFIG_FSL_ESDHC 68448c6f328SShengzhou Liu #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 68548c6f328SShengzhou Liu #define CONFIG_GENERIC_MMC 68648c6f328SShengzhou Liu #define CONFIG_DOS_PARTITION 68748c6f328SShengzhou Liu #endif 68848c6f328SShengzhou Liu 68948c6f328SShengzhou Liu /* Qman/Bman */ 69048c6f328SShengzhou Liu #ifndef CONFIG_NOBQFMAN 69148c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 6922a8b3422SJeffrey Ladouceur #define CONFIG_SYS_BMAN_NUM_PORTALS 10 69348c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 69448c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 69548c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 69648c6f328SShengzhou Liu #else 69748c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 69848c6f328SShengzhou Liu #endif 69948c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 7003fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 7013fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 7023fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 7033fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 7043fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 7053fa66db4SJeffrey Ladouceur CONFIG_SYS_BMAN_CENA_SIZE) 7063fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 7073fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 7082a8b3422SJeffrey Ladouceur #define CONFIG_SYS_QMAN_NUM_PORTALS 10 70948c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 71048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 71148c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 71248c6f328SShengzhou Liu #else 71348c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 71448c6f328SShengzhou Liu #endif 71548c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 7163fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 7173fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 7183fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 7193fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 7203fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 7213fa66db4SJeffrey Ladouceur CONFIG_SYS_QMAN_CENA_SIZE) 7223fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 7233fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 72448c6f328SShengzhou Liu 72548c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_FMAN 72648c6f328SShengzhou Liu 727ff7ea2d1SShengzhou Liu #ifdef CONFIG_T1024RDB 72848c6f328SShengzhou Liu #define CONFIG_QE 72948c6f328SShengzhou Liu #define CONFIG_U_QE 730ff7ea2d1SShengzhou Liu #endif 73148c6f328SShengzhou Liu /* Default address of microcode for the Linux FMan driver */ 73248c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 73348c6f328SShengzhou Liu /* 73448c6f328SShengzhou Liu * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 73548c6f328SShengzhou Liu * env, so we got 0x110000. 73648c6f328SShengzhou Liu */ 73748c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_IN_SPIFLASH 73848c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 73948c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0x130000 74048c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 74148c6f328SShengzhou Liu /* 74248c6f328SShengzhou Liu * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 74348c6f328SShengzhou Liu * about 1MB (2048 blocks), Env is stored after the image, and the env size is 74448c6f328SShengzhou Liu * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 74548c6f328SShengzhou Liu */ 74648c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 74748c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 74848c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 74948c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 75048c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 751e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 75248c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 75348c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 754e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 755e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 756e8a7f1c3SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 757e8a7f1c3SShengzhou Liu #endif 75848c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 75948c6f328SShengzhou Liu /* 76048c6f328SShengzhou Liu * Slave has no ucode locally, it can fetch this from remote. When implementing 76148c6f328SShengzhou Liu * in two corenet boards, slave's ucode could be stored in master's memory 76248c6f328SShengzhou Liu * space, the address can be mapped from slave TLB->slave LAW-> 76348c6f328SShengzhou Liu * slave SRIO or PCIE outbound window->master inbound window-> 76448c6f328SShengzhou Liu * master LAW->the ucode address in master's memory space. 76548c6f328SShengzhou Liu */ 76648c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 76748c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 76848c6f328SShengzhou Liu #else 76948c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 77048c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 77148c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 77248c6f328SShengzhou Liu #endif 77348c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 77448c6f328SShengzhou Liu #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 77548c6f328SShengzhou Liu #endif /* CONFIG_NOBQFMAN */ 77648c6f328SShengzhou Liu 77748c6f328SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 77848c6f328SShengzhou Liu #define CONFIG_FMAN_ENET 77948c6f328SShengzhou Liu #define CONFIG_PHYLIB_10G 78048c6f328SShengzhou Liu #define CONFIG_PHY_REALTEK 781e26416a3SShengzhou Liu #define CONFIG_PHY_AQUANTIA 782e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 78348c6f328SShengzhou Liu #define RGMII_PHY1_ADDR 0x2 78448c6f328SShengzhou Liu #define RGMII_PHY2_ADDR 0x6 785e8a7f1c3SShengzhou Liu #define SGMII_AQR_PHY_ADDR 0x2 78648c6f328SShengzhou Liu #define FM1_10GEC1_PHY_ADDR 0x1 787e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 788e8a7f1c3SShengzhou Liu #define RGMII_PHY1_ADDR 0x1 789e8a7f1c3SShengzhou Liu #define SGMII_RTK_PHY_ADDR 0x3 790e8a7f1c3SShengzhou Liu #define SGMII_AQR_PHY_ADDR 0x2 791e8a7f1c3SShengzhou Liu #endif 79248c6f328SShengzhou Liu #endif 79348c6f328SShengzhou Liu 79448c6f328SShengzhou Liu #ifdef CONFIG_FMAN_ENET 79548c6f328SShengzhou Liu #define CONFIG_MII /* MII PHY management */ 79648c6f328SShengzhou Liu #define CONFIG_ETHPRIME "FM1@DTSEC4" 79748c6f328SShengzhou Liu #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 79848c6f328SShengzhou Liu #endif 79948c6f328SShengzhou Liu 80048c6f328SShengzhou Liu /* 80148c6f328SShengzhou Liu * Dynamic MTD Partition support with mtdparts 80248c6f328SShengzhou Liu */ 80348c6f328SShengzhou Liu #ifndef CONFIG_SYS_NO_FLASH 80448c6f328SShengzhou Liu #define CONFIG_MTD_DEVICE 80548c6f328SShengzhou Liu #define CONFIG_MTD_PARTITIONS 80648c6f328SShengzhou Liu #define CONFIG_CMD_MTDPARTS 80748c6f328SShengzhou Liu #define CONFIG_FLASH_CFI_MTD 80848c6f328SShengzhou Liu #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 80948c6f328SShengzhou Liu "spi0=spife110000.1" 81048c6f328SShengzhou Liu #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 81148c6f328SShengzhou Liu "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 81248c6f328SShengzhou Liu "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 81348c6f328SShengzhou Liu "1m(uboot),5m(kernel),128k(dtb),-(user)" 81448c6f328SShengzhou Liu #endif 81548c6f328SShengzhou Liu 81648c6f328SShengzhou Liu /* 81748c6f328SShengzhou Liu * Environment 81848c6f328SShengzhou Liu */ 81948c6f328SShengzhou Liu #define CONFIG_LOADS_ECHO /* echo on for serial download */ 82048c6f328SShengzhou Liu #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 82148c6f328SShengzhou Liu 82248c6f328SShengzhou Liu /* 82348c6f328SShengzhou Liu * Command line configuration. 82448c6f328SShengzhou Liu */ 82548c6f328SShengzhou Liu #define CONFIG_CMD_DATE 82648c6f328SShengzhou Liu #define CONFIG_CMD_EEPROM 82748c6f328SShengzhou Liu #define CONFIG_CMD_ERRATA 82848c6f328SShengzhou Liu #define CONFIG_CMD_IRQ 82948c6f328SShengzhou Liu #define CONFIG_CMD_REGINFO 83048c6f328SShengzhou Liu 83148c6f328SShengzhou Liu #ifdef CONFIG_PCI 83248c6f328SShengzhou Liu #define CONFIG_CMD_PCI 83348c6f328SShengzhou Liu #endif 83448c6f328SShengzhou Liu 83548c6f328SShengzhou Liu /* 83648c6f328SShengzhou Liu * Miscellaneous configurable options 83748c6f328SShengzhou Liu */ 83848c6f328SShengzhou Liu #define CONFIG_SYS_LONGHELP /* undef to save memory */ 83948c6f328SShengzhou Liu #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 84048c6f328SShengzhou Liu #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 84148c6f328SShengzhou Liu #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 84248c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 84348c6f328SShengzhou Liu #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 84448c6f328SShengzhou Liu #else 84548c6f328SShengzhou Liu #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 84648c6f328SShengzhou Liu #endif 84748c6f328SShengzhou Liu #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 84848c6f328SShengzhou Liu #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 84948c6f328SShengzhou Liu #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 85048c6f328SShengzhou Liu 85148c6f328SShengzhou Liu /* 85248c6f328SShengzhou Liu * For booting Linux, the board info and command line data 85348c6f328SShengzhou Liu * have to be in the first 64 MB of memory, since this is 85448c6f328SShengzhou Liu * the maximum mapped by the Linux kernel during initialization. 85548c6f328SShengzhou Liu */ 85648c6f328SShengzhou Liu #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 85748c6f328SShengzhou Liu #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 85848c6f328SShengzhou Liu 85948c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 86048c6f328SShengzhou Liu #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 86148c6f328SShengzhou Liu #endif 86248c6f328SShengzhou Liu 86348c6f328SShengzhou Liu /* 86448c6f328SShengzhou Liu * Environment Configuration 86548c6f328SShengzhou Liu */ 86648c6f328SShengzhou Liu #define CONFIG_ROOTPATH "/opt/nfsroot" 86748c6f328SShengzhou Liu #define CONFIG_BOOTFILE "uImage" 868e8a7f1c3SShengzhou Liu #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 86948c6f328SShengzhou Liu #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 87048c6f328SShengzhou Liu #define CONFIG_BAUDRATE 115200 87148c6f328SShengzhou Liu #define __USB_PHY_TYPE utmi 87248c6f328SShengzhou Liu 87348c6f328SShengzhou Liu #ifdef CONFIG_PPC_T1024 874e8a7f1c3SShengzhou Liu #define CONFIG_BOARDNAME t1024rdb 875e8a7f1c3SShengzhou Liu #define BANK_INTLV cs0_cs1 87648c6f328SShengzhou Liu #else 877e8a7f1c3SShengzhou Liu #define CONFIG_BOARDNAME t1023rdb 878e8a7f1c3SShengzhou Liu #define BANK_INTLV null 87948c6f328SShengzhou Liu #endif 88048c6f328SShengzhou Liu 88148c6f328SShengzhou Liu #define CONFIG_EXTRA_ENV_SETTINGS \ 88248c6f328SShengzhou Liu "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 883e8a7f1c3SShengzhou Liu "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 88448c6f328SShengzhou Liu "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 88548c6f328SShengzhou Liu "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 88648c6f328SShengzhou Liu "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 88748c6f328SShengzhou Liu __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 88848c6f328SShengzhou Liu "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 88948c6f328SShengzhou Liu "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 89048c6f328SShengzhou Liu "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 89148c6f328SShengzhou Liu "netdev=eth0\0" \ 89248c6f328SShengzhou Liu "tftpflash=tftpboot $loadaddr $uboot && " \ 89348c6f328SShengzhou Liu "protect off $ubootaddr +$filesize && " \ 89448c6f328SShengzhou Liu "erase $ubootaddr +$filesize && " \ 89548c6f328SShengzhou Liu "cp.b $loadaddr $ubootaddr $filesize && " \ 89648c6f328SShengzhou Liu "protect on $ubootaddr +$filesize && " \ 89748c6f328SShengzhou Liu "cmp.b $loadaddr $ubootaddr $filesize\0" \ 89848c6f328SShengzhou Liu "consoledev=ttyS0\0" \ 89948c6f328SShengzhou Liu "ramdiskaddr=2000000\0" \ 900*b24a4f62SScott Wood "fdtaddr=1e00000\0" \ 90148c6f328SShengzhou Liu "bdev=sda3\0" 90248c6f328SShengzhou Liu 90348c6f328SShengzhou Liu #define CONFIG_LINUX \ 90448c6f328SShengzhou Liu "setenv bootargs root=/dev/ram rw " \ 90548c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 90648c6f328SShengzhou Liu "setenv ramdiskaddr 0x02000000;" \ 90748c6f328SShengzhou Liu "setenv fdtaddr 0x00c00000;" \ 90848c6f328SShengzhou Liu "setenv loadaddr 0x1000000;" \ 90948c6f328SShengzhou Liu "bootm $loadaddr $ramdiskaddr $fdtaddr" 91048c6f328SShengzhou Liu 91148c6f328SShengzhou Liu #define CONFIG_NFSBOOTCOMMAND \ 91248c6f328SShengzhou Liu "setenv bootargs root=/dev/nfs rw " \ 91348c6f328SShengzhou Liu "nfsroot=$serverip:$rootpath " \ 91448c6f328SShengzhou Liu "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 91548c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 91648c6f328SShengzhou Liu "tftp $loadaddr $bootfile;" \ 91748c6f328SShengzhou Liu "tftp $fdtaddr $fdtfile;" \ 91848c6f328SShengzhou Liu "bootm $loadaddr - $fdtaddr" 91948c6f328SShengzhou Liu 92048c6f328SShengzhou Liu #define CONFIG_BOOTCOMMAND CONFIG_LINUX 92148c6f328SShengzhou Liu 922ef6c55a2SAneesh Bansal /* Hash command with SHA acceleration supported in hardware */ 923ef6c55a2SAneesh Bansal #ifdef CONFIG_FSL_CAAM 924ef6c55a2SAneesh Bansal #define CONFIG_CMD_HASH 925ef6c55a2SAneesh Bansal #define CONFIG_SHA_HW_ACCEL 926ef6c55a2SAneesh Bansal #endif 927ef6c55a2SAneesh Bansal 92848c6f328SShengzhou Liu #include <asm/fsl_secure_boot.h> 929ef6c55a2SAneesh Bansal 93048c6f328SShengzhou Liu #endif /* __T1024RDB_H */ 931