148c6f328SShengzhou Liu /* 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 348c6f328SShengzhou Liu * 448c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 548c6f328SShengzhou Liu */ 648c6f328SShengzhou Liu 748c6f328SShengzhou Liu /* 848c6f328SShengzhou Liu * T1024/T1023 RDB board configuration file 948c6f328SShengzhou Liu */ 1048c6f328SShengzhou Liu 1148c6f328SShengzhou Liu #ifndef __T1024RDB_H 1248c6f328SShengzhou Liu #define __T1024RDB_H 1348c6f328SShengzhou Liu 14e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1023RDB) 15e8a7f1c3SShengzhou Liu #ifdef CONFIG_SPL 16e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NO_FLASH 17e8a7f1c3SShengzhou Liu #endif 18e8a7f1c3SShengzhou Liu #endif 19e8a7f1c3SShengzhou Liu 2048c6f328SShengzhou Liu /* High Level Configuration Options */ 2148c6f328SShengzhou Liu #define CONFIG_SYS_GENERIC_BOARD 2248c6f328SShengzhou Liu #define CONFIG_DISPLAY_BOARDINFO 2348c6f328SShengzhou Liu #define CONFIG_BOOKE 2448c6f328SShengzhou Liu #define CONFIG_E500 /* BOOKE e500 family */ 2548c6f328SShengzhou Liu #define CONFIG_E500MC /* BOOKE e500mc family */ 2648c6f328SShengzhou Liu #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 2748c6f328SShengzhou Liu #define CONFIG_MP /* support multiple processors */ 2848c6f328SShengzhou Liu #define CONFIG_PHYS_64BIT 2948c6f328SShengzhou Liu #define CONFIG_ENABLE_36BIT_PHYS 3048c6f328SShengzhou Liu 3148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 3248c6f328SShengzhou Liu #define CONFIG_ADDR_MAP 1 3348c6f328SShengzhou Liu #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 3448c6f328SShengzhou Liu #endif 3548c6f328SShengzhou Liu 3648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 3748c6f328SShengzhou Liu #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 3848c6f328SShengzhou Liu #define CONFIG_FSL_IFC /* Enable IFC Support */ 3948c6f328SShengzhou Liu 4048c6f328SShengzhou Liu #define CONFIG_FSL_LAW /* Use common FSL init code */ 4148c6f328SShengzhou Liu #define CONFIG_ENV_OVERWRITE 4248c6f328SShengzhou Liu 4348c6f328SShengzhou Liu /* support deep sleep */ 44e8a7f1c3SShengzhou Liu #ifdef CONFIG_PPC_T1024 4548c6f328SShengzhou Liu #define CONFIG_DEEP_SLEEP 46e8a7f1c3SShengzhou Liu #endif 47f49b8c1bStang yuantian #if defined(CONFIG_DEEP_SLEEP) 4848c6f328SShengzhou Liu #define CONFIG_SILENT_CONSOLE 49f49b8c1bStang yuantian #define CONFIG_BOARD_EARLY_INIT_F 50f49b8c1bStang yuantian #endif 5148c6f328SShengzhou Liu 5248c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 5348c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 54e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 5548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 56e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 57e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 58e8a7f1c3SShengzhou Liu #endif 5948c6f328SShengzhou Liu #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 6048c6f328SShengzhou Liu #define CONFIG_SPL_ENV_SUPPORT 6148c6f328SShengzhou Liu #define CONFIG_SPL_SERIAL_SUPPORT 6248c6f328SShengzhou Liu #define CONFIG_SPL_FLUSH_IMAGE 6348c6f328SShengzhou Liu #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 6448c6f328SShengzhou Liu #define CONFIG_SPL_LIBGENERIC_SUPPORT 6548c6f328SShengzhou Liu #define CONFIG_SPL_LIBCOMMON_SUPPORT 6648c6f328SShengzhou Liu #define CONFIG_SPL_I2C_SUPPORT 6748c6f328SShengzhou Liu #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 6848c6f328SShengzhou Liu #define CONFIG_FSL_LAW /* Use common FSL init code */ 69f49b8c1bStang yuantian #define CONFIG_SYS_TEXT_BASE 0x30001000 7048c6f328SShengzhou Liu #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 7148c6f328SShengzhou Liu #define CONFIG_SPL_PAD_TO 0x40000 7248c6f328SShengzhou Liu #define CONFIG_SPL_MAX_SIZE 0x28000 7348c6f328SShengzhou Liu #define RESET_VECTOR_OFFSET 0x27FFC 7448c6f328SShengzhou Liu #define BOOT_PAGE_OFFSET 0x27000 7548c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 7648c6f328SShengzhou Liu #define CONFIG_SPL_SKIP_RELOCATE 7748c6f328SShengzhou Liu #define CONFIG_SPL_COMMON_INIT_DDR 7848c6f328SShengzhou Liu #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 7948c6f328SShengzhou Liu #define CONFIG_SYS_NO_FLASH 8048c6f328SShengzhou Liu #endif 8148c6f328SShengzhou Liu 8248c6f328SShengzhou Liu #ifdef CONFIG_NAND 8348c6f328SShengzhou Liu #define CONFIG_SPL_NAND_SUPPORT 8448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 85f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 86f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 8748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 8848c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 8948c6f328SShengzhou Liu #define CONFIG_SPL_NAND_BOOT 9048c6f328SShengzhou Liu #endif 9148c6f328SShengzhou Liu 9248c6f328SShengzhou Liu #ifdef CONFIG_SPIFLASH 93f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 9448c6f328SShengzhou Liu #define CONFIG_SPL_SPI_SUPPORT 9548c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_SUPPORT 9648c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_MINIMAL 9748c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 98f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 99f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 10048c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 10148c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 10248c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 10348c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 10448c6f328SShengzhou Liu #endif 10548c6f328SShengzhou Liu #define CONFIG_SPL_SPI_BOOT 10648c6f328SShengzhou Liu #endif 10748c6f328SShengzhou Liu 10848c6f328SShengzhou Liu #ifdef CONFIG_SDCARD 109f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 11048c6f328SShengzhou Liu #define CONFIG_SPL_MMC_SUPPORT 11148c6f328SShengzhou Liu #define CONFIG_SPL_MMC_MINIMAL 11248c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 113f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 114f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 11548c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 11648c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 11748c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 11848c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 11948c6f328SShengzhou Liu #endif 12048c6f328SShengzhou Liu #define CONFIG_SPL_MMC_BOOT 12148c6f328SShengzhou Liu #endif 12248c6f328SShengzhou Liu 12348c6f328SShengzhou Liu #endif /* CONFIG_RAMBOOT_PBL */ 12448c6f328SShengzhou Liu 12548c6f328SShengzhou Liu #ifndef CONFIG_SYS_TEXT_BASE 12648c6f328SShengzhou Liu #define CONFIG_SYS_TEXT_BASE 0xeff40000 12748c6f328SShengzhou Liu #endif 12848c6f328SShengzhou Liu 12948c6f328SShengzhou Liu #ifndef CONFIG_RESET_VECTOR_ADDRESS 13048c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 13148c6f328SShengzhou Liu #endif 13248c6f328SShengzhou Liu 13348c6f328SShengzhou Liu #ifndef CONFIG_SYS_NO_FLASH 13448c6f328SShengzhou Liu #define CONFIG_FLASH_CFI_DRIVER 13548c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_CFI 13648c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 13748c6f328SShengzhou Liu #endif 13848c6f328SShengzhou Liu 13948c6f328SShengzhou Liu /* PCIe Boot - Master */ 14048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_MASTER 14148c6f328SShengzhou Liu /* 14248c6f328SShengzhou Liu * for slave u-boot IMAGE instored in master memory space, 14348c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 14448c6f328SShengzhou Liu */ 14548c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 14648c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 14748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 14848c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 14948c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 15048c6f328SShengzhou Liu #else 15148c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 15248c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 15348c6f328SShengzhou Liu #endif 15448c6f328SShengzhou Liu /* 15548c6f328SShengzhou Liu * for slave UCODE and ENV instored in master memory space, 15648c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 15748c6f328SShengzhou Liu */ 15848c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 15948c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 16048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 16148c6f328SShengzhou Liu #else 16248c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 16348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 16448c6f328SShengzhou Liu #endif 16548c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 16648c6f328SShengzhou Liu /* slave core release by master*/ 16748c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 16848c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 16948c6f328SShengzhou Liu 17048c6f328SShengzhou Liu /* PCIe Boot - Slave */ 17148c6f328SShengzhou Liu #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 17248c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 17348c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 17448c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 17548c6f328SShengzhou Liu /* Set 1M boot space for PCIe boot */ 17648c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 17748c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 17848c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 17948c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18048c6f328SShengzhou Liu #define CONFIG_SYS_NO_FLASH 18148c6f328SShengzhou Liu #endif 18248c6f328SShengzhou Liu 18348c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 18448c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 18548c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_SPI_FLASH 18648c6f328SShengzhou Liu #define CONFIG_ENV_SPI_BUS 0 18748c6f328SShengzhou Liu #define CONFIG_ENV_SPI_CS 0 18848c6f328SShengzhou Liu #define CONFIG_ENV_SPI_MAX_HZ 10000000 18948c6f328SShengzhou Liu #define CONFIG_ENV_SPI_MODE 0 19048c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 19148c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 192e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 19348c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x10000 194e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 195e8a7f1c3SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x40000 196e8a7f1c3SShengzhou Liu #endif 19748c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 19848c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 19948c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_MMC 20048c6f328SShengzhou Liu #define CONFIG_SYS_MMC_ENV_DEV 0 20148c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 20248c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (512 * 0x800) 20348c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 20448c6f328SShengzhou Liu #define CONFIG_SYS_EXTRA_ENV_RELOC 20548c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_NAND 20648c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 207e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 20848c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 209e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 210e8a7f1c3SShengzhou Liu #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 211e8a7f1c3SShengzhou Liu #endif 21248c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 21348c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_REMOTE 21448c6f328SShengzhou Liu #define CONFIG_ENV_ADDR 0xffe20000 21548c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 21648c6f328SShengzhou Liu #elif defined(CONFIG_ENV_IS_NOWHERE) 21748c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 21848c6f328SShengzhou Liu #else 21948c6f328SShengzhou Liu #define CONFIG_ENV_IS_IN_FLASH 22048c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 22148c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 22248c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 22348c6f328SShengzhou Liu #endif 22448c6f328SShengzhou Liu 22548c6f328SShengzhou Liu 22648c6f328SShengzhou Liu #ifndef __ASSEMBLY__ 22748c6f328SShengzhou Liu unsigned long get_board_sys_clk(void); 22848c6f328SShengzhou Liu unsigned long get_board_ddr_clk(void); 22948c6f328SShengzhou Liu #endif 23048c6f328SShengzhou Liu 23148c6f328SShengzhou Liu #define CONFIG_SYS_CLK_FREQ 100000000 232e8a7f1c3SShengzhou Liu #define CONFIG_DDR_CLK_FREQ 100000000 23348c6f328SShengzhou Liu 23448c6f328SShengzhou Liu /* 23548c6f328SShengzhou Liu * These can be toggled for performance analysis, otherwise use default. 23648c6f328SShengzhou Liu */ 23748c6f328SShengzhou Liu #define CONFIG_SYS_CACHE_STASHING 23848c6f328SShengzhou Liu #define CONFIG_BACKSIDE_L2_CACHE 23948c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 24048c6f328SShengzhou Liu #define CONFIG_BTB /* toggle branch predition */ 24148c6f328SShengzhou Liu #define CONFIG_DDR_ECC 24248c6f328SShengzhou Liu #ifdef CONFIG_DDR_ECC 24348c6f328SShengzhou Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 24448c6f328SShengzhou Liu #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 24548c6f328SShengzhou Liu #endif 24648c6f328SShengzhou Liu 247e8a7f1c3SShengzhou Liu #define CONFIG_CMD_MEMTEST 24848c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 24948c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_END 0x00400000 25048c6f328SShengzhou Liu #define CONFIG_SYS_ALT_MEMTEST 25148c6f328SShengzhou Liu #define CONFIG_PANIC_HANG /* do not reset board on panic */ 25248c6f328SShengzhou Liu 25348c6f328SShengzhou Liu /* 25448c6f328SShengzhou Liu * Config the L3 Cache as L3 SRAM 25548c6f328SShengzhou Liu */ 25648c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 25748c6f328SShengzhou Liu #define CONFIG_SYS_L3_SIZE (256 << 10) 25848c6f328SShengzhou Liu #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 25948c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 26048c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 26148c6f328SShengzhou Liu #endif 26248c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 26348c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 26448c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 26548c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 26648c6f328SShengzhou Liu 26748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 26848c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR 0xf0000000 26948c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 27048c6f328SShengzhou Liu #endif 27148c6f328SShengzhou Liu 27248c6f328SShengzhou Liu /* EEPROM */ 27348c6f328SShengzhou Liu #define CONFIG_ID_EEPROM 27448c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_NXID 27548c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_BUS_NUM 0 27648c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 27748c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 27848c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 27948c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 28048c6f328SShengzhou Liu 28148c6f328SShengzhou Liu /* 28248c6f328SShengzhou Liu * DDR Setup 28348c6f328SShengzhou Liu */ 28448c6f328SShengzhou Liu #define CONFIG_VERY_BIG_RAM 28548c6f328SShengzhou Liu #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 28648c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 28748c6f328SShengzhou Liu #define CONFIG_DIMM_SLOTS_PER_CTLR 1 28848c6f328SShengzhou Liu #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 289e8a7f1c3SShengzhou Liu #define CONFIG_FSL_DDR_INTERACTIVE 290e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 29148c6f328SShengzhou Liu #define CONFIG_DDR_SPD 29248c6f328SShengzhou Liu #define CONFIG_SYS_FSL_DDR3 29348c6f328SShengzhou Liu #define CONFIG_SYS_SPD_BUS_NUM 0 29448c6f328SShengzhou Liu #define SPD_EEPROM_ADDRESS 0x51 29548c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 296e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 297e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FSL_DDR4 298e8a7f1c3SShengzhou Liu #define CONFIG_SYS_DDR_RAW_TIMING 299e8a7f1c3SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 2048 300e8a7f1c3SShengzhou Liu #endif 30148c6f328SShengzhou Liu 30248c6f328SShengzhou Liu /* 30348c6f328SShengzhou Liu * IFC Definitions 30448c6f328SShengzhou Liu */ 30548c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE 0xe8000000 30648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 30748c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 30848c6f328SShengzhou Liu #else 30948c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 31048c6f328SShengzhou Liu #endif 31148c6f328SShengzhou Liu 31248c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 31348c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 31448c6f328SShengzhou Liu CSPR_PORT_SIZE_16 | \ 31548c6f328SShengzhou Liu CSPR_MSEL_NOR | \ 31648c6f328SShengzhou Liu CSPR_V) 31748c6f328SShengzhou Liu #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 31848c6f328SShengzhou Liu 31948c6f328SShengzhou Liu /* NOR Flash Timing Params */ 320e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 32148c6f328SShengzhou Liu #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 322e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 323e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 324e8a7f1c3SShengzhou Liu CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 325e8a7f1c3SShengzhou Liu #endif 32648c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 32748c6f328SShengzhou Liu FTIM0_NOR_TEADC(0x5) | \ 32848c6f328SShengzhou Liu FTIM0_NOR_TEAHC(0x5)) 32948c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 33048c6f328SShengzhou Liu FTIM1_NOR_TRAD_NOR(0x1A) |\ 33148c6f328SShengzhou Liu FTIM1_NOR_TSEQRAD_NOR(0x13)) 33248c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 33348c6f328SShengzhou Liu FTIM2_NOR_TCH(0x4) | \ 33448c6f328SShengzhou Liu FTIM2_NOR_TWPH(0x0E) | \ 33548c6f328SShengzhou Liu FTIM2_NOR_TWP(0x1c)) 33648c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM3 0x0 33748c6f328SShengzhou Liu 33848c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_QUIET_TEST 33948c6f328SShengzhou Liu #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 34048c6f328SShengzhou Liu 34148c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 34248c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 34348c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 34448c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 34548c6f328SShengzhou Liu 34648c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_EMPTY_INFO 34748c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 34848c6f328SShengzhou Liu 349e8a7f1c3SShengzhou Liu #ifdef CONFIG_T1024RDB 35048c6f328SShengzhou Liu /* CPLD on IFC */ 35148c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE 0xffdf0000 35248c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 35348c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2_EXT (0xf) 35448c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 35548c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 \ 35648c6f328SShengzhou Liu | CSPR_MSEL_GPCM \ 35748c6f328SShengzhou Liu | CSPR_V) 35848c6f328SShengzhou Liu #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 35948c6f328SShengzhou Liu #define CONFIG_SYS_CSOR2 0x0 36048c6f328SShengzhou Liu 36148c6f328SShengzhou Liu /* CPLD Timing parameters for IFC CS2 */ 36248c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 36348c6f328SShengzhou Liu FTIM0_GPCM_TEADC(0x0e) | \ 36448c6f328SShengzhou Liu FTIM0_GPCM_TEAHC(0x0e)) 36548c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 36648c6f328SShengzhou Liu FTIM1_GPCM_TRAD(0x1f)) 36748c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 36848c6f328SShengzhou Liu FTIM2_GPCM_TCH(0x8) | \ 36948c6f328SShengzhou Liu FTIM2_GPCM_TWP(0x1f)) 37048c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM3 0x0 371e8a7f1c3SShengzhou Liu #endif 37248c6f328SShengzhou Liu 37348c6f328SShengzhou Liu /* NAND Flash on IFC */ 37448c6f328SShengzhou Liu #define CONFIG_NAND_FSL_IFC 37548c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE 0xff800000 37648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 37748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 37848c6f328SShengzhou Liu #else 37948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 38048c6f328SShengzhou Liu #endif 38148c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 38248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 38348c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 38448c6f328SShengzhou Liu | CSPR_MSEL_NAND /* MSEL = NAND */ \ 38548c6f328SShengzhou Liu | CSPR_V) 38648c6f328SShengzhou Liu #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 38748c6f328SShengzhou Liu 388e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 38948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 39048c6f328SShengzhou Liu | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 39148c6f328SShengzhou Liu | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 39248c6f328SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 39348c6f328SShengzhou Liu | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 39448c6f328SShengzhou Liu | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 39548c6f328SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 396e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 397e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 398*7842950fSJaiprakash Singh #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 399*7842950fSJaiprakash Singh | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 400*7842950fSJaiprakash Singh | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 401e8a7f1c3SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 402e8a7f1c3SShengzhou Liu | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 403e8a7f1c3SShengzhou Liu | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 404e8a7f1c3SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 405e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 406e8a7f1c3SShengzhou Liu #endif 40748c6f328SShengzhou Liu 40848c6f328SShengzhou Liu #define CONFIG_SYS_NAND_ONFI_DETECTION 40948c6f328SShengzhou Liu /* ONFI NAND Flash mode0 Timing Params */ 41048c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 41148c6f328SShengzhou Liu FTIM0_NAND_TWP(0x18) | \ 41248c6f328SShengzhou Liu FTIM0_NAND_TWCHT(0x07) | \ 41348c6f328SShengzhou Liu FTIM0_NAND_TWH(0x0a)) 41448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 41548c6f328SShengzhou Liu FTIM1_NAND_TWBE(0x39) | \ 41648c6f328SShengzhou Liu FTIM1_NAND_TRR(0x0e) | \ 41748c6f328SShengzhou Liu FTIM1_NAND_TRP(0x18)) 41848c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 41948c6f328SShengzhou Liu FTIM2_NAND_TREH(0x0a) | \ 42048c6f328SShengzhou Liu FTIM2_NAND_TWHRE(0x1e)) 42148c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM3 0x0 42248c6f328SShengzhou Liu 42348c6f328SShengzhou Liu #define CONFIG_SYS_NAND_DDR_LAW 11 42448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 42548c6f328SShengzhou Liu #define CONFIG_SYS_MAX_NAND_DEVICE 1 42648c6f328SShengzhou Liu #define CONFIG_CMD_NAND 42748c6f328SShengzhou Liu 42848c6f328SShengzhou Liu #if defined(CONFIG_NAND) 42948c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 43048c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 43148c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 43248c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 43348c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 43448c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 43548c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 43648c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 43748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 43848c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 43948c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 44048c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 44148c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 44248c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 44348c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 44448c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 44548c6f328SShengzhou Liu #else 44648c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 44748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 44848c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 44948c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 45048c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 45148c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 45248c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 45348c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 45448c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 45548c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 45648c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 45748c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 45848c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 45948c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 46048c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 46148c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 46248c6f328SShengzhou Liu #endif 46348c6f328SShengzhou Liu 46448c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 46548c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 46648c6f328SShengzhou Liu #else 46748c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 46848c6f328SShengzhou Liu #endif 46948c6f328SShengzhou Liu 47048c6f328SShengzhou Liu #if defined(CONFIG_RAMBOOT_PBL) 47148c6f328SShengzhou Liu #define CONFIG_SYS_RAMBOOT 47248c6f328SShengzhou Liu #endif 47348c6f328SShengzhou Liu 47448c6f328SShengzhou Liu #define CONFIG_BOARD_EARLY_INIT_R 47548c6f328SShengzhou Liu #define CONFIG_MISC_INIT_R 47648c6f328SShengzhou Liu 47748c6f328SShengzhou Liu #define CONFIG_HWCONFIG 47848c6f328SShengzhou Liu 47948c6f328SShengzhou Liu /* define to use L1 as initial stack */ 48048c6f328SShengzhou Liu #define CONFIG_L1_INIT_RAM 48148c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_LOCK 48248c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 48348c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 48448c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 48548c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 48648c6f328SShengzhou Liu /* The assembler doesn't like typecast */ 48748c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 48848c6f328SShengzhou Liu ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 48948c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 49048c6f328SShengzhou Liu #else 49148c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 49248c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 49348c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 49448c6f328SShengzhou Liu #endif 49548c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 49648c6f328SShengzhou Liu 49748c6f328SShengzhou Liu #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 49848c6f328SShengzhou Liu GENERATED_GBL_DATA_SIZE) 49948c6f328SShengzhou Liu #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 50048c6f328SShengzhou Liu 50148c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 50248c6f328SShengzhou Liu #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 50348c6f328SShengzhou Liu 50448c6f328SShengzhou Liu /* Serial Port */ 50548c6f328SShengzhou Liu #define CONFIG_CONS_INDEX 1 50648c6f328SShengzhou Liu #define CONFIG_SYS_NS16550 50748c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_SERIAL 50848c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_REG_SIZE 1 50948c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 51048c6f328SShengzhou Liu 51148c6f328SShengzhou Liu #define CONFIG_SYS_BAUDRATE_TABLE \ 51248c6f328SShengzhou Liu {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 51348c6f328SShengzhou Liu 51448c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 51548c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 51648c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 51748c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 51848c6f328SShengzhou Liu #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 51948c6f328SShengzhou Liu 52048c6f328SShengzhou Liu /* Use the HUSH parser */ 52148c6f328SShengzhou Liu #define CONFIG_SYS_HUSH_PARSER 52248c6f328SShengzhou Liu #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 52348c6f328SShengzhou Liu 52448c6f328SShengzhou Liu /* Video */ 52548c6f328SShengzhou Liu #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 52648c6f328SShengzhou Liu #ifdef CONFIG_FSL_DIU_FB 52748c6f328SShengzhou Liu #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 52848c6f328SShengzhou Liu #define CONFIG_VIDEO 52948c6f328SShengzhou Liu #define CONFIG_CMD_BMP 53048c6f328SShengzhou Liu #define CONFIG_CFB_CONSOLE 53148c6f328SShengzhou Liu #define CONFIG_VIDEO_SW_CURSOR 53248c6f328SShengzhou Liu #define CONFIG_VGA_AS_SINGLE_DEVICE 53348c6f328SShengzhou Liu #define CONFIG_VIDEO_LOGO 53448c6f328SShengzhou Liu #define CONFIG_VIDEO_BMP_LOGO 53548c6f328SShengzhou Liu #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 53648c6f328SShengzhou Liu /* 53748c6f328SShengzhou Liu * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 53848c6f328SShengzhou Liu * disable empty flash sector detection, which is I/O-intensive. 53948c6f328SShengzhou Liu */ 54048c6f328SShengzhou Liu #undef CONFIG_SYS_FLASH_EMPTY_INFO 54148c6f328SShengzhou Liu #endif 54248c6f328SShengzhou Liu 54348c6f328SShengzhou Liu /* pass open firmware flat tree */ 54448c6f328SShengzhou Liu #define CONFIG_OF_LIBFDT 54548c6f328SShengzhou Liu #define CONFIG_OF_BOARD_SETUP 54648c6f328SShengzhou Liu #define CONFIG_OF_STDOUT_VIA_ALIAS 54748c6f328SShengzhou Liu 54848c6f328SShengzhou Liu /* new uImage format support */ 54948c6f328SShengzhou Liu #define CONFIG_FIT 55048c6f328SShengzhou Liu #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 55148c6f328SShengzhou Liu 55248c6f328SShengzhou Liu /* I2C */ 55348c6f328SShengzhou Liu #define CONFIG_SYS_I2C 55448c6f328SShengzhou Liu #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 55548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 55648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 55748c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 55848c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 55948c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 56048c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 56148c6f328SShengzhou Liu 56248c6f328SShengzhou Liu #define I2C_MUX_PCA_ADDR 0x77 56348c6f328SShengzhou Liu #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 56448c6f328SShengzhou Liu 56548c6f328SShengzhou Liu 56648c6f328SShengzhou Liu /* I2C bus multiplexer */ 56748c6f328SShengzhou Liu #define I2C_MUX_CH_DEFAULT 0x8 56848c6f328SShengzhou Liu 56948c6f328SShengzhou Liu /* 57048c6f328SShengzhou Liu * RTC configuration 57148c6f328SShengzhou Liu */ 57248c6f328SShengzhou Liu #define RTC 57348c6f328SShengzhou Liu #define CONFIG_RTC_DS1337 1 57448c6f328SShengzhou Liu #define CONFIG_SYS_I2C_RTC_ADDR 0x68 57548c6f328SShengzhou Liu 57648c6f328SShengzhou Liu /* 57748c6f328SShengzhou Liu * eSPI - Enhanced SPI 57848c6f328SShengzhou Liu */ 57948c6f328SShengzhou Liu #define CONFIG_FSL_ESPI 580e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 58148c6f328SShengzhou Liu #define CONFIG_SPI_FLASH_STMICRO 582e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 583e8a7f1c3SShengzhou Liu #define CONFIG_SPI_FLASH_SPANSION 584e8a7f1c3SShengzhou Liu #endif 58548c6f328SShengzhou Liu #define CONFIG_CMD_SF 58648c6f328SShengzhou Liu #define CONFIG_SPI_FLASH_BAR 58748c6f328SShengzhou Liu #define CONFIG_SF_DEFAULT_SPEED 10000000 58848c6f328SShengzhou Liu #define CONFIG_SF_DEFAULT_MODE 0 58948c6f328SShengzhou Liu 59048c6f328SShengzhou Liu /* 59148c6f328SShengzhou Liu * General PCIe 59248c6f328SShengzhou Liu * Memory space is mapped 1-1, but I/O space must start from 0. 59348c6f328SShengzhou Liu */ 59448c6f328SShengzhou Liu #define CONFIG_PCI /* Enable PCI/PCIE */ 59548c6f328SShengzhou Liu #define CONFIG_PCIE1 /* PCIE controler 1 */ 59648c6f328SShengzhou Liu #define CONFIG_PCIE2 /* PCIE controler 2 */ 59748c6f328SShengzhou Liu #define CONFIG_PCIE3 /* PCIE controler 3 */ 59848c6f328SShengzhou Liu #ifdef CONFIG_PPC_T1040 59948c6f328SShengzhou Liu #define CONFIG_PCIE4 /* PCIE controler 4 */ 60048c6f328SShengzhou Liu #endif 60148c6f328SShengzhou Liu #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 60248c6f328SShengzhou Liu #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 60348c6f328SShengzhou Liu #define CONFIG_PCI_INDIRECT_BRIDGE 60448c6f328SShengzhou Liu 60548c6f328SShengzhou Liu #ifdef CONFIG_PCI 60648c6f328SShengzhou Liu /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 60748c6f328SShengzhou Liu #ifdef CONFIG_PCIE1 60848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 60948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 61048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 61148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 61248c6f328SShengzhou Liu #else 61348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 61448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 61548c6f328SShengzhou Liu #endif 61648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 61748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 61848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 61948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 62048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 62148c6f328SShengzhou Liu #else 62248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 62348c6f328SShengzhou Liu #endif 62448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 62548c6f328SShengzhou Liu #endif 62648c6f328SShengzhou Liu 62748c6f328SShengzhou Liu /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 62848c6f328SShengzhou Liu #ifdef CONFIG_PCIE2 62948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 63048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 63148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 63248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 63348c6f328SShengzhou Liu #else 63448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 63548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 63648c6f328SShengzhou Liu #endif 63748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 63848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 63948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 64048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 64148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 64248c6f328SShengzhou Liu #else 64348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 64448c6f328SShengzhou Liu #endif 64548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 64648c6f328SShengzhou Liu #endif 64748c6f328SShengzhou Liu 64848c6f328SShengzhou Liu /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 64948c6f328SShengzhou Liu #ifdef CONFIG_PCIE3 65048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 65148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 65248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 65348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 65448c6f328SShengzhou Liu #else 65548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 65648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 65748c6f328SShengzhou Liu #endif 65848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 65948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 66048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 66148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 66248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 66348c6f328SShengzhou Liu #else 66448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 66548c6f328SShengzhou Liu #endif 66648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 66748c6f328SShengzhou Liu #endif 66848c6f328SShengzhou Liu 66948c6f328SShengzhou Liu /* controller 4, Base address 203000, to be removed */ 67048c6f328SShengzhou Liu #ifdef CONFIG_PCIE4 67148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 67248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 67348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 67448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 67548c6f328SShengzhou Liu #else 67648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 67748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 67848c6f328SShengzhou Liu #endif 67948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 68048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 68148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 68248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 68348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 68448c6f328SShengzhou Liu #else 68548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 68648c6f328SShengzhou Liu #endif 68748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 68848c6f328SShengzhou Liu #endif 68948c6f328SShengzhou Liu 69048c6f328SShengzhou Liu #define CONFIG_PCI_PNP /* do pci plug-and-play */ 69148c6f328SShengzhou Liu #define CONFIG_E1000 69248c6f328SShengzhou Liu #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 69348c6f328SShengzhou Liu #define CONFIG_DOS_PARTITION 69448c6f328SShengzhou Liu #endif /* CONFIG_PCI */ 69548c6f328SShengzhou Liu 69648c6f328SShengzhou Liu /* 69748c6f328SShengzhou Liu * USB 69848c6f328SShengzhou Liu */ 69948c6f328SShengzhou Liu #define CONFIG_HAS_FSL_DR_USB 70048c6f328SShengzhou Liu 70148c6f328SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 70248c6f328SShengzhou Liu #define CONFIG_USB_EHCI 70348c6f328SShengzhou Liu #define CONFIG_CMD_USB 70448c6f328SShengzhou Liu #define CONFIG_USB_STORAGE 70548c6f328SShengzhou Liu #define CONFIG_USB_EHCI_FSL 70648c6f328SShengzhou Liu #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 70748c6f328SShengzhou Liu #define CONFIG_CMD_EXT2 70848c6f328SShengzhou Liu #endif 70948c6f328SShengzhou Liu 71048c6f328SShengzhou Liu /* 71148c6f328SShengzhou Liu * SDHC 71248c6f328SShengzhou Liu */ 71348c6f328SShengzhou Liu #define CONFIG_MMC 71448c6f328SShengzhou Liu #ifdef CONFIG_MMC 71548c6f328SShengzhou Liu #define CONFIG_FSL_ESDHC 71648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 71748c6f328SShengzhou Liu #define CONFIG_CMD_MMC 71848c6f328SShengzhou Liu #define CONFIG_GENERIC_MMC 71948c6f328SShengzhou Liu #define CONFIG_CMD_EXT2 72048c6f328SShengzhou Liu #define CONFIG_CMD_FAT 72148c6f328SShengzhou Liu #define CONFIG_DOS_PARTITION 72248c6f328SShengzhou Liu #endif 72348c6f328SShengzhou Liu 72448c6f328SShengzhou Liu /* Qman/Bman */ 72548c6f328SShengzhou Liu #ifndef CONFIG_NOBQFMAN 72648c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 7272a8b3422SJeffrey Ladouceur #define CONFIG_SYS_BMAN_NUM_PORTALS 10 72848c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 72948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 73048c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 73148c6f328SShengzhou Liu #else 73248c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 73348c6f328SShengzhou Liu #endif 73448c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 7353fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 7363fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 7373fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 7383fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 7393fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 7403fa66db4SJeffrey Ladouceur CONFIG_SYS_BMAN_CENA_SIZE) 7413fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 7423fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 7432a8b3422SJeffrey Ladouceur #define CONFIG_SYS_QMAN_NUM_PORTALS 10 74448c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 74548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 74648c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 74748c6f328SShengzhou Liu #else 74848c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 74948c6f328SShengzhou Liu #endif 75048c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 7513fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 7523fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 7533fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 7543fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 7553fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 7563fa66db4SJeffrey Ladouceur CONFIG_SYS_QMAN_CENA_SIZE) 7573fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 7583fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 75948c6f328SShengzhou Liu 76048c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_FMAN 76148c6f328SShengzhou Liu 76248c6f328SShengzhou Liu #define CONFIG_QE 76348c6f328SShengzhou Liu #define CONFIG_U_QE 76448c6f328SShengzhou Liu /* Default address of microcode for the Linux FMan driver */ 76548c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 76648c6f328SShengzhou Liu /* 76748c6f328SShengzhou Liu * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 76848c6f328SShengzhou Liu * env, so we got 0x110000. 76948c6f328SShengzhou Liu */ 77048c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_IN_SPIFLASH 77148c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 77248c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0x130000 77348c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 77448c6f328SShengzhou Liu /* 77548c6f328SShengzhou Liu * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 77648c6f328SShengzhou Liu * about 1MB (2048 blocks), Env is stored after the image, and the env size is 77748c6f328SShengzhou Liu * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 77848c6f328SShengzhou Liu */ 77948c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 78048c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 78148c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 78248c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 78348c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 784e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 78548c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 78648c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 787e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 788e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 789e8a7f1c3SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 790e8a7f1c3SShengzhou Liu #endif 79148c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 79248c6f328SShengzhou Liu /* 79348c6f328SShengzhou Liu * Slave has no ucode locally, it can fetch this from remote. When implementing 79448c6f328SShengzhou Liu * in two corenet boards, slave's ucode could be stored in master's memory 79548c6f328SShengzhou Liu * space, the address can be mapped from slave TLB->slave LAW-> 79648c6f328SShengzhou Liu * slave SRIO or PCIE outbound window->master inbound window-> 79748c6f328SShengzhou Liu * master LAW->the ucode address in master's memory space. 79848c6f328SShengzhou Liu */ 79948c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 80048c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 80148c6f328SShengzhou Liu #else 80248c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 80348c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 80448c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 80548c6f328SShengzhou Liu #endif 80648c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 80748c6f328SShengzhou Liu #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 80848c6f328SShengzhou Liu #endif /* CONFIG_NOBQFMAN */ 80948c6f328SShengzhou Liu 81048c6f328SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 81148c6f328SShengzhou Liu #define CONFIG_FMAN_ENET 81248c6f328SShengzhou Liu #define CONFIG_PHYLIB_10G 81348c6f328SShengzhou Liu #define CONFIG_PHY_REALTEK 814e26416a3SShengzhou Liu #define CONFIG_PHY_AQUANTIA 815e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 81648c6f328SShengzhou Liu #define RGMII_PHY1_ADDR 0x2 81748c6f328SShengzhou Liu #define RGMII_PHY2_ADDR 0x6 818e8a7f1c3SShengzhou Liu #define SGMII_AQR_PHY_ADDR 0x2 81948c6f328SShengzhou Liu #define FM1_10GEC1_PHY_ADDR 0x1 820e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1023RDB) 821e8a7f1c3SShengzhou Liu #define RGMII_PHY1_ADDR 0x1 822e8a7f1c3SShengzhou Liu #define SGMII_RTK_PHY_ADDR 0x3 823e8a7f1c3SShengzhou Liu #define SGMII_AQR_PHY_ADDR 0x2 824e8a7f1c3SShengzhou Liu #endif 82548c6f328SShengzhou Liu #endif 82648c6f328SShengzhou Liu 82748c6f328SShengzhou Liu #ifdef CONFIG_FMAN_ENET 82848c6f328SShengzhou Liu #define CONFIG_MII /* MII PHY management */ 82948c6f328SShengzhou Liu #define CONFIG_ETHPRIME "FM1@DTSEC4" 83048c6f328SShengzhou Liu #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 83148c6f328SShengzhou Liu #endif 83248c6f328SShengzhou Liu 83348c6f328SShengzhou Liu /* 83448c6f328SShengzhou Liu * Dynamic MTD Partition support with mtdparts 83548c6f328SShengzhou Liu */ 83648c6f328SShengzhou Liu #ifndef CONFIG_SYS_NO_FLASH 83748c6f328SShengzhou Liu #define CONFIG_MTD_DEVICE 83848c6f328SShengzhou Liu #define CONFIG_MTD_PARTITIONS 83948c6f328SShengzhou Liu #define CONFIG_CMD_MTDPARTS 84048c6f328SShengzhou Liu #define CONFIG_FLASH_CFI_MTD 84148c6f328SShengzhou Liu #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 84248c6f328SShengzhou Liu "spi0=spife110000.1" 84348c6f328SShengzhou Liu #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 84448c6f328SShengzhou Liu "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 84548c6f328SShengzhou Liu "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 84648c6f328SShengzhou Liu "1m(uboot),5m(kernel),128k(dtb),-(user)" 84748c6f328SShengzhou Liu #endif 84848c6f328SShengzhou Liu 84948c6f328SShengzhou Liu /* 85048c6f328SShengzhou Liu * Environment 85148c6f328SShengzhou Liu */ 85248c6f328SShengzhou Liu #define CONFIG_LOADS_ECHO /* echo on for serial download */ 85348c6f328SShengzhou Liu #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 85448c6f328SShengzhou Liu 85548c6f328SShengzhou Liu /* 85648c6f328SShengzhou Liu * Command line configuration. 85748c6f328SShengzhou Liu */ 85848c6f328SShengzhou Liu #define CONFIG_CMD_DATE 85948c6f328SShengzhou Liu #define CONFIG_CMD_DHCP 86048c6f328SShengzhou Liu #define CONFIG_CMD_EEPROM 86148c6f328SShengzhou Liu #define CONFIG_CMD_ELF 86248c6f328SShengzhou Liu #define CONFIG_CMD_ERRATA 86348c6f328SShengzhou Liu #define CONFIG_CMD_GREPENV 86448c6f328SShengzhou Liu #define CONFIG_CMD_IRQ 86548c6f328SShengzhou Liu #define CONFIG_CMD_I2C 86648c6f328SShengzhou Liu #define CONFIG_CMD_MII 86748c6f328SShengzhou Liu #define CONFIG_CMD_PING 86848c6f328SShengzhou Liu #define CONFIG_CMD_REGINFO 86948c6f328SShengzhou Liu 87048c6f328SShengzhou Liu #ifdef CONFIG_PCI 87148c6f328SShengzhou Liu #define CONFIG_CMD_PCI 87248c6f328SShengzhou Liu #endif 87348c6f328SShengzhou Liu 87448c6f328SShengzhou Liu /* 87548c6f328SShengzhou Liu * Miscellaneous configurable options 87648c6f328SShengzhou Liu */ 87748c6f328SShengzhou Liu #define CONFIG_SYS_LONGHELP /* undef to save memory */ 87848c6f328SShengzhou Liu #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 87948c6f328SShengzhou Liu #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 88048c6f328SShengzhou Liu #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 88148c6f328SShengzhou Liu #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 88248c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 88348c6f328SShengzhou Liu #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 88448c6f328SShengzhou Liu #else 88548c6f328SShengzhou Liu #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 88648c6f328SShengzhou Liu #endif 88748c6f328SShengzhou Liu #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 88848c6f328SShengzhou Liu #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 88948c6f328SShengzhou Liu #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 89048c6f328SShengzhou Liu 89148c6f328SShengzhou Liu /* 89248c6f328SShengzhou Liu * For booting Linux, the board info and command line data 89348c6f328SShengzhou Liu * have to be in the first 64 MB of memory, since this is 89448c6f328SShengzhou Liu * the maximum mapped by the Linux kernel during initialization. 89548c6f328SShengzhou Liu */ 89648c6f328SShengzhou Liu #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 89748c6f328SShengzhou Liu #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 89848c6f328SShengzhou Liu 89948c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 90048c6f328SShengzhou Liu #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 90148c6f328SShengzhou Liu #endif 90248c6f328SShengzhou Liu 90348c6f328SShengzhou Liu /* 90448c6f328SShengzhou Liu * Environment Configuration 90548c6f328SShengzhou Liu */ 90648c6f328SShengzhou Liu #define CONFIG_ROOTPATH "/opt/nfsroot" 90748c6f328SShengzhou Liu #define CONFIG_BOOTFILE "uImage" 908e8a7f1c3SShengzhou Liu #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 90948c6f328SShengzhou Liu #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 91048c6f328SShengzhou Liu #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 91148c6f328SShengzhou Liu #define CONFIG_BAUDRATE 115200 91248c6f328SShengzhou Liu #define __USB_PHY_TYPE utmi 91348c6f328SShengzhou Liu 91448c6f328SShengzhou Liu #ifdef CONFIG_PPC_T1024 915e8a7f1c3SShengzhou Liu #define CONFIG_BOARDNAME t1024rdb 916e8a7f1c3SShengzhou Liu #define BANK_INTLV cs0_cs1 91748c6f328SShengzhou Liu #else 918e8a7f1c3SShengzhou Liu #define CONFIG_BOARDNAME t1023rdb 919e8a7f1c3SShengzhou Liu #define BANK_INTLV null 92048c6f328SShengzhou Liu #endif 92148c6f328SShengzhou Liu 92248c6f328SShengzhou Liu #define CONFIG_EXTRA_ENV_SETTINGS \ 92348c6f328SShengzhou Liu "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 924e8a7f1c3SShengzhou Liu "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 92548c6f328SShengzhou Liu "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 92648c6f328SShengzhou Liu "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 92748c6f328SShengzhou Liu "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 92848c6f328SShengzhou Liu __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 92948c6f328SShengzhou Liu "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 93048c6f328SShengzhou Liu "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 93148c6f328SShengzhou Liu "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 93248c6f328SShengzhou Liu "netdev=eth0\0" \ 93348c6f328SShengzhou Liu "tftpflash=tftpboot $loadaddr $uboot && " \ 93448c6f328SShengzhou Liu "protect off $ubootaddr +$filesize && " \ 93548c6f328SShengzhou Liu "erase $ubootaddr +$filesize && " \ 93648c6f328SShengzhou Liu "cp.b $loadaddr $ubootaddr $filesize && " \ 93748c6f328SShengzhou Liu "protect on $ubootaddr +$filesize && " \ 93848c6f328SShengzhou Liu "cmp.b $loadaddr $ubootaddr $filesize\0" \ 93948c6f328SShengzhou Liu "consoledev=ttyS0\0" \ 94048c6f328SShengzhou Liu "ramdiskaddr=2000000\0" \ 94148c6f328SShengzhou Liu "fdtaddr=c00000\0" \ 94248c6f328SShengzhou Liu "bdev=sda3\0" 94348c6f328SShengzhou Liu 94448c6f328SShengzhou Liu #define CONFIG_LINUX \ 94548c6f328SShengzhou Liu "setenv bootargs root=/dev/ram rw " \ 94648c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 94748c6f328SShengzhou Liu "setenv ramdiskaddr 0x02000000;" \ 94848c6f328SShengzhou Liu "setenv fdtaddr 0x00c00000;" \ 94948c6f328SShengzhou Liu "setenv loadaddr 0x1000000;" \ 95048c6f328SShengzhou Liu "bootm $loadaddr $ramdiskaddr $fdtaddr" 95148c6f328SShengzhou Liu 95248c6f328SShengzhou Liu 95348c6f328SShengzhou Liu #define CONFIG_NFSBOOTCOMMAND \ 95448c6f328SShengzhou Liu "setenv bootargs root=/dev/nfs rw " \ 95548c6f328SShengzhou Liu "nfsroot=$serverip:$rootpath " \ 95648c6f328SShengzhou Liu "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 95748c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 95848c6f328SShengzhou Liu "tftp $loadaddr $bootfile;" \ 95948c6f328SShengzhou Liu "tftp $fdtaddr $fdtfile;" \ 96048c6f328SShengzhou Liu "bootm $loadaddr - $fdtaddr" 96148c6f328SShengzhou Liu 96248c6f328SShengzhou Liu #define CONFIG_BOOTCOMMAND CONFIG_LINUX 96348c6f328SShengzhou Liu 96448c6f328SShengzhou Liu #ifdef CONFIG_SECURE_BOOT 96548c6f328SShengzhou Liu #include <asm/fsl_secure_boot.h> 96648c6f328SShengzhou Liu #endif 96748c6f328SShengzhou Liu 96848c6f328SShengzhou Liu #endif /* __T1024RDB_H */ 969