1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 QDS board configuration file 8 */ 9 10 #ifndef __T1024QDS_H 11 #define __T1024QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 #define CONFIG_DEEP_SLEEP 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 33 #define CONFIG_SPL_PAD_TO 0x40000 34 #define CONFIG_SPL_MAX_SIZE 0x28000 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SPL_SKIP_RELOCATE 39 #define CONFIG_SPL_COMMON_INIT_DDR 40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 50 #define CONFIG_SPL_NAND_BOOT 51 #endif 52 53 #ifdef CONFIG_SPIFLASH 54 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 55 #define CONFIG_SPL_SPI_FLASH_MINIMAL 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 61 #ifndef CONFIG_SPL_BUILD 62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 63 #endif 64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 65 #define CONFIG_SPL_SPI_BOOT 66 #endif 67 68 #ifdef CONFIG_SDCARD 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 70 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 72 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 73 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 75 #ifndef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 77 #endif 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 79 #define CONFIG_SPL_MMC_BOOT 80 #endif 81 82 #endif /* CONFIG_RAMBOOT_PBL */ 83 84 #ifndef CONFIG_RESET_VECTOR_ADDRESS 85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 86 #endif 87 88 /* PCIe Boot - Master */ 89 #define CONFIG_SRIO_PCIE_BOOT_MASTER 90 /* 91 * for slave u-boot IMAGE instored in master memory space, 92 * PHYS must be aligned based on the SIZE 93 */ 94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 95 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 96 #ifdef CONFIG_PHYS_64BIT 97 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 99 #else 100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 102 #endif 103 /* 104 * for slave UCODE and ENV instored in master memory space, 105 * PHYS must be aligned based on the SIZE 106 */ 107 #ifdef CONFIG_PHYS_64BIT 108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 109 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 110 #else 111 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 113 #endif 114 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 115 /* slave core release by master*/ 116 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 117 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 118 119 /* PCIe Boot - Slave */ 120 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 121 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 122 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 123 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 124 /* Set 1M boot space for PCIe boot */ 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 126 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 127 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 128 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 129 #endif 130 131 #if defined(CONFIG_SPIFLASH) 132 #define CONFIG_ENV_SPI_BUS 0 133 #define CONFIG_ENV_SPI_CS 0 134 #define CONFIG_ENV_SPI_MAX_HZ 10000000 135 #define CONFIG_ENV_SPI_MODE 0 136 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 137 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 138 #define CONFIG_ENV_SECT_SIZE 0x10000 139 #elif defined(CONFIG_SDCARD) 140 #define CONFIG_SYS_MMC_ENV_DEV 0 141 #define CONFIG_ENV_SIZE 0x2000 142 #define CONFIG_ENV_OFFSET (512 * 0x800) 143 #elif defined(CONFIG_NAND) 144 #define CONFIG_ENV_SIZE 0x2000 145 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 146 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 147 #define CONFIG_ENV_ADDR 0xffe20000 148 #define CONFIG_ENV_SIZE 0x2000 149 #elif defined(CONFIG_ENV_IS_NOWHERE) 150 #define CONFIG_ENV_SIZE 0x2000 151 #else 152 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 153 #define CONFIG_ENV_SIZE 0x2000 154 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 155 #endif 156 157 #ifndef __ASSEMBLY__ 158 unsigned long get_board_sys_clk(void); 159 unsigned long get_board_ddr_clk(void); 160 #endif 161 162 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 163 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 164 165 /* 166 * These can be toggled for performance analysis, otherwise use default. 167 */ 168 #define CONFIG_SYS_CACHE_STASHING 169 #define CONFIG_BACKSIDE_L2_CACHE 170 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 171 #define CONFIG_BTB /* toggle branch predition */ 172 #define CONFIG_DDR_ECC 173 #ifdef CONFIG_DDR_ECC 174 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 175 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 176 #endif 177 178 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 179 #define CONFIG_SYS_MEMTEST_END 0x00400000 180 181 /* 182 * Config the L3 Cache as L3 SRAM 183 */ 184 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 185 #define CONFIG_SYS_L3_SIZE (256 << 10) 186 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 187 #ifdef CONFIG_RAMBOOT_PBL 188 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 189 #endif 190 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 191 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 192 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 193 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_DCSRBAR 0xf0000000 196 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 197 #endif 198 199 /* EEPROM */ 200 #define CONFIG_ID_EEPROM 201 #define CONFIG_SYS_I2C_EEPROM_NXID 202 #define CONFIG_SYS_EEPROM_BUS_NUM 0 203 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 204 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 205 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 207 208 /* 209 * DDR Setup 210 */ 211 #define CONFIG_VERY_BIG_RAM 212 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 213 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 214 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 215 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 216 #define CONFIG_DDR_SPD 217 218 #define CONFIG_SYS_SPD_BUS_NUM 0 219 #define SPD_EEPROM_ADDRESS 0x51 220 221 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 222 223 /* 224 * IFC Definitions 225 */ 226 #define CONFIG_SYS_FLASH_BASE 0xe0000000 227 #ifdef CONFIG_PHYS_64BIT 228 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 229 #else 230 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 231 #endif 232 233 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 234 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 235 + 0x8000000) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 240 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 241 CSPR_PORT_SIZE_16 | \ 242 CSPR_MSEL_NOR | \ 243 CSPR_V) 244 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 245 /* NOR Flash Timing Params */ 246 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 247 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 248 FTIM0_NOR_TEADC(0x5) | \ 249 FTIM0_NOR_TEAHC(0x5)) 250 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 251 FTIM1_NOR_TRAD_NOR(0x1A) |\ 252 FTIM1_NOR_TSEQRAD_NOR(0x13)) 253 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 254 FTIM2_NOR_TCH(0x4) | \ 255 FTIM2_NOR_TWPH(0x0E) | \ 256 FTIM2_NOR_TWP(0x1c)) 257 #define CONFIG_SYS_NOR_FTIM3 0x0 258 259 #define CONFIG_SYS_FLASH_QUIET_TEST 260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 261 262 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 263 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 266 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 269 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 270 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 271 #define QIXIS_BASE 0xffdf0000 272 #ifdef CONFIG_PHYS_64BIT 273 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 274 #else 275 #define QIXIS_BASE_PHYS QIXIS_BASE 276 #endif 277 #define QIXIS_LBMAP_SWITCH 0x06 278 #define QIXIS_LBMAP_MASK 0x0f 279 #define QIXIS_LBMAP_SHIFT 0 280 #define QIXIS_LBMAP_DFLTBANK 0x00 281 #define QIXIS_LBMAP_ALTBANK 0x04 282 #define QIXIS_RST_CTL_RESET 0x31 283 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 284 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 285 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 286 #define QIXIS_RST_FORCE_MEM 0x01 287 288 #define CONFIG_SYS_CSPR3_EXT (0xf) 289 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 290 | CSPR_PORT_SIZE_8 \ 291 | CSPR_MSEL_GPCM \ 292 | CSPR_V) 293 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 294 #define CONFIG_SYS_CSOR3 0x0 295 /* QIXIS Timing parameters for IFC CS3 */ 296 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 297 FTIM0_GPCM_TEADC(0x0e) | \ 298 FTIM0_GPCM_TEAHC(0x0e)) 299 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 300 FTIM1_GPCM_TRAD(0x3f)) 301 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 302 FTIM2_GPCM_TCH(0x8) | \ 303 FTIM2_GPCM_TWP(0x1f)) 304 #define CONFIG_SYS_CS3_FTIM3 0x0 305 306 #define CONFIG_NAND_FSL_IFC 307 #define CONFIG_SYS_NAND_BASE 0xff800000 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 310 #else 311 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 312 #endif 313 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 314 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 315 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 316 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 317 | CSPR_V) 318 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 319 320 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 321 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 322 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 323 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 324 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 325 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 326 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 327 328 #define CONFIG_SYS_NAND_ONFI_DETECTION 329 330 /* ONFI NAND Flash mode0 Timing Params */ 331 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 332 FTIM0_NAND_TWP(0x18) | \ 333 FTIM0_NAND_TWCHT(0x07) | \ 334 FTIM0_NAND_TWH(0x0a)) 335 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 336 FTIM1_NAND_TWBE(0x39) | \ 337 FTIM1_NAND_TRR(0x0e) | \ 338 FTIM1_NAND_TRP(0x18)) 339 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 340 FTIM2_NAND_TREH(0x0a) | \ 341 FTIM2_NAND_TWHRE(0x1e)) 342 #define CONFIG_SYS_NAND_FTIM3 0x0 343 344 #define CONFIG_SYS_NAND_DDR_LAW 11 345 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 346 #define CONFIG_SYS_MAX_NAND_DEVICE 1 347 348 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 349 350 #if defined(CONFIG_NAND) 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 375 #else 376 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 377 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 378 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 379 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 380 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 381 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 382 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 383 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 384 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 385 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 386 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 387 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 388 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 389 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 390 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 391 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 392 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 393 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 394 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 395 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 396 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 397 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 398 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 399 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 400 #endif 401 402 #ifdef CONFIG_SPL_BUILD 403 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 404 #else 405 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 406 #endif 407 408 #if defined(CONFIG_RAMBOOT_PBL) 409 #define CONFIG_SYS_RAMBOOT 410 #endif 411 412 #define CONFIG_HWCONFIG 413 414 /* define to use L1 as initial stack */ 415 #define CONFIG_L1_INIT_RAM 416 #define CONFIG_SYS_INIT_RAM_LOCK 417 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 421 /* The assembler doesn't like typecast */ 422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 423 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 424 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 425 #else 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 429 #endif 430 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 431 432 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 433 GENERATED_GBL_DATA_SIZE) 434 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 435 436 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 437 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 438 439 /* Serial Port */ 440 #define CONFIG_SYS_NS16550_SERIAL 441 #define CONFIG_SYS_NS16550_REG_SIZE 1 442 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 443 444 #define CONFIG_SYS_BAUDRATE_TABLE \ 445 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 446 447 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 448 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 449 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 450 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 451 452 /* Video */ 453 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 454 #define CONFIG_FSL_DIU_FB 455 #ifdef CONFIG_FSL_DIU_FB 456 #define CONFIG_FSL_DIU_CH7301 457 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 458 #define CONFIG_VIDEO_LOGO 459 #define CONFIG_VIDEO_BMP_LOGO 460 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 461 /* 462 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 463 * disable empty flash sector detection, which is I/O-intensive. 464 */ 465 #undef CONFIG_SYS_FLASH_EMPTY_INFO 466 #endif 467 #endif 468 469 /* I2C */ 470 #define CONFIG_SYS_I2C 471 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 472 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 473 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 474 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 475 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 476 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 477 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 478 479 #define I2C_MUX_PCA_ADDR 0x77 480 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 481 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 482 #define I2C_RETIMER_ADDR 0x18 483 484 /* I2C bus multiplexer */ 485 #define I2C_MUX_CH_DEFAULT 0x8 486 #define I2C_MUX_CH_DIU 0xC 487 #define I2C_MUX_CH5 0xD 488 #define I2C_MUX_CH7 0xF 489 490 /* LDI/DVI Encoder for display */ 491 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 492 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 493 494 /* 495 * RTC configuration 496 */ 497 #define RTC 498 #define CONFIG_RTC_DS3231 1 499 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 500 501 /* 502 * eSPI - Enhanced SPI 503 */ 504 #define CONFIG_SPI_FLASH_BAR 505 #define CONFIG_SF_DEFAULT_SPEED 10000000 506 #define CONFIG_SF_DEFAULT_MODE 0 507 508 /* 509 * General PCIe 510 * Memory space is mapped 1-1, but I/O space must start from 0. 511 */ 512 #define CONFIG_PCIE1 /* PCIE controller 1 */ 513 #define CONFIG_PCIE2 /* PCIE controller 2 */ 514 #define CONFIG_PCIE3 /* PCIE controller 3 */ 515 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 516 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 517 #define CONFIG_PCI_INDIRECT_BRIDGE 518 519 #ifdef CONFIG_PCI 520 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 521 #ifdef CONFIG_PCIE1 522 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 523 #ifdef CONFIG_PHYS_64BIT 524 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 526 #else 527 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 528 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 529 #endif 530 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 531 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 532 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 533 #ifdef CONFIG_PHYS_64BIT 534 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 535 #else 536 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 537 #endif 538 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 539 #endif 540 541 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 542 #ifdef CONFIG_PCIE2 543 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 544 #ifdef CONFIG_PHYS_64BIT 545 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 546 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 547 #else 548 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 549 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 550 #endif 551 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 552 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 553 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 554 #ifdef CONFIG_PHYS_64BIT 555 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 556 #else 557 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 558 #endif 559 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 560 #endif 561 562 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 563 #ifdef CONFIG_PCIE3 564 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 565 #ifdef CONFIG_PHYS_64BIT 566 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 568 #else 569 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 570 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 571 #endif 572 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 573 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 574 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 575 #ifdef CONFIG_PHYS_64BIT 576 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 577 #else 578 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 579 #endif 580 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 581 #endif 582 583 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 584 #endif /* CONFIG_PCI */ 585 586 /* 587 *SATA 588 */ 589 #define CONFIG_FSL_SATA_V2 590 #ifdef CONFIG_FSL_SATA_V2 591 #define CONFIG_SYS_SATA_MAX_DEVICE 1 592 #define CONFIG_SATA1 593 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 594 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 595 #define CONFIG_LBA48 596 #endif 597 598 /* 599 * USB 600 */ 601 #define CONFIG_HAS_FSL_DR_USB 602 603 #ifdef CONFIG_HAS_FSL_DR_USB 604 #define CONFIG_USB_EHCI_FSL 605 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 606 #endif 607 608 /* 609 * SDHC 610 */ 611 #ifdef CONFIG_MMC 612 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 613 #endif 614 615 /* Qman/Bman */ 616 #ifndef CONFIG_NOBQFMAN 617 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 618 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 621 #else 622 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 623 #endif 624 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 625 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 626 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 627 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 628 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 629 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 630 CONFIG_SYS_BMAN_CENA_SIZE) 631 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 632 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 633 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 634 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 635 #ifdef CONFIG_PHYS_64BIT 636 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 637 #else 638 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 639 #endif 640 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 641 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 642 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 643 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 644 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 645 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 646 CONFIG_SYS_QMAN_CENA_SIZE) 647 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 648 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 649 650 #define CONFIG_SYS_DPAA_FMAN 651 652 #define CONFIG_QE 653 /* Default address of microcode for the Linux FMan driver */ 654 #if defined(CONFIG_SPIFLASH) 655 /* 656 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 657 * env, so we got 0x110000. 658 */ 659 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 660 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 661 #define CONFIG_SYS_QE_FW_ADDR 0x130000 662 #elif defined(CONFIG_SDCARD) 663 /* 664 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 665 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 666 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 667 */ 668 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 669 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 670 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 671 #elif defined(CONFIG_NAND) 672 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 673 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 674 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 675 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 676 /* 677 * Slave has no ucode locally, it can fetch this from remote. When implementing 678 * in two corenet boards, slave's ucode could be stored in master's memory 679 * space, the address can be mapped from slave TLB->slave LAW-> 680 * slave SRIO or PCIE outbound window->master inbound window-> 681 * master LAW->the ucode address in master's memory space. 682 */ 683 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 684 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 685 #else 686 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 687 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 688 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 689 #endif 690 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 691 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 692 #endif /* CONFIG_NOBQFMAN */ 693 694 #ifdef CONFIG_SYS_DPAA_FMAN 695 #define CONFIG_FMAN_ENET 696 #define CONFIG_PHYLIB_10G 697 #define CONFIG_PHY_VITESSE 698 #define CONFIG_PHY_REALTEK 699 #define CONFIG_PHY_TERANETICS 700 #define RGMII_PHY1_ADDR 0x1 701 #define RGMII_PHY2_ADDR 0x2 702 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 703 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 704 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 705 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 706 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 707 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 708 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 709 #endif 710 711 #ifdef CONFIG_FMAN_ENET 712 #define CONFIG_ETHPRIME "FM1@DTSEC4" 713 #endif 714 715 /* 716 * Dynamic MTD Partition support with mtdparts 717 */ 718 719 /* 720 * Environment 721 */ 722 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 723 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 724 725 /* 726 * Miscellaneous configurable options 727 */ 728 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 729 730 /* 731 * For booting Linux, the board info and command line data 732 * have to be in the first 64 MB of memory, since this is 733 * the maximum mapped by the Linux kernel during initialization. 734 */ 735 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 736 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 737 738 #ifdef CONFIG_CMD_KGDB 739 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 740 #endif 741 742 /* 743 * Environment Configuration 744 */ 745 #define CONFIG_ROOTPATH "/opt/nfsroot" 746 #define CONFIG_BOOTFILE "uImage" 747 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 748 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 749 #define __USB_PHY_TYPE utmi 750 751 #define CONFIG_EXTRA_ENV_SETTINGS \ 752 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 753 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 754 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 755 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 756 "fdtfile=t1024qds/t1024qds.dtb\0" \ 757 "netdev=eth0\0" \ 758 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 759 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 760 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 761 "tftpflash=tftpboot $loadaddr $uboot && " \ 762 "protect off $ubootaddr +$filesize && " \ 763 "erase $ubootaddr +$filesize && " \ 764 "cp.b $loadaddr $ubootaddr $filesize && " \ 765 "protect on $ubootaddr +$filesize && " \ 766 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 767 "consoledev=ttyS0\0" \ 768 "ramdiskaddr=2000000\0" \ 769 "fdtaddr=d00000\0" \ 770 "bdev=sda3\0" 771 772 #define CONFIG_LINUX \ 773 "setenv bootargs root=/dev/ram rw " \ 774 "console=$consoledev,$baudrate $othbootargs;" \ 775 "setenv ramdiskaddr 0x02000000;" \ 776 "setenv fdtaddr 0x00c00000;" \ 777 "setenv loadaddr 0x1000000;" \ 778 "bootm $loadaddr $ramdiskaddr $fdtaddr" 779 780 #define CONFIG_NFSBOOTCOMMAND \ 781 "setenv bootargs root=/dev/nfs rw " \ 782 "nfsroot=$serverip:$rootpath " \ 783 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr - $fdtaddr" 788 789 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 790 791 #include <asm/fsl_secure_boot.h> 792 793 #endif /* __T1024QDS_H */ 794