1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 #define CONFIG_DEEP_SLEEP 30 31 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 32 33 #ifdef CONFIG_RAMBOOT_PBL 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 35 #define CONFIG_SPL_FLUSH_IMAGE 36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 37 #define CONFIG_SYS_TEXT_BASE 0x00201000 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_SKIP_RELOCATE 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 47 #endif 48 49 #ifdef CONFIG_NAND 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 56 #define CONFIG_SPL_NAND_BOOT 57 #endif 58 59 #ifdef CONFIG_SPIFLASH 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 61 #define CONFIG_SPL_SPI_FLASH_MINIMAL 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 67 #ifndef CONFIG_SPL_BUILD 68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 69 #endif 70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 71 #define CONFIG_SPL_SPI_BOOT 72 #endif 73 74 #ifdef CONFIG_SDCARD 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 76 #define CONFIG_SPL_MMC_MINIMAL 77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 79 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 86 #define CONFIG_SPL_MMC_BOOT 87 #endif 88 89 #endif /* CONFIG_RAMBOOT_PBL */ 90 91 #ifndef CONFIG_SYS_TEXT_BASE 92 #define CONFIG_SYS_TEXT_BASE 0xeff40000 93 #endif 94 95 #ifndef CONFIG_RESET_VECTOR_ADDRESS 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 97 #endif 98 99 #ifdef CONFIG_MTD_NOR_FLASH 100 #define CONFIG_FLASH_CFI_DRIVER 101 #define CONFIG_SYS_FLASH_CFI 102 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 103 #endif 104 105 /* PCIe Boot - Master */ 106 #define CONFIG_SRIO_PCIE_BOOT_MASTER 107 /* 108 * for slave u-boot IMAGE instored in master memory space, 109 * PHYS must be aligned based on the SIZE 110 */ 111 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 113 #ifdef CONFIG_PHYS_64BIT 114 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 116 #else 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 119 #endif 120 /* 121 * for slave UCODE and ENV instored in master memory space, 122 * PHYS must be aligned based on the SIZE 123 */ 124 #ifdef CONFIG_PHYS_64BIT 125 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 127 #else 128 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 130 #endif 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 132 /* slave core release by master*/ 133 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 134 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 135 136 /* PCIe Boot - Slave */ 137 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 138 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 139 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 140 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 141 /* Set 1M boot space for PCIe boot */ 142 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 144 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 145 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 146 #endif 147 148 #if defined(CONFIG_SPIFLASH) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_ENV_IS_IN_SPI_FLASH 151 #define CONFIG_ENV_SPI_BUS 0 152 #define CONFIG_ENV_SPI_CS 0 153 #define CONFIG_ENV_SPI_MAX_HZ 10000000 154 #define CONFIG_ENV_SPI_MODE 0 155 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 156 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 157 #define CONFIG_ENV_SECT_SIZE 0x10000 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_MMC 161 #define CONFIG_SYS_MMC_ENV_DEV 0 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (512 * 0x800) 164 #elif defined(CONFIG_NAND) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_NAND 167 #define CONFIG_ENV_SIZE 0x2000 168 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 170 #define CONFIG_ENV_IS_IN_REMOTE 171 #define CONFIG_ENV_ADDR 0xffe20000 172 #define CONFIG_ENV_SIZE 0x2000 173 #elif defined(CONFIG_ENV_IS_NOWHERE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #else 176 #define CONFIG_ENV_IS_IN_FLASH 177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 180 #endif 181 182 #ifndef __ASSEMBLY__ 183 unsigned long get_board_sys_clk(void); 184 unsigned long get_board_ddr_clk(void); 185 #endif 186 187 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 188 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 189 190 /* 191 * These can be toggled for performance analysis, otherwise use default. 192 */ 193 #define CONFIG_SYS_CACHE_STASHING 194 #define CONFIG_BACKSIDE_L2_CACHE 195 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 196 #define CONFIG_BTB /* toggle branch predition */ 197 #define CONFIG_DDR_ECC 198 #ifdef CONFIG_DDR_ECC 199 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 200 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 201 #endif 202 203 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 204 #define CONFIG_SYS_MEMTEST_END 0x00400000 205 #define CONFIG_SYS_ALT_MEMTEST 206 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 207 208 /* 209 * Config the L3 Cache as L3 SRAM 210 */ 211 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 212 #define CONFIG_SYS_L3_SIZE (256 << 10) 213 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 214 #ifdef CONFIG_RAMBOOT_PBL 215 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 216 #endif 217 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 218 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 219 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 220 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 221 222 #ifdef CONFIG_PHYS_64BIT 223 #define CONFIG_SYS_DCSRBAR 0xf0000000 224 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 225 #endif 226 227 /* EEPROM */ 228 #define CONFIG_ID_EEPROM 229 #define CONFIG_SYS_I2C_EEPROM_NXID 230 #define CONFIG_SYS_EEPROM_BUS_NUM 0 231 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 235 236 /* 237 * DDR Setup 238 */ 239 #define CONFIG_VERY_BIG_RAM 240 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 241 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 242 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 243 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 244 #define CONFIG_DDR_SPD 245 246 #define CONFIG_SYS_SPD_BUS_NUM 0 247 #define SPD_EEPROM_ADDRESS 0x51 248 249 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 250 251 /* 252 * IFC Definitions 253 */ 254 #define CONFIG_SYS_FLASH_BASE 0xe0000000 255 #ifdef CONFIG_PHYS_64BIT 256 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 257 #else 258 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 259 #endif 260 261 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 262 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 263 + 0x8000000) | \ 264 CSPR_PORT_SIZE_16 | \ 265 CSPR_MSEL_NOR | \ 266 CSPR_V) 267 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 268 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 269 CSPR_PORT_SIZE_16 | \ 270 CSPR_MSEL_NOR | \ 271 CSPR_V) 272 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 273 /* NOR Flash Timing Params */ 274 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 275 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 276 FTIM0_NOR_TEADC(0x5) | \ 277 FTIM0_NOR_TEAHC(0x5)) 278 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 279 FTIM1_NOR_TRAD_NOR(0x1A) |\ 280 FTIM1_NOR_TSEQRAD_NOR(0x13)) 281 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 282 FTIM2_NOR_TCH(0x4) | \ 283 FTIM2_NOR_TWPH(0x0E) | \ 284 FTIM2_NOR_TWP(0x1c)) 285 #define CONFIG_SYS_NOR_FTIM3 0x0 286 287 #define CONFIG_SYS_FLASH_QUIET_TEST 288 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 289 290 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 291 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 292 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 293 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 294 295 #define CONFIG_SYS_FLASH_EMPTY_INFO 296 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 297 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 298 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 299 #define QIXIS_BASE 0xffdf0000 300 #ifdef CONFIG_PHYS_64BIT 301 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 302 #else 303 #define QIXIS_BASE_PHYS QIXIS_BASE 304 #endif 305 #define QIXIS_LBMAP_SWITCH 0x06 306 #define QIXIS_LBMAP_MASK 0x0f 307 #define QIXIS_LBMAP_SHIFT 0 308 #define QIXIS_LBMAP_DFLTBANK 0x00 309 #define QIXIS_LBMAP_ALTBANK 0x04 310 #define QIXIS_RST_CTL_RESET 0x31 311 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 312 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 313 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 314 #define QIXIS_RST_FORCE_MEM 0x01 315 316 #define CONFIG_SYS_CSPR3_EXT (0xf) 317 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 318 | CSPR_PORT_SIZE_8 \ 319 | CSPR_MSEL_GPCM \ 320 | CSPR_V) 321 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 322 #define CONFIG_SYS_CSOR3 0x0 323 /* QIXIS Timing parameters for IFC CS3 */ 324 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 325 FTIM0_GPCM_TEADC(0x0e) | \ 326 FTIM0_GPCM_TEAHC(0x0e)) 327 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 328 FTIM1_GPCM_TRAD(0x3f)) 329 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 330 FTIM2_GPCM_TCH(0x8) | \ 331 FTIM2_GPCM_TWP(0x1f)) 332 #define CONFIG_SYS_CS3_FTIM3 0x0 333 334 #define CONFIG_NAND_FSL_IFC 335 #define CONFIG_SYS_NAND_BASE 0xff800000 336 #ifdef CONFIG_PHYS_64BIT 337 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 338 #else 339 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 340 #endif 341 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 342 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 343 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 344 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 345 | CSPR_V) 346 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 347 348 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 349 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 350 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 351 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 352 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 353 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 354 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 355 356 #define CONFIG_SYS_NAND_ONFI_DETECTION 357 358 /* ONFI NAND Flash mode0 Timing Params */ 359 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 360 FTIM0_NAND_TWP(0x18) | \ 361 FTIM0_NAND_TWCHT(0x07) | \ 362 FTIM0_NAND_TWH(0x0a)) 363 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 364 FTIM1_NAND_TWBE(0x39) | \ 365 FTIM1_NAND_TRR(0x0e) | \ 366 FTIM1_NAND_TRP(0x18)) 367 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 368 FTIM2_NAND_TREH(0x0a) | \ 369 FTIM2_NAND_TWHRE(0x1e)) 370 #define CONFIG_SYS_NAND_FTIM3 0x0 371 372 #define CONFIG_SYS_NAND_DDR_LAW 11 373 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 374 #define CONFIG_SYS_MAX_NAND_DEVICE 1 375 #define CONFIG_CMD_NAND 376 377 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 378 379 #if defined(CONFIG_NAND) 380 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 381 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 382 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 383 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 384 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 385 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 386 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 387 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 388 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 389 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 390 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 391 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 392 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 393 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 394 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 395 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 396 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 397 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 398 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 399 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 400 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 401 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 402 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 403 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 404 #else 405 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 406 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 407 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 421 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 422 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 423 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 424 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 425 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 426 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 427 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 428 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 429 #endif 430 431 #ifdef CONFIG_SPL_BUILD 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 433 #else 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 435 #endif 436 437 #if defined(CONFIG_RAMBOOT_PBL) 438 #define CONFIG_SYS_RAMBOOT 439 #endif 440 441 #define CONFIG_BOARD_EARLY_INIT_R 442 #define CONFIG_MISC_INIT_R 443 444 #define CONFIG_HWCONFIG 445 446 /* define to use L1 as initial stack */ 447 #define CONFIG_L1_INIT_RAM 448 #define CONFIG_SYS_INIT_RAM_LOCK 449 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 453 /* The assembler doesn't like typecast */ 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 455 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 456 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 457 #else 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 461 #endif 462 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 463 464 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 465 GENERATED_GBL_DATA_SIZE) 466 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 467 468 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 469 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 470 471 /* Serial Port */ 472 #define CONFIG_CONS_INDEX 1 473 #define CONFIG_SYS_NS16550_SERIAL 474 #define CONFIG_SYS_NS16550_REG_SIZE 1 475 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 476 477 #define CONFIG_SYS_BAUDRATE_TABLE \ 478 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 479 480 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 481 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 482 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 483 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 484 485 /* Video */ 486 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 487 #define CONFIG_FSL_DIU_FB 488 #ifdef CONFIG_FSL_DIU_FB 489 #define CONFIG_FSL_DIU_CH7301 490 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 491 #define CONFIG_CMD_BMP 492 #define CONFIG_VIDEO_LOGO 493 #define CONFIG_VIDEO_BMP_LOGO 494 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 495 /* 496 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 497 * disable empty flash sector detection, which is I/O-intensive. 498 */ 499 #undef CONFIG_SYS_FLASH_EMPTY_INFO 500 #endif 501 #endif 502 503 /* I2C */ 504 #define CONFIG_SYS_I2C 505 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 506 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 507 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 508 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 509 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 510 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 511 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 512 513 #define I2C_MUX_PCA_ADDR 0x77 514 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 515 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 516 #define I2C_RETIMER_ADDR 0x18 517 518 /* I2C bus multiplexer */ 519 #define I2C_MUX_CH_DEFAULT 0x8 520 #define I2C_MUX_CH_DIU 0xC 521 #define I2C_MUX_CH5 0xD 522 #define I2C_MUX_CH7 0xF 523 524 /* LDI/DVI Encoder for display */ 525 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 526 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 527 528 /* 529 * RTC configuration 530 */ 531 #define RTC 532 #define CONFIG_RTC_DS3231 1 533 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 534 535 /* 536 * eSPI - Enhanced SPI 537 */ 538 #ifndef CONFIG_SPL_BUILD 539 #endif 540 #define CONFIG_SPI_FLASH_BAR 541 #define CONFIG_SF_DEFAULT_SPEED 10000000 542 #define CONFIG_SF_DEFAULT_MODE 0 543 544 /* 545 * General PCIe 546 * Memory space is mapped 1-1, but I/O space must start from 0. 547 */ 548 #define CONFIG_PCIE1 /* PCIE controller 1 */ 549 #define CONFIG_PCIE2 /* PCIE controller 2 */ 550 #define CONFIG_PCIE3 /* PCIE controller 3 */ 551 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 552 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 553 #define CONFIG_PCI_INDIRECT_BRIDGE 554 555 #ifdef CONFIG_PCI 556 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 557 #ifdef CONFIG_PCIE1 558 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 562 #else 563 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 564 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 565 #endif 566 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 568 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 569 #ifdef CONFIG_PHYS_64BIT 570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 571 #else 572 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 573 #endif 574 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 575 #endif 576 577 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 578 #ifdef CONFIG_PCIE2 579 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 583 #else 584 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 585 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 586 #endif 587 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 589 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 592 #else 593 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 594 #endif 595 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 599 #ifdef CONFIG_PCIE3 600 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 604 #else 605 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 606 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 607 #endif 608 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 610 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 611 #ifdef CONFIG_PHYS_64BIT 612 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 613 #else 614 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 615 #endif 616 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 617 #endif 618 619 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 620 #endif /* CONFIG_PCI */ 621 622 /* 623 *SATA 624 */ 625 #define CONFIG_FSL_SATA_V2 626 #ifdef CONFIG_FSL_SATA_V2 627 #define CONFIG_LIBATA 628 #define CONFIG_FSL_SATA 629 #define CONFIG_SYS_SATA_MAX_DEVICE 1 630 #define CONFIG_SATA1 631 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 632 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 633 #define CONFIG_LBA48 634 #define CONFIG_CMD_SATA 635 #endif 636 637 /* 638 * USB 639 */ 640 #define CONFIG_HAS_FSL_DR_USB 641 642 #ifdef CONFIG_HAS_FSL_DR_USB 643 #define CONFIG_USB_EHCI 644 #define CONFIG_USB_EHCI_FSL 645 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 646 #endif 647 648 /* 649 * SDHC 650 */ 651 #ifdef CONFIG_MMC 652 #define CONFIG_FSL_ESDHC 653 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 654 #endif 655 656 /* Qman/Bman */ 657 #ifndef CONFIG_NOBQFMAN 658 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 659 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 660 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 661 #ifdef CONFIG_PHYS_64BIT 662 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 663 #else 664 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 665 #endif 666 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 667 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 668 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 669 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 670 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 671 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 672 CONFIG_SYS_BMAN_CENA_SIZE) 673 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 674 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 675 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 676 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 677 #ifdef CONFIG_PHYS_64BIT 678 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 679 #else 680 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 681 #endif 682 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 683 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 684 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 685 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 686 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 687 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 688 CONFIG_SYS_QMAN_CENA_SIZE) 689 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 690 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 691 692 #define CONFIG_SYS_DPAA_FMAN 693 694 #define CONFIG_QE 695 #define CONFIG_U_QE 696 /* Default address of microcode for the Linux FMan driver */ 697 #if defined(CONFIG_SPIFLASH) 698 /* 699 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 700 * env, so we got 0x110000. 701 */ 702 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 703 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 704 #define CONFIG_SYS_QE_FW_ADDR 0x130000 705 #elif defined(CONFIG_SDCARD) 706 /* 707 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 708 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 709 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 710 */ 711 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 712 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 713 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 714 #elif defined(CONFIG_NAND) 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 716 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 717 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 718 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 719 /* 720 * Slave has no ucode locally, it can fetch this from remote. When implementing 721 * in two corenet boards, slave's ucode could be stored in master's memory 722 * space, the address can be mapped from slave TLB->slave LAW-> 723 * slave SRIO or PCIE outbound window->master inbound window-> 724 * master LAW->the ucode address in master's memory space. 725 */ 726 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 727 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 728 #else 729 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 730 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 731 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 732 #endif 733 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 734 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 735 #endif /* CONFIG_NOBQFMAN */ 736 737 #ifdef CONFIG_SYS_DPAA_FMAN 738 #define CONFIG_FMAN_ENET 739 #define CONFIG_PHYLIB_10G 740 #define CONFIG_PHY_VITESSE 741 #define CONFIG_PHY_REALTEK 742 #define CONFIG_PHY_TERANETICS 743 #define RGMII_PHY1_ADDR 0x1 744 #define RGMII_PHY2_ADDR 0x2 745 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 746 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 747 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 748 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 749 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 750 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 751 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 752 #endif 753 754 #ifdef CONFIG_FMAN_ENET 755 #define CONFIG_MII /* MII PHY management */ 756 #define CONFIG_ETHPRIME "FM1@DTSEC4" 757 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 758 #endif 759 760 /* 761 * Dynamic MTD Partition support with mtdparts 762 */ 763 #ifdef CONFIG_MTD_NOR_FLASH 764 #define CONFIG_MTD_DEVICE 765 #define CONFIG_MTD_PARTITIONS 766 #define CONFIG_CMD_MTDPARTS 767 #define CONFIG_FLASH_CFI_MTD 768 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 769 "spi0=spife110000.0" 770 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 771 "128k(dtb),96m(fs),-(user);"\ 772 "fff800000.flash:2m(uboot),9m(kernel),"\ 773 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 774 "2m(uboot),9m(kernel),128k(dtb),-(user)" 775 #endif 776 777 /* 778 * Environment 779 */ 780 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 781 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 782 783 /* 784 * Command line configuration. 785 */ 786 #define CONFIG_CMD_DATE 787 #define CONFIG_CMD_EEPROM 788 #define CONFIG_CMD_ERRATA 789 #define CONFIG_CMD_IRQ 790 #define CONFIG_CMD_REGINFO 791 792 #ifdef CONFIG_PCI 793 #define CONFIG_CMD_PCI 794 #endif 795 796 /* 797 * Miscellaneous configurable options 798 */ 799 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 800 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 801 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 802 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 803 #ifdef CONFIG_CMD_KGDB 804 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 805 #else 806 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 807 #endif 808 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 809 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 810 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 811 812 /* 813 * For booting Linux, the board info and command line data 814 * have to be in the first 64 MB of memory, since this is 815 * the maximum mapped by the Linux kernel during initialization. 816 */ 817 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 818 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 819 820 #ifdef CONFIG_CMD_KGDB 821 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 822 #endif 823 824 /* 825 * Environment Configuration 826 */ 827 #define CONFIG_ROOTPATH "/opt/nfsroot" 828 #define CONFIG_BOOTFILE "uImage" 829 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 830 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 831 #define CONFIG_BAUDRATE 115200 832 #define __USB_PHY_TYPE utmi 833 834 #define CONFIG_EXTRA_ENV_SETTINGS \ 835 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 836 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 837 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 838 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 839 "fdtfile=t1024qds/t1024qds.dtb\0" \ 840 "netdev=eth0\0" \ 841 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 842 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 843 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 844 "tftpflash=tftpboot $loadaddr $uboot && " \ 845 "protect off $ubootaddr +$filesize && " \ 846 "erase $ubootaddr +$filesize && " \ 847 "cp.b $loadaddr $ubootaddr $filesize && " \ 848 "protect on $ubootaddr +$filesize && " \ 849 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 850 "consoledev=ttyS0\0" \ 851 "ramdiskaddr=2000000\0" \ 852 "fdtaddr=d00000\0" \ 853 "bdev=sda3\0" 854 855 #define CONFIG_LINUX \ 856 "setenv bootargs root=/dev/ram rw " \ 857 "console=$consoledev,$baudrate $othbootargs;" \ 858 "setenv ramdiskaddr 0x02000000;" \ 859 "setenv fdtaddr 0x00c00000;" \ 860 "setenv loadaddr 0x1000000;" \ 861 "bootm $loadaddr $ramdiskaddr $fdtaddr" 862 863 #define CONFIG_NFSBOOTCOMMAND \ 864 "setenv bootargs root=/dev/nfs rw " \ 865 "nfsroot=$serverip:$rootpath " \ 866 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 867 "console=$consoledev,$baudrate $othbootargs;" \ 868 "tftp $loadaddr $bootfile;" \ 869 "tftp $fdtaddr $fdtfile;" \ 870 "bootm $loadaddr - $fdtaddr" 871 872 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 873 874 /* Hash command with SHA acceleration supported in hardware */ 875 #ifdef CONFIG_FSL_CAAM 876 #define CONFIG_CMD_HASH 877 #define CONFIG_SHA_HW_ACCEL 878 #endif 879 880 #include <asm/fsl_secure_boot.h> 881 882 #endif /* __T1024QDS_H */ 883