1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 #define CONFIG_DEEP_SLEEP 30 31 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 32 33 #ifdef CONFIG_RAMBOOT_PBL 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 35 #define CONFIG_SPL_FLUSH_IMAGE 36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 37 #define CONFIG_SYS_TEXT_BASE 0x00201000 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_SKIP_RELOCATE 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 47 #define CONFIG_SYS_NO_FLASH 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 57 #define CONFIG_SPL_NAND_BOOT 58 #endif 59 60 #ifdef CONFIG_SPIFLASH 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 72 #define CONFIG_SPL_SPI_BOOT 73 #endif 74 75 #ifdef CONFIG_SDCARD 76 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 77 #define CONFIG_SPL_MMC_MINIMAL 78 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 80 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 81 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 87 #define CONFIG_SPL_MMC_BOOT 88 #endif 89 90 #endif /* CONFIG_RAMBOOT_PBL */ 91 92 #ifndef CONFIG_SYS_TEXT_BASE 93 #define CONFIG_SYS_TEXT_BASE 0xeff40000 94 #endif 95 96 #ifndef CONFIG_RESET_VECTOR_ADDRESS 97 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 98 #endif 99 100 #ifndef CONFIG_SYS_NO_FLASH 101 #define CONFIG_FLASH_CFI_DRIVER 102 #define CONFIG_SYS_FLASH_CFI 103 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 104 #endif 105 106 /* PCIe Boot - Master */ 107 #define CONFIG_SRIO_PCIE_BOOT_MASTER 108 /* 109 * for slave u-boot IMAGE instored in master memory space, 110 * PHYS must be aligned based on the SIZE 111 */ 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 114 #ifdef CONFIG_PHYS_64BIT 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 117 #else 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 120 #endif 121 /* 122 * for slave UCODE and ENV instored in master memory space, 123 * PHYS must be aligned based on the SIZE 124 */ 125 #ifdef CONFIG_PHYS_64BIT 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 128 #else 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 131 #endif 132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 133 /* slave core release by master*/ 134 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 135 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 136 137 /* PCIe Boot - Slave */ 138 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 139 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 141 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 142 /* Set 1M boot space for PCIe boot */ 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 145 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 146 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 147 #define CONFIG_SYS_NO_FLASH 148 #endif 149 150 #if defined(CONFIG_SPIFLASH) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_IS_IN_SPI_FLASH 153 #define CONFIG_ENV_SPI_BUS 0 154 #define CONFIG_ENV_SPI_CS 0 155 #define CONFIG_ENV_SPI_MAX_HZ 10000000 156 #define CONFIG_ENV_SPI_MODE 0 157 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 158 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 159 #define CONFIG_ENV_SECT_SIZE 0x10000 160 #elif defined(CONFIG_SDCARD) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_MMC 163 #define CONFIG_SYS_MMC_ENV_DEV 0 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_OFFSET (512 * 0x800) 166 #elif defined(CONFIG_NAND) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_NAND 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 171 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 172 #define CONFIG_ENV_IS_IN_REMOTE 173 #define CONFIG_ENV_ADDR 0xffe20000 174 #define CONFIG_ENV_SIZE 0x2000 175 #elif defined(CONFIG_ENV_IS_NOWHERE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #else 178 #define CONFIG_ENV_IS_IN_FLASH 179 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 180 #define CONFIG_ENV_SIZE 0x2000 181 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 182 #endif 183 184 #ifndef __ASSEMBLY__ 185 unsigned long get_board_sys_clk(void); 186 unsigned long get_board_ddr_clk(void); 187 #endif 188 189 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 190 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 191 192 /* 193 * These can be toggled for performance analysis, otherwise use default. 194 */ 195 #define CONFIG_SYS_CACHE_STASHING 196 #define CONFIG_BACKSIDE_L2_CACHE 197 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 198 #define CONFIG_BTB /* toggle branch predition */ 199 #define CONFIG_DDR_ECC 200 #ifdef CONFIG_DDR_ECC 201 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 202 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 203 #endif 204 205 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 206 #define CONFIG_SYS_MEMTEST_END 0x00400000 207 #define CONFIG_SYS_ALT_MEMTEST 208 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 209 210 /* 211 * Config the L3 Cache as L3 SRAM 212 */ 213 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 214 #define CONFIG_SYS_L3_SIZE (256 << 10) 215 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 216 #ifdef CONFIG_RAMBOOT_PBL 217 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 218 #endif 219 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 220 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 221 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 222 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 223 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_SYS_DCSRBAR 0xf0000000 226 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 227 #endif 228 229 /* EEPROM */ 230 #define CONFIG_ID_EEPROM 231 #define CONFIG_SYS_I2C_EEPROM_NXID 232 #define CONFIG_SYS_EEPROM_BUS_NUM 0 233 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 237 238 /* 239 * DDR Setup 240 */ 241 #define CONFIG_VERY_BIG_RAM 242 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 243 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 244 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 245 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 246 #define CONFIG_DDR_SPD 247 248 #define CONFIG_SYS_SPD_BUS_NUM 0 249 #define SPD_EEPROM_ADDRESS 0x51 250 251 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 252 253 /* 254 * IFC Definitions 255 */ 256 #define CONFIG_SYS_FLASH_BASE 0xe0000000 257 #ifdef CONFIG_PHYS_64BIT 258 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 259 #else 260 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 261 #endif 262 263 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 264 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 265 + 0x8000000) | \ 266 CSPR_PORT_SIZE_16 | \ 267 CSPR_MSEL_NOR | \ 268 CSPR_V) 269 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 270 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 271 CSPR_PORT_SIZE_16 | \ 272 CSPR_MSEL_NOR | \ 273 CSPR_V) 274 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 275 /* NOR Flash Timing Params */ 276 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 277 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 278 FTIM0_NOR_TEADC(0x5) | \ 279 FTIM0_NOR_TEAHC(0x5)) 280 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 281 FTIM1_NOR_TRAD_NOR(0x1A) |\ 282 FTIM1_NOR_TSEQRAD_NOR(0x13)) 283 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 284 FTIM2_NOR_TCH(0x4) | \ 285 FTIM2_NOR_TWPH(0x0E) | \ 286 FTIM2_NOR_TWP(0x1c)) 287 #define CONFIG_SYS_NOR_FTIM3 0x0 288 289 #define CONFIG_SYS_FLASH_QUIET_TEST 290 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 291 292 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 293 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 294 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 295 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 296 297 #define CONFIG_SYS_FLASH_EMPTY_INFO 298 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 299 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 300 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 301 #define QIXIS_BASE 0xffdf0000 302 #ifdef CONFIG_PHYS_64BIT 303 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 304 #else 305 #define QIXIS_BASE_PHYS QIXIS_BASE 306 #endif 307 #define QIXIS_LBMAP_SWITCH 0x06 308 #define QIXIS_LBMAP_MASK 0x0f 309 #define QIXIS_LBMAP_SHIFT 0 310 #define QIXIS_LBMAP_DFLTBANK 0x00 311 #define QIXIS_LBMAP_ALTBANK 0x04 312 #define QIXIS_RST_CTL_RESET 0x31 313 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 314 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 315 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 316 #define QIXIS_RST_FORCE_MEM 0x01 317 318 #define CONFIG_SYS_CSPR3_EXT (0xf) 319 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 320 | CSPR_PORT_SIZE_8 \ 321 | CSPR_MSEL_GPCM \ 322 | CSPR_V) 323 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 324 #define CONFIG_SYS_CSOR3 0x0 325 /* QIXIS Timing parameters for IFC CS3 */ 326 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 327 FTIM0_GPCM_TEADC(0x0e) | \ 328 FTIM0_GPCM_TEAHC(0x0e)) 329 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 330 FTIM1_GPCM_TRAD(0x3f)) 331 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 332 FTIM2_GPCM_TCH(0x8) | \ 333 FTIM2_GPCM_TWP(0x1f)) 334 #define CONFIG_SYS_CS3_FTIM3 0x0 335 336 #define CONFIG_NAND_FSL_IFC 337 #define CONFIG_SYS_NAND_BASE 0xff800000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 340 #else 341 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 342 #endif 343 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 344 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 345 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 346 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 347 | CSPR_V) 348 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 349 350 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 351 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 352 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 353 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 354 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 355 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 356 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 357 358 #define CONFIG_SYS_NAND_ONFI_DETECTION 359 360 /* ONFI NAND Flash mode0 Timing Params */ 361 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 362 FTIM0_NAND_TWP(0x18) | \ 363 FTIM0_NAND_TWCHT(0x07) | \ 364 FTIM0_NAND_TWH(0x0a)) 365 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 366 FTIM1_NAND_TWBE(0x39) | \ 367 FTIM1_NAND_TRR(0x0e) | \ 368 FTIM1_NAND_TRP(0x18)) 369 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 370 FTIM2_NAND_TREH(0x0a) | \ 371 FTIM2_NAND_TWHRE(0x1e)) 372 #define CONFIG_SYS_NAND_FTIM3 0x0 373 374 #define CONFIG_SYS_NAND_DDR_LAW 11 375 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 376 #define CONFIG_SYS_MAX_NAND_DEVICE 1 377 #define CONFIG_CMD_NAND 378 379 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 380 381 #if defined(CONFIG_NAND) 382 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 383 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 384 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 385 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 386 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 387 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 388 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 389 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 390 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 391 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 392 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 398 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 399 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 400 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 401 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 402 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 403 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 404 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 405 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 406 #else 407 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 408 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 409 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 424 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 425 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 426 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 427 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 428 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 429 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 430 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 431 #endif 432 433 #ifdef CONFIG_SPL_BUILD 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 435 #else 436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 437 #endif 438 439 #if defined(CONFIG_RAMBOOT_PBL) 440 #define CONFIG_SYS_RAMBOOT 441 #endif 442 443 #define CONFIG_BOARD_EARLY_INIT_R 444 #define CONFIG_MISC_INIT_R 445 446 #define CONFIG_HWCONFIG 447 448 /* define to use L1 as initial stack */ 449 #define CONFIG_L1_INIT_RAM 450 #define CONFIG_SYS_INIT_RAM_LOCK 451 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 455 /* The assembler doesn't like typecast */ 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 457 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 458 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 459 #else 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 463 #endif 464 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 465 466 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 467 GENERATED_GBL_DATA_SIZE) 468 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 469 470 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 471 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 472 473 /* Serial Port */ 474 #define CONFIG_CONS_INDEX 1 475 #define CONFIG_SYS_NS16550_SERIAL 476 #define CONFIG_SYS_NS16550_REG_SIZE 1 477 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 478 479 #define CONFIG_SYS_BAUDRATE_TABLE \ 480 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 481 482 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 483 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 484 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 485 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 486 487 /* Video */ 488 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 489 #define CONFIG_FSL_DIU_FB 490 #ifdef CONFIG_FSL_DIU_FB 491 #define CONFIG_FSL_DIU_CH7301 492 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 493 #define CONFIG_CMD_BMP 494 #define CONFIG_VIDEO_LOGO 495 #define CONFIG_VIDEO_BMP_LOGO 496 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 497 /* 498 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 499 * disable empty flash sector detection, which is I/O-intensive. 500 */ 501 #undef CONFIG_SYS_FLASH_EMPTY_INFO 502 #endif 503 #endif 504 505 /* I2C */ 506 #define CONFIG_SYS_I2C 507 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 508 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 509 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 510 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 511 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 512 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 513 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 514 515 #define I2C_MUX_PCA_ADDR 0x77 516 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 517 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 518 #define I2C_RETIMER_ADDR 0x18 519 520 /* I2C bus multiplexer */ 521 #define I2C_MUX_CH_DEFAULT 0x8 522 #define I2C_MUX_CH_DIU 0xC 523 #define I2C_MUX_CH5 0xD 524 #define I2C_MUX_CH7 0xF 525 526 /* LDI/DVI Encoder for display */ 527 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 528 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 529 530 /* 531 * RTC configuration 532 */ 533 #define RTC 534 #define CONFIG_RTC_DS3231 1 535 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 536 537 /* 538 * eSPI - Enhanced SPI 539 */ 540 #ifndef CONFIG_SPL_BUILD 541 #endif 542 #define CONFIG_SPI_FLASH_BAR 543 #define CONFIG_SF_DEFAULT_SPEED 10000000 544 #define CONFIG_SF_DEFAULT_MODE 0 545 546 /* 547 * General PCIe 548 * Memory space is mapped 1-1, but I/O space must start from 0. 549 */ 550 #define CONFIG_PCIE1 /* PCIE controller 1 */ 551 #define CONFIG_PCIE2 /* PCIE controller 2 */ 552 #define CONFIG_PCIE3 /* PCIE controller 3 */ 553 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 554 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 555 #define CONFIG_PCI_INDIRECT_BRIDGE 556 557 #ifdef CONFIG_PCI 558 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 559 #ifdef CONFIG_PCIE1 560 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 561 #ifdef CONFIG_PHYS_64BIT 562 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 563 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 564 #else 565 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 567 #endif 568 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 569 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 570 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 571 #ifdef CONFIG_PHYS_64BIT 572 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 573 #else 574 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 575 #endif 576 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 577 #endif 578 579 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 580 #ifdef CONFIG_PCIE2 581 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 582 #ifdef CONFIG_PHYS_64BIT 583 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 584 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 585 #else 586 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 587 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 588 #endif 589 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 590 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 591 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 592 #ifdef CONFIG_PHYS_64BIT 593 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 594 #else 595 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 596 #endif 597 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 598 #endif 599 600 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 601 #ifdef CONFIG_PCIE3 602 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 603 #ifdef CONFIG_PHYS_64BIT 604 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 605 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 606 #else 607 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 608 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 609 #endif 610 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 611 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 612 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 613 #ifdef CONFIG_PHYS_64BIT 614 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 615 #else 616 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 617 #endif 618 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 619 #endif 620 621 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 622 #endif /* CONFIG_PCI */ 623 624 /* 625 *SATA 626 */ 627 #define CONFIG_FSL_SATA_V2 628 #ifdef CONFIG_FSL_SATA_V2 629 #define CONFIG_LIBATA 630 #define CONFIG_FSL_SATA 631 #define CONFIG_SYS_SATA_MAX_DEVICE 1 632 #define CONFIG_SATA1 633 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 634 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 635 #define CONFIG_LBA48 636 #define CONFIG_CMD_SATA 637 #endif 638 639 /* 640 * USB 641 */ 642 #define CONFIG_HAS_FSL_DR_USB 643 644 #ifdef CONFIG_HAS_FSL_DR_USB 645 #define CONFIG_USB_EHCI 646 #define CONFIG_USB_EHCI_FSL 647 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 648 #endif 649 650 /* 651 * SDHC 652 */ 653 #ifdef CONFIG_MMC 654 #define CONFIG_FSL_ESDHC 655 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 656 #endif 657 658 /* Qman/Bman */ 659 #ifndef CONFIG_NOBQFMAN 660 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 661 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 662 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 663 #ifdef CONFIG_PHYS_64BIT 664 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 665 #else 666 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 667 #endif 668 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 669 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 670 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 671 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 672 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 674 CONFIG_SYS_BMAN_CENA_SIZE) 675 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 676 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 677 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 678 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 679 #ifdef CONFIG_PHYS_64BIT 680 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 681 #else 682 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 683 #endif 684 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 685 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 686 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 687 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 688 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 689 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 690 CONFIG_SYS_QMAN_CENA_SIZE) 691 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 692 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 693 694 #define CONFIG_SYS_DPAA_FMAN 695 696 #define CONFIG_QE 697 #define CONFIG_U_QE 698 /* Default address of microcode for the Linux FMan driver */ 699 #if defined(CONFIG_SPIFLASH) 700 /* 701 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 702 * env, so we got 0x110000. 703 */ 704 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 705 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 706 #define CONFIG_SYS_QE_FW_ADDR 0x130000 707 #elif defined(CONFIG_SDCARD) 708 /* 709 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 710 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 711 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 712 */ 713 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 714 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 715 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 716 #elif defined(CONFIG_NAND) 717 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 718 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 719 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 720 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 721 /* 722 * Slave has no ucode locally, it can fetch this from remote. When implementing 723 * in two corenet boards, slave's ucode could be stored in master's memory 724 * space, the address can be mapped from slave TLB->slave LAW-> 725 * slave SRIO or PCIE outbound window->master inbound window-> 726 * master LAW->the ucode address in master's memory space. 727 */ 728 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 729 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 730 #else 731 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 732 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 733 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 734 #endif 735 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 736 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 737 #endif /* CONFIG_NOBQFMAN */ 738 739 #ifdef CONFIG_SYS_DPAA_FMAN 740 #define CONFIG_FMAN_ENET 741 #define CONFIG_PHYLIB_10G 742 #define CONFIG_PHY_VITESSE 743 #define CONFIG_PHY_REALTEK 744 #define CONFIG_PHY_TERANETICS 745 #define RGMII_PHY1_ADDR 0x1 746 #define RGMII_PHY2_ADDR 0x2 747 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 748 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 749 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 750 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 751 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 752 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 753 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 754 #endif 755 756 #ifdef CONFIG_FMAN_ENET 757 #define CONFIG_MII /* MII PHY management */ 758 #define CONFIG_ETHPRIME "FM1@DTSEC4" 759 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 760 #endif 761 762 /* 763 * Dynamic MTD Partition support with mtdparts 764 */ 765 #ifndef CONFIG_SYS_NO_FLASH 766 #define CONFIG_MTD_DEVICE 767 #define CONFIG_MTD_PARTITIONS 768 #define CONFIG_CMD_MTDPARTS 769 #define CONFIG_FLASH_CFI_MTD 770 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 771 "spi0=spife110000.0" 772 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 773 "128k(dtb),96m(fs),-(user);"\ 774 "fff800000.flash:2m(uboot),9m(kernel),"\ 775 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 776 "2m(uboot),9m(kernel),128k(dtb),-(user)" 777 #endif 778 779 /* 780 * Environment 781 */ 782 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 783 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 784 785 /* 786 * Command line configuration. 787 */ 788 #define CONFIG_CMD_DATE 789 #define CONFIG_CMD_EEPROM 790 #define CONFIG_CMD_ERRATA 791 #define CONFIG_CMD_IRQ 792 #define CONFIG_CMD_REGINFO 793 794 #ifdef CONFIG_PCI 795 #define CONFIG_CMD_PCI 796 #endif 797 798 /* 799 * Miscellaneous configurable options 800 */ 801 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 802 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 803 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 804 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 805 #ifdef CONFIG_CMD_KGDB 806 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 807 #else 808 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 809 #endif 810 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 811 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 812 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 813 814 /* 815 * For booting Linux, the board info and command line data 816 * have to be in the first 64 MB of memory, since this is 817 * the maximum mapped by the Linux kernel during initialization. 818 */ 819 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 820 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 821 822 #ifdef CONFIG_CMD_KGDB 823 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 824 #endif 825 826 /* 827 * Environment Configuration 828 */ 829 #define CONFIG_ROOTPATH "/opt/nfsroot" 830 #define CONFIG_BOOTFILE "uImage" 831 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 832 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 833 #define CONFIG_BAUDRATE 115200 834 #define __USB_PHY_TYPE utmi 835 836 #define CONFIG_EXTRA_ENV_SETTINGS \ 837 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 838 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 839 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 840 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 841 "fdtfile=t1024qds/t1024qds.dtb\0" \ 842 "netdev=eth0\0" \ 843 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 844 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 845 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 846 "tftpflash=tftpboot $loadaddr $uboot && " \ 847 "protect off $ubootaddr +$filesize && " \ 848 "erase $ubootaddr +$filesize && " \ 849 "cp.b $loadaddr $ubootaddr $filesize && " \ 850 "protect on $ubootaddr +$filesize && " \ 851 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 852 "consoledev=ttyS0\0" \ 853 "ramdiskaddr=2000000\0" \ 854 "fdtaddr=d00000\0" \ 855 "bdev=sda3\0" 856 857 #define CONFIG_LINUX \ 858 "setenv bootargs root=/dev/ram rw " \ 859 "console=$consoledev,$baudrate $othbootargs;" \ 860 "setenv ramdiskaddr 0x02000000;" \ 861 "setenv fdtaddr 0x00c00000;" \ 862 "setenv loadaddr 0x1000000;" \ 863 "bootm $loadaddr $ramdiskaddr $fdtaddr" 864 865 #define CONFIG_NFSBOOTCOMMAND \ 866 "setenv bootargs root=/dev/nfs rw " \ 867 "nfsroot=$serverip:$rootpath " \ 868 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 869 "console=$consoledev,$baudrate $othbootargs;" \ 870 "tftp $loadaddr $bootfile;" \ 871 "tftp $fdtaddr $fdtfile;" \ 872 "bootm $loadaddr - $fdtaddr" 873 874 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 875 876 /* Hash command with SHA acceleration supported in hardware */ 877 #ifdef CONFIG_FSL_CAAM 878 #define CONFIG_CMD_HASH 879 #define CONFIG_SHA_HW_ACCEL 880 #endif 881 882 #include <asm/fsl_secure_boot.h> 883 884 #endif /* __T1024QDS_H */ 885