1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_FSL_LAW /* Use common FSL init code */ 49 #define CONFIG_SYS_TEXT_BASE 0x00201000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 51 #define CONFIG_SPL_PAD_TO 0x40000 52 #define CONFIG_SPL_MAX_SIZE 0x28000 53 #define RESET_VECTOR_OFFSET 0x27FFC 54 #define BOOT_PAGE_OFFSET 0x27000 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 62 #ifdef CONFIG_NAND 63 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 65 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 66 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 68 #define CONFIG_SPL_NAND_BOOT 69 #endif 70 71 #ifdef CONFIG_SPIFLASH 72 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 73 #define CONFIG_SPL_SPI_FLASH_MINIMAL 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 78 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 79 #ifndef CONFIG_SPL_BUILD 80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 81 #endif 82 #define CONFIG_SPL_SPI_BOOT 83 #endif 84 85 #ifdef CONFIG_SDCARD 86 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 87 #define CONFIG_SPL_MMC_MINIMAL 88 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 89 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 90 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 91 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 92 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 93 #ifndef CONFIG_SPL_BUILD 94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 95 #endif 96 #define CONFIG_SPL_MMC_BOOT 97 #endif 98 99 #endif /* CONFIG_RAMBOOT_PBL */ 100 101 #ifndef CONFIG_SYS_TEXT_BASE 102 #define CONFIG_SYS_TEXT_BASE 0xeff40000 103 #endif 104 105 #ifndef CONFIG_RESET_VECTOR_ADDRESS 106 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 107 #endif 108 109 #ifndef CONFIG_SYS_NO_FLASH 110 #define CONFIG_FLASH_CFI_DRIVER 111 #define CONFIG_SYS_FLASH_CFI 112 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 113 #endif 114 115 /* PCIe Boot - Master */ 116 #define CONFIG_SRIO_PCIE_BOOT_MASTER 117 /* 118 * for slave u-boot IMAGE instored in master memory space, 119 * PHYS must be aligned based on the SIZE 120 */ 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 126 #else 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 129 #endif 130 /* 131 * for slave UCODE and ENV instored in master memory space, 132 * PHYS must be aligned based on the SIZE 133 */ 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 137 #else 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 140 #endif 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 142 /* slave core release by master*/ 143 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 144 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 145 146 /* PCIe Boot - Slave */ 147 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 149 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 150 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 151 /* Set 1M boot space for PCIe boot */ 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 153 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 154 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 155 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 156 #define CONFIG_SYS_NO_FLASH 157 #endif 158 159 #if defined(CONFIG_SPIFLASH) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_SPI_FLASH 162 #define CONFIG_ENV_SPI_BUS 0 163 #define CONFIG_ENV_SPI_CS 0 164 #define CONFIG_ENV_SPI_MAX_HZ 10000000 165 #define CONFIG_ENV_SPI_MODE 0 166 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 167 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 168 #define CONFIG_ENV_SECT_SIZE 0x10000 169 #elif defined(CONFIG_SDCARD) 170 #define CONFIG_SYS_EXTRA_ENV_RELOC 171 #define CONFIG_ENV_IS_IN_MMC 172 #define CONFIG_SYS_MMC_ENV_DEV 0 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_OFFSET (512 * 0x800) 175 #elif defined(CONFIG_NAND) 176 #define CONFIG_SYS_EXTRA_ENV_RELOC 177 #define CONFIG_ENV_IS_IN_NAND 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 180 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 181 #define CONFIG_ENV_IS_IN_REMOTE 182 #define CONFIG_ENV_ADDR 0xffe20000 183 #define CONFIG_ENV_SIZE 0x2000 184 #elif defined(CONFIG_ENV_IS_NOWHERE) 185 #define CONFIG_ENV_SIZE 0x2000 186 #else 187 #define CONFIG_ENV_IS_IN_FLASH 188 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 189 #define CONFIG_ENV_SIZE 0x2000 190 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 191 #endif 192 193 #ifndef __ASSEMBLY__ 194 unsigned long get_board_sys_clk(void); 195 unsigned long get_board_ddr_clk(void); 196 #endif 197 198 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 199 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 200 201 /* 202 * These can be toggled for performance analysis, otherwise use default. 203 */ 204 #define CONFIG_SYS_CACHE_STASHING 205 #define CONFIG_BACKSIDE_L2_CACHE 206 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 207 #define CONFIG_BTB /* toggle branch predition */ 208 #define CONFIG_DDR_ECC 209 #ifdef CONFIG_DDR_ECC 210 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 211 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 212 #endif 213 214 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 215 #define CONFIG_SYS_MEMTEST_END 0x00400000 216 #define CONFIG_SYS_ALT_MEMTEST 217 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 218 219 /* 220 * Config the L3 Cache as L3 SRAM 221 */ 222 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 223 #define CONFIG_SYS_L3_SIZE (256 << 10) 224 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 225 #ifdef CONFIG_RAMBOOT_PBL 226 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 227 #endif 228 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 229 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 230 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 231 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 232 233 #ifdef CONFIG_PHYS_64BIT 234 #define CONFIG_SYS_DCSRBAR 0xf0000000 235 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 236 #endif 237 238 /* EEPROM */ 239 #define CONFIG_ID_EEPROM 240 #define CONFIG_SYS_I2C_EEPROM_NXID 241 #define CONFIG_SYS_EEPROM_BUS_NUM 0 242 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 243 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 246 247 /* 248 * DDR Setup 249 */ 250 #define CONFIG_VERY_BIG_RAM 251 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 252 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 253 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 254 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 255 #define CONFIG_DDR_SPD 256 #ifndef CONFIG_SYS_FSL_DDR4 257 #define CONFIG_SYS_FSL_DDR3 258 #endif 259 260 #define CONFIG_SYS_SPD_BUS_NUM 0 261 #define SPD_EEPROM_ADDRESS 0x51 262 263 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 264 265 /* 266 * IFC Definitions 267 */ 268 #define CONFIG_SYS_FLASH_BASE 0xe0000000 269 #ifdef CONFIG_PHYS_64BIT 270 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 271 #else 272 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 273 #endif 274 275 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 276 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 277 + 0x8000000) | \ 278 CSPR_PORT_SIZE_16 | \ 279 CSPR_MSEL_NOR | \ 280 CSPR_V) 281 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 282 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 283 CSPR_PORT_SIZE_16 | \ 284 CSPR_MSEL_NOR | \ 285 CSPR_V) 286 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 287 /* NOR Flash Timing Params */ 288 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 289 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 290 FTIM0_NOR_TEADC(0x5) | \ 291 FTIM0_NOR_TEAHC(0x5)) 292 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 293 FTIM1_NOR_TRAD_NOR(0x1A) |\ 294 FTIM1_NOR_TSEQRAD_NOR(0x13)) 295 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 296 FTIM2_NOR_TCH(0x4) | \ 297 FTIM2_NOR_TWPH(0x0E) | \ 298 FTIM2_NOR_TWP(0x1c)) 299 #define CONFIG_SYS_NOR_FTIM3 0x0 300 301 #define CONFIG_SYS_FLASH_QUIET_TEST 302 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 303 304 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 305 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 306 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 307 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 308 309 #define CONFIG_SYS_FLASH_EMPTY_INFO 310 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 311 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 312 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 313 #define QIXIS_BASE 0xffdf0000 314 #ifdef CONFIG_PHYS_64BIT 315 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 316 #else 317 #define QIXIS_BASE_PHYS QIXIS_BASE 318 #endif 319 #define QIXIS_LBMAP_SWITCH 0x06 320 #define QIXIS_LBMAP_MASK 0x0f 321 #define QIXIS_LBMAP_SHIFT 0 322 #define QIXIS_LBMAP_DFLTBANK 0x00 323 #define QIXIS_LBMAP_ALTBANK 0x04 324 #define QIXIS_RST_CTL_RESET 0x31 325 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 326 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 327 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 328 #define QIXIS_RST_FORCE_MEM 0x01 329 330 #define CONFIG_SYS_CSPR3_EXT (0xf) 331 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 332 | CSPR_PORT_SIZE_8 \ 333 | CSPR_MSEL_GPCM \ 334 | CSPR_V) 335 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 336 #define CONFIG_SYS_CSOR3 0x0 337 /* QIXIS Timing parameters for IFC CS3 */ 338 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 339 FTIM0_GPCM_TEADC(0x0e) | \ 340 FTIM0_GPCM_TEAHC(0x0e)) 341 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 342 FTIM1_GPCM_TRAD(0x3f)) 343 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 344 FTIM2_GPCM_TCH(0x8) | \ 345 FTIM2_GPCM_TWP(0x1f)) 346 #define CONFIG_SYS_CS3_FTIM3 0x0 347 348 #define CONFIG_NAND_FSL_IFC 349 #define CONFIG_SYS_NAND_BASE 0xff800000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 352 #else 353 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 354 #endif 355 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 356 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 357 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 358 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 359 | CSPR_V) 360 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 361 362 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 363 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 364 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 365 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 366 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 367 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 368 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 369 370 #define CONFIG_SYS_NAND_ONFI_DETECTION 371 372 /* ONFI NAND Flash mode0 Timing Params */ 373 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 374 FTIM0_NAND_TWP(0x18) | \ 375 FTIM0_NAND_TWCHT(0x07) | \ 376 FTIM0_NAND_TWH(0x0a)) 377 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 378 FTIM1_NAND_TWBE(0x39) | \ 379 FTIM1_NAND_TRR(0x0e) | \ 380 FTIM1_NAND_TRP(0x18)) 381 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 382 FTIM2_NAND_TREH(0x0a) | \ 383 FTIM2_NAND_TWHRE(0x1e)) 384 #define CONFIG_SYS_NAND_FTIM3 0x0 385 386 #define CONFIG_SYS_NAND_DDR_LAW 11 387 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 388 #define CONFIG_SYS_MAX_NAND_DEVICE 1 389 #define CONFIG_CMD_NAND 390 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 392 393 #if defined(CONFIG_NAND) 394 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 395 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 396 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 397 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 398 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 399 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 400 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 401 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 402 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 403 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 404 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 405 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 406 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 407 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 408 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 409 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 410 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 411 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 412 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 413 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 414 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 415 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 416 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 417 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 418 #else 419 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 420 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 421 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 422 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 423 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 424 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 425 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 426 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 427 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 428 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 429 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 430 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 431 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 432 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 433 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 434 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 435 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 436 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 437 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 438 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 439 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 440 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 441 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 442 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 443 #endif 444 445 #ifdef CONFIG_SPL_BUILD 446 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 447 #else 448 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 449 #endif 450 451 #if defined(CONFIG_RAMBOOT_PBL) 452 #define CONFIG_SYS_RAMBOOT 453 #endif 454 455 #define CONFIG_BOARD_EARLY_INIT_R 456 #define CONFIG_MISC_INIT_R 457 458 #define CONFIG_HWCONFIG 459 460 /* define to use L1 as initial stack */ 461 #define CONFIG_L1_INIT_RAM 462 #define CONFIG_SYS_INIT_RAM_LOCK 463 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 467 /* The assembler doesn't like typecast */ 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 469 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 470 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 471 #else 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 475 #endif 476 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 477 478 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 479 GENERATED_GBL_DATA_SIZE) 480 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 481 482 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 483 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 484 485 /* Serial Port */ 486 #define CONFIG_CONS_INDEX 1 487 #define CONFIG_SYS_NS16550_SERIAL 488 #define CONFIG_SYS_NS16550_REG_SIZE 1 489 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 490 491 #define CONFIG_SYS_BAUDRATE_TABLE \ 492 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 493 494 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 495 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 496 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 497 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 498 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 499 500 /* Video */ 501 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 502 #define CONFIG_FSL_DIU_FB 503 #ifdef CONFIG_FSL_DIU_FB 504 #define CONFIG_FSL_DIU_CH7301 505 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 506 #define CONFIG_VIDEO 507 #define CONFIG_CMD_BMP 508 #define CONFIG_CFB_CONSOLE 509 #define CONFIG_VIDEO_SW_CURSOR 510 #define CONFIG_VGA_AS_SINGLE_DEVICE 511 #define CONFIG_VIDEO_LOGO 512 #define CONFIG_VIDEO_BMP_LOGO 513 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 514 /* 515 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 516 * disable empty flash sector detection, which is I/O-intensive. 517 */ 518 #undef CONFIG_SYS_FLASH_EMPTY_INFO 519 #endif 520 #endif 521 522 /* I2C */ 523 #define CONFIG_SYS_I2C 524 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 525 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 526 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 527 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 528 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 529 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 530 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 531 532 #define I2C_MUX_PCA_ADDR 0x77 533 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 534 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 535 #define I2C_RETIMER_ADDR 0x18 536 537 /* I2C bus multiplexer */ 538 #define I2C_MUX_CH_DEFAULT 0x8 539 #define I2C_MUX_CH_DIU 0xC 540 #define I2C_MUX_CH5 0xD 541 #define I2C_MUX_CH7 0xF 542 543 /* LDI/DVI Encoder for display */ 544 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 545 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 546 547 /* 548 * RTC configuration 549 */ 550 #define RTC 551 #define CONFIG_RTC_DS3231 1 552 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 553 554 /* 555 * eSPI - Enhanced SPI 556 */ 557 #ifndef CONFIG_SPL_BUILD 558 #endif 559 #define CONFIG_SPI_FLASH_BAR 560 #define CONFIG_SF_DEFAULT_SPEED 10000000 561 #define CONFIG_SF_DEFAULT_MODE 0 562 563 /* 564 * General PCIe 565 * Memory space is mapped 1-1, but I/O space must start from 0. 566 */ 567 #define CONFIG_PCI /* Enable PCI/PCIE */ 568 #define CONFIG_PCIE1 /* PCIE controller 1 */ 569 #define CONFIG_PCIE2 /* PCIE controller 2 */ 570 #define CONFIG_PCIE3 /* PCIE controller 3 */ 571 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 572 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 573 #define CONFIG_PCI_INDIRECT_BRIDGE 574 575 #ifdef CONFIG_PCI 576 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 577 #ifdef CONFIG_PCIE1 578 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 579 #ifdef CONFIG_PHYS_64BIT 580 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 582 #else 583 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 584 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 585 #endif 586 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 587 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 588 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 591 #else 592 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 593 #endif 594 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 595 #endif 596 597 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 598 #ifdef CONFIG_PCIE2 599 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 600 #ifdef CONFIG_PHYS_64BIT 601 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 602 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 603 #else 604 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 605 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 606 #endif 607 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 608 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 609 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 612 #else 613 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 614 #endif 615 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 616 #endif 617 618 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 619 #ifdef CONFIG_PCIE3 620 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 621 #ifdef CONFIG_PHYS_64BIT 622 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 623 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 624 #else 625 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 626 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 627 #endif 628 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 629 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 630 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 631 #ifdef CONFIG_PHYS_64BIT 632 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 633 #else 634 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 635 #endif 636 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 637 #endif 638 639 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 640 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 641 #define CONFIG_DOS_PARTITION 642 #endif /* CONFIG_PCI */ 643 644 /* 645 *SATA 646 */ 647 #define CONFIG_FSL_SATA_V2 648 #ifdef CONFIG_FSL_SATA_V2 649 #define CONFIG_LIBATA 650 #define CONFIG_FSL_SATA 651 #define CONFIG_SYS_SATA_MAX_DEVICE 1 652 #define CONFIG_SATA1 653 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 654 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 655 #define CONFIG_LBA48 656 #define CONFIG_CMD_SATA 657 #define CONFIG_DOS_PARTITION 658 #endif 659 660 /* 661 * USB 662 */ 663 #define CONFIG_HAS_FSL_DR_USB 664 665 #ifdef CONFIG_HAS_FSL_DR_USB 666 #define CONFIG_USB_EHCI 667 #define CONFIG_USB_EHCI_FSL 668 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 669 #endif 670 671 /* 672 * SDHC 673 */ 674 #define CONFIG_MMC 675 #ifdef CONFIG_MMC 676 #define CONFIG_FSL_ESDHC 677 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 678 #define CONFIG_GENERIC_MMC 679 #define CONFIG_DOS_PARTITION 680 #endif 681 682 /* Qman/Bman */ 683 #ifndef CONFIG_NOBQFMAN 684 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 685 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 686 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 687 #ifdef CONFIG_PHYS_64BIT 688 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 689 #else 690 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 691 #endif 692 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 693 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 694 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 695 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 696 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 697 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 698 CONFIG_SYS_BMAN_CENA_SIZE) 699 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 700 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 701 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 702 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 703 #ifdef CONFIG_PHYS_64BIT 704 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 705 #else 706 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 707 #endif 708 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 709 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 710 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 711 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 712 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 713 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 714 CONFIG_SYS_QMAN_CENA_SIZE) 715 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 716 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 717 718 #define CONFIG_SYS_DPAA_FMAN 719 720 #define CONFIG_QE 721 #define CONFIG_U_QE 722 /* Default address of microcode for the Linux FMan driver */ 723 #if defined(CONFIG_SPIFLASH) 724 /* 725 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 726 * env, so we got 0x110000. 727 */ 728 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 729 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 730 #define CONFIG_SYS_QE_FW_ADDR 0x130000 731 #elif defined(CONFIG_SDCARD) 732 /* 733 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 734 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 735 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 736 */ 737 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 738 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 739 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 740 #elif defined(CONFIG_NAND) 741 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 742 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 743 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 744 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 745 /* 746 * Slave has no ucode locally, it can fetch this from remote. When implementing 747 * in two corenet boards, slave's ucode could be stored in master's memory 748 * space, the address can be mapped from slave TLB->slave LAW-> 749 * slave SRIO or PCIE outbound window->master inbound window-> 750 * master LAW->the ucode address in master's memory space. 751 */ 752 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 753 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 754 #else 755 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 756 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 757 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 758 #endif 759 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 760 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 761 #endif /* CONFIG_NOBQFMAN */ 762 763 #ifdef CONFIG_SYS_DPAA_FMAN 764 #define CONFIG_FMAN_ENET 765 #define CONFIG_PHYLIB_10G 766 #define CONFIG_PHY_VITESSE 767 #define CONFIG_PHY_REALTEK 768 #define CONFIG_PHY_TERANETICS 769 #define RGMII_PHY1_ADDR 0x1 770 #define RGMII_PHY2_ADDR 0x2 771 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 772 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 773 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 774 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 775 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 776 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 777 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 778 #endif 779 780 #ifdef CONFIG_FMAN_ENET 781 #define CONFIG_MII /* MII PHY management */ 782 #define CONFIG_ETHPRIME "FM1@DTSEC4" 783 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 784 #endif 785 786 /* 787 * Dynamic MTD Partition support with mtdparts 788 */ 789 #ifndef CONFIG_SYS_NO_FLASH 790 #define CONFIG_MTD_DEVICE 791 #define CONFIG_MTD_PARTITIONS 792 #define CONFIG_CMD_MTDPARTS 793 #define CONFIG_FLASH_CFI_MTD 794 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 795 "spi0=spife110000.0" 796 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 797 "128k(dtb),96m(fs),-(user);"\ 798 "fff800000.flash:2m(uboot),9m(kernel),"\ 799 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 800 "2m(uboot),9m(kernel),128k(dtb),-(user)" 801 #endif 802 803 /* 804 * Environment 805 */ 806 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 807 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 808 809 /* 810 * Command line configuration. 811 */ 812 #define CONFIG_CMD_DATE 813 #define CONFIG_CMD_EEPROM 814 #define CONFIG_CMD_ERRATA 815 #define CONFIG_CMD_IRQ 816 #define CONFIG_CMD_REGINFO 817 818 #ifdef CONFIG_PCI 819 #define CONFIG_CMD_PCI 820 #endif 821 822 /* 823 * Miscellaneous configurable options 824 */ 825 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 826 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 827 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 828 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 829 #ifdef CONFIG_CMD_KGDB 830 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 831 #else 832 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 833 #endif 834 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 835 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 836 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 837 838 /* 839 * For booting Linux, the board info and command line data 840 * have to be in the first 64 MB of memory, since this is 841 * the maximum mapped by the Linux kernel during initialization. 842 */ 843 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 844 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 845 846 #ifdef CONFIG_CMD_KGDB 847 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 848 #endif 849 850 /* 851 * Environment Configuration 852 */ 853 #define CONFIG_ROOTPATH "/opt/nfsroot" 854 #define CONFIG_BOOTFILE "uImage" 855 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 856 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 857 #define CONFIG_BAUDRATE 115200 858 #define __USB_PHY_TYPE utmi 859 860 #define CONFIG_EXTRA_ENV_SETTINGS \ 861 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 862 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 863 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 864 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 865 "fdtfile=t1024qds/t1024qds.dtb\0" \ 866 "netdev=eth0\0" \ 867 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 868 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 869 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 870 "tftpflash=tftpboot $loadaddr $uboot && " \ 871 "protect off $ubootaddr +$filesize && " \ 872 "erase $ubootaddr +$filesize && " \ 873 "cp.b $loadaddr $ubootaddr $filesize && " \ 874 "protect on $ubootaddr +$filesize && " \ 875 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 876 "consoledev=ttyS0\0" \ 877 "ramdiskaddr=2000000\0" \ 878 "fdtaddr=d00000\0" \ 879 "bdev=sda3\0" 880 881 #define CONFIG_LINUX \ 882 "setenv bootargs root=/dev/ram rw " \ 883 "console=$consoledev,$baudrate $othbootargs;" \ 884 "setenv ramdiskaddr 0x02000000;" \ 885 "setenv fdtaddr 0x00c00000;" \ 886 "setenv loadaddr 0x1000000;" \ 887 "bootm $loadaddr $ramdiskaddr $fdtaddr" 888 889 #define CONFIG_NFSBOOTCOMMAND \ 890 "setenv bootargs root=/dev/nfs rw " \ 891 "nfsroot=$serverip:$rootpath " \ 892 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 893 "console=$consoledev,$baudrate $othbootargs;" \ 894 "tftp $loadaddr $bootfile;" \ 895 "tftp $fdtaddr $fdtfile;" \ 896 "bootm $loadaddr - $fdtaddr" 897 898 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 899 900 /* Hash command with SHA acceleration supported in hardware */ 901 #ifdef CONFIG_FSL_CAAM 902 #define CONFIG_CMD_HASH 903 #define CONFIG_SHA_HW_ACCEL 904 #endif 905 906 #include <asm/fsl_secure_boot.h> 907 908 #endif /* __T1024QDS_H */ 909