1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 #define CONFIG_FSL_IFC /* Enable IFC Support */ 27 28 #define CONFIG_ENV_OVERWRITE 29 30 #define CONFIG_DEEP_SLEEP 31 32 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x00201000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #define CONFIG_SYS_NO_FLASH 49 #endif 50 51 #ifdef CONFIG_NAND 52 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 53 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 55 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 56 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 58 #define CONFIG_SPL_NAND_BOOT 59 #endif 60 61 #ifdef CONFIG_SPIFLASH 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 63 #define CONFIG_SPL_SPI_FLASH_MINIMAL 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 69 #ifndef CONFIG_SPL_BUILD 70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 71 #endif 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 73 #define CONFIG_SPL_SPI_BOOT 74 #endif 75 76 #ifdef CONFIG_SDCARD 77 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 78 #define CONFIG_SPL_MMC_MINIMAL 79 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 81 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 82 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 88 #define CONFIG_SPL_MMC_BOOT 89 #endif 90 91 #endif /* CONFIG_RAMBOOT_PBL */ 92 93 #ifndef CONFIG_SYS_TEXT_BASE 94 #define CONFIG_SYS_TEXT_BASE 0xeff40000 95 #endif 96 97 #ifndef CONFIG_RESET_VECTOR_ADDRESS 98 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 99 #endif 100 101 #ifndef CONFIG_SYS_NO_FLASH 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_FLASH_CFI 104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 105 #endif 106 107 /* PCIe Boot - Master */ 108 #define CONFIG_SRIO_PCIE_BOOT_MASTER 109 /* 110 * for slave u-boot IMAGE instored in master memory space, 111 * PHYS must be aligned based on the SIZE 112 */ 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 114 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 118 #else 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 121 #endif 122 /* 123 * for slave UCODE and ENV instored in master memory space, 124 * PHYS must be aligned based on the SIZE 125 */ 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 128 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 129 #else 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 132 #endif 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 134 /* slave core release by master*/ 135 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 136 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 137 138 /* PCIe Boot - Slave */ 139 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 141 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 143 /* Set 1M boot space for PCIe boot */ 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 145 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 146 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 147 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 148 #define CONFIG_SYS_NO_FLASH 149 #endif 150 151 #if defined(CONFIG_SPIFLASH) 152 #define CONFIG_SYS_EXTRA_ENV_RELOC 153 #define CONFIG_ENV_IS_IN_SPI_FLASH 154 #define CONFIG_ENV_SPI_BUS 0 155 #define CONFIG_ENV_SPI_CS 0 156 #define CONFIG_ENV_SPI_MAX_HZ 10000000 157 #define CONFIG_ENV_SPI_MODE 0 158 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 159 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 160 #define CONFIG_ENV_SECT_SIZE 0x10000 161 #elif defined(CONFIG_SDCARD) 162 #define CONFIG_SYS_EXTRA_ENV_RELOC 163 #define CONFIG_ENV_IS_IN_MMC 164 #define CONFIG_SYS_MMC_ENV_DEV 0 165 #define CONFIG_ENV_SIZE 0x2000 166 #define CONFIG_ENV_OFFSET (512 * 0x800) 167 #elif defined(CONFIG_NAND) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_ENV_IS_IN_NAND 170 #define CONFIG_ENV_SIZE 0x2000 171 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 172 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 173 #define CONFIG_ENV_IS_IN_REMOTE 174 #define CONFIG_ENV_ADDR 0xffe20000 175 #define CONFIG_ENV_SIZE 0x2000 176 #elif defined(CONFIG_ENV_IS_NOWHERE) 177 #define CONFIG_ENV_SIZE 0x2000 178 #else 179 #define CONFIG_ENV_IS_IN_FLASH 180 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 181 #define CONFIG_ENV_SIZE 0x2000 182 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 183 #endif 184 185 #ifndef __ASSEMBLY__ 186 unsigned long get_board_sys_clk(void); 187 unsigned long get_board_ddr_clk(void); 188 #endif 189 190 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 191 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 192 193 /* 194 * These can be toggled for performance analysis, otherwise use default. 195 */ 196 #define CONFIG_SYS_CACHE_STASHING 197 #define CONFIG_BACKSIDE_L2_CACHE 198 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 199 #define CONFIG_BTB /* toggle branch predition */ 200 #define CONFIG_DDR_ECC 201 #ifdef CONFIG_DDR_ECC 202 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 203 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 204 #endif 205 206 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 207 #define CONFIG_SYS_MEMTEST_END 0x00400000 208 #define CONFIG_SYS_ALT_MEMTEST 209 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 210 211 /* 212 * Config the L3 Cache as L3 SRAM 213 */ 214 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 215 #define CONFIG_SYS_L3_SIZE (256 << 10) 216 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 217 #ifdef CONFIG_RAMBOOT_PBL 218 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 219 #endif 220 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 221 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 222 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 223 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 224 225 #ifdef CONFIG_PHYS_64BIT 226 #define CONFIG_SYS_DCSRBAR 0xf0000000 227 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 228 #endif 229 230 /* EEPROM */ 231 #define CONFIG_ID_EEPROM 232 #define CONFIG_SYS_I2C_EEPROM_NXID 233 #define CONFIG_SYS_EEPROM_BUS_NUM 0 234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 238 239 /* 240 * DDR Setup 241 */ 242 #define CONFIG_VERY_BIG_RAM 243 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 244 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 245 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 246 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 247 #define CONFIG_DDR_SPD 248 249 #define CONFIG_SYS_SPD_BUS_NUM 0 250 #define SPD_EEPROM_ADDRESS 0x51 251 252 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 253 254 /* 255 * IFC Definitions 256 */ 257 #define CONFIG_SYS_FLASH_BASE 0xe0000000 258 #ifdef CONFIG_PHYS_64BIT 259 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 260 #else 261 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 262 #endif 263 264 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 265 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 266 + 0x8000000) | \ 267 CSPR_PORT_SIZE_16 | \ 268 CSPR_MSEL_NOR | \ 269 CSPR_V) 270 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 271 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 272 CSPR_PORT_SIZE_16 | \ 273 CSPR_MSEL_NOR | \ 274 CSPR_V) 275 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 276 /* NOR Flash Timing Params */ 277 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 278 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 279 FTIM0_NOR_TEADC(0x5) | \ 280 FTIM0_NOR_TEAHC(0x5)) 281 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 282 FTIM1_NOR_TRAD_NOR(0x1A) |\ 283 FTIM1_NOR_TSEQRAD_NOR(0x13)) 284 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 285 FTIM2_NOR_TCH(0x4) | \ 286 FTIM2_NOR_TWPH(0x0E) | \ 287 FTIM2_NOR_TWP(0x1c)) 288 #define CONFIG_SYS_NOR_FTIM3 0x0 289 290 #define CONFIG_SYS_FLASH_QUIET_TEST 291 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 292 293 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 294 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 295 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 296 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 297 298 #define CONFIG_SYS_FLASH_EMPTY_INFO 299 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 300 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 301 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 302 #define QIXIS_BASE 0xffdf0000 303 #ifdef CONFIG_PHYS_64BIT 304 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 305 #else 306 #define QIXIS_BASE_PHYS QIXIS_BASE 307 #endif 308 #define QIXIS_LBMAP_SWITCH 0x06 309 #define QIXIS_LBMAP_MASK 0x0f 310 #define QIXIS_LBMAP_SHIFT 0 311 #define QIXIS_LBMAP_DFLTBANK 0x00 312 #define QIXIS_LBMAP_ALTBANK 0x04 313 #define QIXIS_RST_CTL_RESET 0x31 314 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 315 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 316 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 317 #define QIXIS_RST_FORCE_MEM 0x01 318 319 #define CONFIG_SYS_CSPR3_EXT (0xf) 320 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 321 | CSPR_PORT_SIZE_8 \ 322 | CSPR_MSEL_GPCM \ 323 | CSPR_V) 324 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 325 #define CONFIG_SYS_CSOR3 0x0 326 /* QIXIS Timing parameters for IFC CS3 */ 327 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 328 FTIM0_GPCM_TEADC(0x0e) | \ 329 FTIM0_GPCM_TEAHC(0x0e)) 330 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 331 FTIM1_GPCM_TRAD(0x3f)) 332 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 333 FTIM2_GPCM_TCH(0x8) | \ 334 FTIM2_GPCM_TWP(0x1f)) 335 #define CONFIG_SYS_CS3_FTIM3 0x0 336 337 #define CONFIG_NAND_FSL_IFC 338 #define CONFIG_SYS_NAND_BASE 0xff800000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 341 #else 342 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 343 #endif 344 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 345 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 346 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 347 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 348 | CSPR_V) 349 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 350 351 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 352 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 353 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 354 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 355 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 356 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 357 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 358 359 #define CONFIG_SYS_NAND_ONFI_DETECTION 360 361 /* ONFI NAND Flash mode0 Timing Params */ 362 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 363 FTIM0_NAND_TWP(0x18) | \ 364 FTIM0_NAND_TWCHT(0x07) | \ 365 FTIM0_NAND_TWH(0x0a)) 366 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 367 FTIM1_NAND_TWBE(0x39) | \ 368 FTIM1_NAND_TRR(0x0e) | \ 369 FTIM1_NAND_TRP(0x18)) 370 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 371 FTIM2_NAND_TREH(0x0a) | \ 372 FTIM2_NAND_TWHRE(0x1e)) 373 #define CONFIG_SYS_NAND_FTIM3 0x0 374 375 #define CONFIG_SYS_NAND_DDR_LAW 11 376 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 377 #define CONFIG_SYS_MAX_NAND_DEVICE 1 378 #define CONFIG_CMD_NAND 379 380 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 381 382 #if defined(CONFIG_NAND) 383 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 384 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 385 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 386 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 387 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 388 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 389 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 390 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 391 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 392 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 393 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 394 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 395 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 396 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 397 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 398 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 399 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 400 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 401 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 402 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 403 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 404 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 405 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 406 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 407 #else 408 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 409 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 410 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 411 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 412 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 413 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 414 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 415 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 416 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 417 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 418 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 424 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 425 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 426 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 427 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 428 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 429 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 430 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 431 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 432 #endif 433 434 #ifdef CONFIG_SPL_BUILD 435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 436 #else 437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 438 #endif 439 440 #if defined(CONFIG_RAMBOOT_PBL) 441 #define CONFIG_SYS_RAMBOOT 442 #endif 443 444 #define CONFIG_BOARD_EARLY_INIT_R 445 #define CONFIG_MISC_INIT_R 446 447 #define CONFIG_HWCONFIG 448 449 /* define to use L1 as initial stack */ 450 #define CONFIG_L1_INIT_RAM 451 #define CONFIG_SYS_INIT_RAM_LOCK 452 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 456 /* The assembler doesn't like typecast */ 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 458 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 459 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 460 #else 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 464 #endif 465 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 466 467 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 468 GENERATED_GBL_DATA_SIZE) 469 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 470 471 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 472 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 473 474 /* Serial Port */ 475 #define CONFIG_CONS_INDEX 1 476 #define CONFIG_SYS_NS16550_SERIAL 477 #define CONFIG_SYS_NS16550_REG_SIZE 1 478 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 479 480 #define CONFIG_SYS_BAUDRATE_TABLE \ 481 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 482 483 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 484 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 485 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 486 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 487 488 /* Video */ 489 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 490 #define CONFIG_FSL_DIU_FB 491 #ifdef CONFIG_FSL_DIU_FB 492 #define CONFIG_FSL_DIU_CH7301 493 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 494 #define CONFIG_CMD_BMP 495 #define CONFIG_VIDEO_LOGO 496 #define CONFIG_VIDEO_BMP_LOGO 497 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 498 /* 499 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 500 * disable empty flash sector detection, which is I/O-intensive. 501 */ 502 #undef CONFIG_SYS_FLASH_EMPTY_INFO 503 #endif 504 #endif 505 506 /* I2C */ 507 #define CONFIG_SYS_I2C 508 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 509 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 510 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 511 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 512 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 513 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 514 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 515 516 #define I2C_MUX_PCA_ADDR 0x77 517 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 518 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 519 #define I2C_RETIMER_ADDR 0x18 520 521 /* I2C bus multiplexer */ 522 #define I2C_MUX_CH_DEFAULT 0x8 523 #define I2C_MUX_CH_DIU 0xC 524 #define I2C_MUX_CH5 0xD 525 #define I2C_MUX_CH7 0xF 526 527 /* LDI/DVI Encoder for display */ 528 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 529 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 530 531 /* 532 * RTC configuration 533 */ 534 #define RTC 535 #define CONFIG_RTC_DS3231 1 536 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 537 538 /* 539 * eSPI - Enhanced SPI 540 */ 541 #ifndef CONFIG_SPL_BUILD 542 #endif 543 #define CONFIG_SPI_FLASH_BAR 544 #define CONFIG_SF_DEFAULT_SPEED 10000000 545 #define CONFIG_SF_DEFAULT_MODE 0 546 547 /* 548 * General PCIe 549 * Memory space is mapped 1-1, but I/O space must start from 0. 550 */ 551 #define CONFIG_PCIE1 /* PCIE controller 1 */ 552 #define CONFIG_PCIE2 /* PCIE controller 2 */ 553 #define CONFIG_PCIE3 /* PCIE controller 3 */ 554 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 555 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 556 #define CONFIG_PCI_INDIRECT_BRIDGE 557 558 #ifdef CONFIG_PCI 559 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 560 #ifdef CONFIG_PCIE1 561 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 562 #ifdef CONFIG_PHYS_64BIT 563 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 564 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 565 #else 566 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 567 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 568 #endif 569 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 570 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 571 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 572 #ifdef CONFIG_PHYS_64BIT 573 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 574 #else 575 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 576 #endif 577 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 578 #endif 579 580 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 581 #ifdef CONFIG_PCIE2 582 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 583 #ifdef CONFIG_PHYS_64BIT 584 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 585 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 586 #else 587 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 588 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 589 #endif 590 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 591 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 592 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 593 #ifdef CONFIG_PHYS_64BIT 594 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 595 #else 596 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 597 #endif 598 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 599 #endif 600 601 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 602 #ifdef CONFIG_PCIE3 603 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 606 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 607 #else 608 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 609 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 610 #endif 611 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 612 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 613 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 616 #else 617 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 618 #endif 619 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 620 #endif 621 622 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 623 #endif /* CONFIG_PCI */ 624 625 /* 626 *SATA 627 */ 628 #define CONFIG_FSL_SATA_V2 629 #ifdef CONFIG_FSL_SATA_V2 630 #define CONFIG_LIBATA 631 #define CONFIG_FSL_SATA 632 #define CONFIG_SYS_SATA_MAX_DEVICE 1 633 #define CONFIG_SATA1 634 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 635 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 636 #define CONFIG_LBA48 637 #define CONFIG_CMD_SATA 638 #endif 639 640 /* 641 * USB 642 */ 643 #define CONFIG_HAS_FSL_DR_USB 644 645 #ifdef CONFIG_HAS_FSL_DR_USB 646 #define CONFIG_USB_EHCI 647 #define CONFIG_USB_EHCI_FSL 648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 649 #endif 650 651 /* 652 * SDHC 653 */ 654 #ifdef CONFIG_MMC 655 #define CONFIG_FSL_ESDHC 656 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 657 #define CONFIG_GENERIC_MMC 658 #endif 659 660 /* Qman/Bman */ 661 #ifndef CONFIG_NOBQFMAN 662 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 663 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 664 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 665 #ifdef CONFIG_PHYS_64BIT 666 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 667 #else 668 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 669 #endif 670 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 671 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 672 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 673 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 674 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 675 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 676 CONFIG_SYS_BMAN_CENA_SIZE) 677 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 678 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 679 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 680 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 681 #ifdef CONFIG_PHYS_64BIT 682 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 683 #else 684 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 685 #endif 686 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 687 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 688 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 689 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 690 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 691 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 692 CONFIG_SYS_QMAN_CENA_SIZE) 693 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 694 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 695 696 #define CONFIG_SYS_DPAA_FMAN 697 698 #define CONFIG_QE 699 #define CONFIG_U_QE 700 /* Default address of microcode for the Linux FMan driver */ 701 #if defined(CONFIG_SPIFLASH) 702 /* 703 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 704 * env, so we got 0x110000. 705 */ 706 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 707 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 708 #define CONFIG_SYS_QE_FW_ADDR 0x130000 709 #elif defined(CONFIG_SDCARD) 710 /* 711 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 712 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 713 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 714 */ 715 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 716 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 717 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 718 #elif defined(CONFIG_NAND) 719 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 720 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 721 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 722 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 723 /* 724 * Slave has no ucode locally, it can fetch this from remote. When implementing 725 * in two corenet boards, slave's ucode could be stored in master's memory 726 * space, the address can be mapped from slave TLB->slave LAW-> 727 * slave SRIO or PCIE outbound window->master inbound window-> 728 * master LAW->the ucode address in master's memory space. 729 */ 730 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 731 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 732 #else 733 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 734 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 735 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 736 #endif 737 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 738 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 739 #endif /* CONFIG_NOBQFMAN */ 740 741 #ifdef CONFIG_SYS_DPAA_FMAN 742 #define CONFIG_FMAN_ENET 743 #define CONFIG_PHYLIB_10G 744 #define CONFIG_PHY_VITESSE 745 #define CONFIG_PHY_REALTEK 746 #define CONFIG_PHY_TERANETICS 747 #define RGMII_PHY1_ADDR 0x1 748 #define RGMII_PHY2_ADDR 0x2 749 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 750 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 751 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 752 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 753 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 754 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 755 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 756 #endif 757 758 #ifdef CONFIG_FMAN_ENET 759 #define CONFIG_MII /* MII PHY management */ 760 #define CONFIG_ETHPRIME "FM1@DTSEC4" 761 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 762 #endif 763 764 /* 765 * Dynamic MTD Partition support with mtdparts 766 */ 767 #ifndef CONFIG_SYS_NO_FLASH 768 #define CONFIG_MTD_DEVICE 769 #define CONFIG_MTD_PARTITIONS 770 #define CONFIG_CMD_MTDPARTS 771 #define CONFIG_FLASH_CFI_MTD 772 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 773 "spi0=spife110000.0" 774 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 775 "128k(dtb),96m(fs),-(user);"\ 776 "fff800000.flash:2m(uboot),9m(kernel),"\ 777 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 778 "2m(uboot),9m(kernel),128k(dtb),-(user)" 779 #endif 780 781 /* 782 * Environment 783 */ 784 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 785 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 786 787 /* 788 * Command line configuration. 789 */ 790 #define CONFIG_CMD_DATE 791 #define CONFIG_CMD_EEPROM 792 #define CONFIG_CMD_ERRATA 793 #define CONFIG_CMD_IRQ 794 #define CONFIG_CMD_REGINFO 795 796 #ifdef CONFIG_PCI 797 #define CONFIG_CMD_PCI 798 #endif 799 800 /* 801 * Miscellaneous configurable options 802 */ 803 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 804 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 805 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 806 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 807 #ifdef CONFIG_CMD_KGDB 808 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 809 #else 810 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 811 #endif 812 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 813 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 814 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 815 816 /* 817 * For booting Linux, the board info and command line data 818 * have to be in the first 64 MB of memory, since this is 819 * the maximum mapped by the Linux kernel during initialization. 820 */ 821 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 822 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 823 824 #ifdef CONFIG_CMD_KGDB 825 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 826 #endif 827 828 /* 829 * Environment Configuration 830 */ 831 #define CONFIG_ROOTPATH "/opt/nfsroot" 832 #define CONFIG_BOOTFILE "uImage" 833 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 834 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 835 #define CONFIG_BAUDRATE 115200 836 #define __USB_PHY_TYPE utmi 837 838 #define CONFIG_EXTRA_ENV_SETTINGS \ 839 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 840 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 841 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 842 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 843 "fdtfile=t1024qds/t1024qds.dtb\0" \ 844 "netdev=eth0\0" \ 845 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 846 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 847 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 848 "tftpflash=tftpboot $loadaddr $uboot && " \ 849 "protect off $ubootaddr +$filesize && " \ 850 "erase $ubootaddr +$filesize && " \ 851 "cp.b $loadaddr $ubootaddr $filesize && " \ 852 "protect on $ubootaddr +$filesize && " \ 853 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 854 "consoledev=ttyS0\0" \ 855 "ramdiskaddr=2000000\0" \ 856 "fdtaddr=d00000\0" \ 857 "bdev=sda3\0" 858 859 #define CONFIG_LINUX \ 860 "setenv bootargs root=/dev/ram rw " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "setenv ramdiskaddr 0x02000000;" \ 863 "setenv fdtaddr 0x00c00000;" \ 864 "setenv loadaddr 0x1000000;" \ 865 "bootm $loadaddr $ramdiskaddr $fdtaddr" 866 867 #define CONFIG_NFSBOOTCOMMAND \ 868 "setenv bootargs root=/dev/nfs rw " \ 869 "nfsroot=$serverip:$rootpath " \ 870 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 871 "console=$consoledev,$baudrate $othbootargs;" \ 872 "tftp $loadaddr $bootfile;" \ 873 "tftp $fdtaddr $fdtfile;" \ 874 "bootm $loadaddr - $fdtaddr" 875 876 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 877 878 /* Hash command with SHA acceleration supported in hardware */ 879 #ifdef CONFIG_FSL_CAAM 880 #define CONFIG_CMD_HASH 881 #define CONFIG_SHA_HW_ACCEL 882 #endif 883 884 #include <asm/fsl_secure_boot.h> 885 886 #endif /* __T1024QDS_H */ 887