1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 QDS board configuration file 8 */ 9 10 #ifndef __T1024QDS_H 11 #define __T1024QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 #define CONFIG_DEEP_SLEEP 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 33 #define CONFIG_SPL_PAD_TO 0x40000 34 #define CONFIG_SPL_MAX_SIZE 0x28000 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SPL_SKIP_RELOCATE 39 #define CONFIG_SPL_COMMON_INIT_DDR 40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 50 #define CONFIG_SPL_NAND_BOOT 51 #endif 52 53 #ifdef CONFIG_SPIFLASH 54 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 55 #define CONFIG_SPL_SPI_FLASH_MINIMAL 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 61 #ifndef CONFIG_SPL_BUILD 62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 63 #endif 64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 65 #define CONFIG_SPL_SPI_BOOT 66 #endif 67 68 #ifdef CONFIG_SDCARD 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 70 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 72 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 73 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 75 #ifndef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 77 #endif 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 79 #define CONFIG_SPL_MMC_BOOT 80 #endif 81 82 #endif /* CONFIG_RAMBOOT_PBL */ 83 84 #ifndef CONFIG_RESET_VECTOR_ADDRESS 85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 86 #endif 87 88 #ifdef CONFIG_MTD_NOR_FLASH 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_CFI 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 92 #endif 93 94 /* PCIe Boot - Master */ 95 #define CONFIG_SRIO_PCIE_BOOT_MASTER 96 /* 97 * for slave u-boot IMAGE instored in master memory space, 98 * PHYS must be aligned based on the SIZE 99 */ 100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 102 #ifdef CONFIG_PHYS_64BIT 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 105 #else 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 108 #endif 109 /* 110 * for slave UCODE and ENV instored in master memory space, 111 * PHYS must be aligned based on the SIZE 112 */ 113 #ifdef CONFIG_PHYS_64BIT 114 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 116 #else 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 119 #endif 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 121 /* slave core release by master*/ 122 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 123 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 124 125 /* PCIe Boot - Slave */ 126 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 127 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 128 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 129 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 130 /* Set 1M boot space for PCIe boot */ 131 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 132 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 133 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 134 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 135 #endif 136 137 #if defined(CONFIG_SPIFLASH) 138 #define CONFIG_SYS_EXTRA_ENV_RELOC 139 #define CONFIG_ENV_SPI_BUS 0 140 #define CONFIG_ENV_SPI_CS 0 141 #define CONFIG_ENV_SPI_MAX_HZ 10000000 142 #define CONFIG_ENV_SPI_MODE 0 143 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 144 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 145 #define CONFIG_ENV_SECT_SIZE 0x10000 146 #elif defined(CONFIG_SDCARD) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_SYS_MMC_ENV_DEV 0 149 #define CONFIG_ENV_SIZE 0x2000 150 #define CONFIG_ENV_OFFSET (512 * 0x800) 151 #elif defined(CONFIG_NAND) 152 #define CONFIG_SYS_EXTRA_ENV_RELOC 153 #define CONFIG_ENV_SIZE 0x2000 154 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 155 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 156 #define CONFIG_ENV_ADDR 0xffe20000 157 #define CONFIG_ENV_SIZE 0x2000 158 #elif defined(CONFIG_ENV_IS_NOWHERE) 159 #define CONFIG_ENV_SIZE 0x2000 160 #else 161 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 164 #endif 165 166 #ifndef __ASSEMBLY__ 167 unsigned long get_board_sys_clk(void); 168 unsigned long get_board_ddr_clk(void); 169 #endif 170 171 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 172 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 173 174 /* 175 * These can be toggled for performance analysis, otherwise use default. 176 */ 177 #define CONFIG_SYS_CACHE_STASHING 178 #define CONFIG_BACKSIDE_L2_CACHE 179 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 180 #define CONFIG_BTB /* toggle branch predition */ 181 #define CONFIG_DDR_ECC 182 #ifdef CONFIG_DDR_ECC 183 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 184 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 185 #endif 186 187 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 188 #define CONFIG_SYS_MEMTEST_END 0x00400000 189 190 /* 191 * Config the L3 Cache as L3 SRAM 192 */ 193 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 194 #define CONFIG_SYS_L3_SIZE (256 << 10) 195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 196 #ifdef CONFIG_RAMBOOT_PBL 197 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 198 #endif 199 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 200 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 201 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 202 203 #ifdef CONFIG_PHYS_64BIT 204 #define CONFIG_SYS_DCSRBAR 0xf0000000 205 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 206 #endif 207 208 /* EEPROM */ 209 #define CONFIG_ID_EEPROM 210 #define CONFIG_SYS_I2C_EEPROM_NXID 211 #define CONFIG_SYS_EEPROM_BUS_NUM 0 212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 216 217 /* 218 * DDR Setup 219 */ 220 #define CONFIG_VERY_BIG_RAM 221 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 222 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 223 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 224 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 225 #define CONFIG_DDR_SPD 226 227 #define CONFIG_SYS_SPD_BUS_NUM 0 228 #define SPD_EEPROM_ADDRESS 0x51 229 230 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 231 232 /* 233 * IFC Definitions 234 */ 235 #define CONFIG_SYS_FLASH_BASE 0xe0000000 236 #ifdef CONFIG_PHYS_64BIT 237 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 238 #else 239 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 240 #endif 241 242 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 243 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 244 + 0x8000000) | \ 245 CSPR_PORT_SIZE_16 | \ 246 CSPR_MSEL_NOR | \ 247 CSPR_V) 248 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 249 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 250 CSPR_PORT_SIZE_16 | \ 251 CSPR_MSEL_NOR | \ 252 CSPR_V) 253 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 254 /* NOR Flash Timing Params */ 255 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 256 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 257 FTIM0_NOR_TEADC(0x5) | \ 258 FTIM0_NOR_TEAHC(0x5)) 259 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 260 FTIM1_NOR_TRAD_NOR(0x1A) |\ 261 FTIM1_NOR_TSEQRAD_NOR(0x13)) 262 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 263 FTIM2_NOR_TCH(0x4) | \ 264 FTIM2_NOR_TWPH(0x0E) | \ 265 FTIM2_NOR_TWP(0x1c)) 266 #define CONFIG_SYS_NOR_FTIM3 0x0 267 268 #define CONFIG_SYS_FLASH_QUIET_TEST 269 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 270 271 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 272 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 273 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 274 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 275 276 #define CONFIG_SYS_FLASH_EMPTY_INFO 277 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 278 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 279 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 280 #define QIXIS_BASE 0xffdf0000 281 #ifdef CONFIG_PHYS_64BIT 282 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 283 #else 284 #define QIXIS_BASE_PHYS QIXIS_BASE 285 #endif 286 #define QIXIS_LBMAP_SWITCH 0x06 287 #define QIXIS_LBMAP_MASK 0x0f 288 #define QIXIS_LBMAP_SHIFT 0 289 #define QIXIS_LBMAP_DFLTBANK 0x00 290 #define QIXIS_LBMAP_ALTBANK 0x04 291 #define QIXIS_RST_CTL_RESET 0x31 292 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 293 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 294 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 295 #define QIXIS_RST_FORCE_MEM 0x01 296 297 #define CONFIG_SYS_CSPR3_EXT (0xf) 298 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 299 | CSPR_PORT_SIZE_8 \ 300 | CSPR_MSEL_GPCM \ 301 | CSPR_V) 302 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 303 #define CONFIG_SYS_CSOR3 0x0 304 /* QIXIS Timing parameters for IFC CS3 */ 305 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 306 FTIM0_GPCM_TEADC(0x0e) | \ 307 FTIM0_GPCM_TEAHC(0x0e)) 308 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 309 FTIM1_GPCM_TRAD(0x3f)) 310 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 311 FTIM2_GPCM_TCH(0x8) | \ 312 FTIM2_GPCM_TWP(0x1f)) 313 #define CONFIG_SYS_CS3_FTIM3 0x0 314 315 #define CONFIG_NAND_FSL_IFC 316 #define CONFIG_SYS_NAND_BASE 0xff800000 317 #ifdef CONFIG_PHYS_64BIT 318 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 319 #else 320 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 321 #endif 322 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 323 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 324 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 325 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 326 | CSPR_V) 327 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 328 329 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 330 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 331 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 332 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 333 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 334 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 335 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 336 337 #define CONFIG_SYS_NAND_ONFI_DETECTION 338 339 /* ONFI NAND Flash mode0 Timing Params */ 340 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 341 FTIM0_NAND_TWP(0x18) | \ 342 FTIM0_NAND_TWCHT(0x07) | \ 343 FTIM0_NAND_TWH(0x0a)) 344 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 345 FTIM1_NAND_TWBE(0x39) | \ 346 FTIM1_NAND_TRR(0x0e) | \ 347 FTIM1_NAND_TRP(0x18)) 348 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 349 FTIM2_NAND_TREH(0x0a) | \ 350 FTIM2_NAND_TWHRE(0x1e)) 351 #define CONFIG_SYS_NAND_FTIM3 0x0 352 353 #define CONFIG_SYS_NAND_DDR_LAW 11 354 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 355 #define CONFIG_SYS_MAX_NAND_DEVICE 1 356 357 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 358 359 #if defined(CONFIG_NAND) 360 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 361 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 369 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 370 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 371 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 372 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 373 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 374 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 375 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 376 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 377 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 378 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 379 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 380 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 381 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 382 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 383 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 384 #else 385 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 386 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 387 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 388 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 389 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 390 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 391 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 392 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 393 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 394 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 395 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 396 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 397 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 398 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 399 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 400 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 401 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 402 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 403 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 404 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 405 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 406 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 407 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 408 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 409 #endif 410 411 #ifdef CONFIG_SPL_BUILD 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 413 #else 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 415 #endif 416 417 #if defined(CONFIG_RAMBOOT_PBL) 418 #define CONFIG_SYS_RAMBOOT 419 #endif 420 421 #define CONFIG_HWCONFIG 422 423 /* define to use L1 as initial stack */ 424 #define CONFIG_L1_INIT_RAM 425 #define CONFIG_SYS_INIT_RAM_LOCK 426 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 430 /* The assembler doesn't like typecast */ 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 432 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 433 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 434 #else 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 438 #endif 439 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 440 441 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 442 GENERATED_GBL_DATA_SIZE) 443 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 444 445 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 446 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 447 448 /* Serial Port */ 449 #define CONFIG_SYS_NS16550_SERIAL 450 #define CONFIG_SYS_NS16550_REG_SIZE 1 451 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 452 453 #define CONFIG_SYS_BAUDRATE_TABLE \ 454 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 455 456 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 457 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 458 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 459 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 460 461 /* Video */ 462 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 463 #define CONFIG_FSL_DIU_FB 464 #ifdef CONFIG_FSL_DIU_FB 465 #define CONFIG_FSL_DIU_CH7301 466 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 467 #define CONFIG_VIDEO_LOGO 468 #define CONFIG_VIDEO_BMP_LOGO 469 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 470 /* 471 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 472 * disable empty flash sector detection, which is I/O-intensive. 473 */ 474 #undef CONFIG_SYS_FLASH_EMPTY_INFO 475 #endif 476 #endif 477 478 /* I2C */ 479 #define CONFIG_SYS_I2C 480 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 481 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 482 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 483 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 484 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 485 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 486 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 487 488 #define I2C_MUX_PCA_ADDR 0x77 489 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 490 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 491 #define I2C_RETIMER_ADDR 0x18 492 493 /* I2C bus multiplexer */ 494 #define I2C_MUX_CH_DEFAULT 0x8 495 #define I2C_MUX_CH_DIU 0xC 496 #define I2C_MUX_CH5 0xD 497 #define I2C_MUX_CH7 0xF 498 499 /* LDI/DVI Encoder for display */ 500 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 501 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 502 503 /* 504 * RTC configuration 505 */ 506 #define RTC 507 #define CONFIG_RTC_DS3231 1 508 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 509 510 /* 511 * eSPI - Enhanced SPI 512 */ 513 #define CONFIG_SPI_FLASH_BAR 514 #define CONFIG_SF_DEFAULT_SPEED 10000000 515 #define CONFIG_SF_DEFAULT_MODE 0 516 517 /* 518 * General PCIe 519 * Memory space is mapped 1-1, but I/O space must start from 0. 520 */ 521 #define CONFIG_PCIE1 /* PCIE controller 1 */ 522 #define CONFIG_PCIE2 /* PCIE controller 2 */ 523 #define CONFIG_PCIE3 /* PCIE controller 3 */ 524 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 525 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 526 #define CONFIG_PCI_INDIRECT_BRIDGE 527 528 #ifdef CONFIG_PCI 529 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 530 #ifdef CONFIG_PCIE1 531 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 532 #ifdef CONFIG_PHYS_64BIT 533 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 534 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 535 #else 536 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 537 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 538 #endif 539 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 540 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 541 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 542 #ifdef CONFIG_PHYS_64BIT 543 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 544 #else 545 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 546 #endif 547 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 548 #endif 549 550 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 551 #ifdef CONFIG_PCIE2 552 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 553 #ifdef CONFIG_PHYS_64BIT 554 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 555 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 556 #else 557 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 558 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 559 #endif 560 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 561 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 562 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 563 #ifdef CONFIG_PHYS_64BIT 564 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 565 #else 566 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 567 #endif 568 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 569 #endif 570 571 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 572 #ifdef CONFIG_PCIE3 573 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 574 #ifdef CONFIG_PHYS_64BIT 575 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 576 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 577 #else 578 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 579 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 580 #endif 581 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 582 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 583 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 584 #ifdef CONFIG_PHYS_64BIT 585 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 586 #else 587 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 588 #endif 589 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 590 #endif 591 592 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 593 #endif /* CONFIG_PCI */ 594 595 /* 596 *SATA 597 */ 598 #define CONFIG_FSL_SATA_V2 599 #ifdef CONFIG_FSL_SATA_V2 600 #define CONFIG_SYS_SATA_MAX_DEVICE 1 601 #define CONFIG_SATA1 602 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 603 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 604 #define CONFIG_LBA48 605 #endif 606 607 /* 608 * USB 609 */ 610 #define CONFIG_HAS_FSL_DR_USB 611 612 #ifdef CONFIG_HAS_FSL_DR_USB 613 #define CONFIG_USB_EHCI_FSL 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 615 #endif 616 617 /* 618 * SDHC 619 */ 620 #ifdef CONFIG_MMC 621 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 622 #endif 623 624 /* Qman/Bman */ 625 #ifndef CONFIG_NOBQFMAN 626 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 627 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 628 #ifdef CONFIG_PHYS_64BIT 629 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 630 #else 631 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 632 #endif 633 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 634 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 635 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 636 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 637 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 638 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 639 CONFIG_SYS_BMAN_CENA_SIZE) 640 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 642 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 643 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 644 #ifdef CONFIG_PHYS_64BIT 645 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 646 #else 647 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 648 #endif 649 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 650 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 651 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 652 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 653 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 654 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 655 CONFIG_SYS_QMAN_CENA_SIZE) 656 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 657 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 658 659 #define CONFIG_SYS_DPAA_FMAN 660 661 #define CONFIG_QE 662 #define CONFIG_U_QE 663 /* Default address of microcode for the Linux FMan driver */ 664 #if defined(CONFIG_SPIFLASH) 665 /* 666 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 667 * env, so we got 0x110000. 668 */ 669 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 670 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 671 #define CONFIG_SYS_QE_FW_ADDR 0x130000 672 #elif defined(CONFIG_SDCARD) 673 /* 674 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 675 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 676 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 677 */ 678 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 679 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 680 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 681 #elif defined(CONFIG_NAND) 682 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 683 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 684 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 685 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 686 /* 687 * Slave has no ucode locally, it can fetch this from remote. When implementing 688 * in two corenet boards, slave's ucode could be stored in master's memory 689 * space, the address can be mapped from slave TLB->slave LAW-> 690 * slave SRIO or PCIE outbound window->master inbound window-> 691 * master LAW->the ucode address in master's memory space. 692 */ 693 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 694 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 695 #else 696 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 697 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 698 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 699 #endif 700 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 701 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 702 #endif /* CONFIG_NOBQFMAN */ 703 704 #ifdef CONFIG_SYS_DPAA_FMAN 705 #define CONFIG_FMAN_ENET 706 #define CONFIG_PHYLIB_10G 707 #define CONFIG_PHY_VITESSE 708 #define CONFIG_PHY_REALTEK 709 #define CONFIG_PHY_TERANETICS 710 #define RGMII_PHY1_ADDR 0x1 711 #define RGMII_PHY2_ADDR 0x2 712 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 713 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 714 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 715 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 716 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 717 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 718 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 719 #endif 720 721 #ifdef CONFIG_FMAN_ENET 722 #define CONFIG_ETHPRIME "FM1@DTSEC4" 723 #endif 724 725 /* 726 * Dynamic MTD Partition support with mtdparts 727 */ 728 #ifdef CONFIG_MTD_NOR_FLASH 729 #define CONFIG_FLASH_CFI_MTD 730 #endif 731 732 /* 733 * Environment 734 */ 735 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 736 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 737 738 /* 739 * Miscellaneous configurable options 740 */ 741 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 742 743 /* 744 * For booting Linux, the board info and command line data 745 * have to be in the first 64 MB of memory, since this is 746 * the maximum mapped by the Linux kernel during initialization. 747 */ 748 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 749 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 750 751 #ifdef CONFIG_CMD_KGDB 752 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 753 #endif 754 755 /* 756 * Environment Configuration 757 */ 758 #define CONFIG_ROOTPATH "/opt/nfsroot" 759 #define CONFIG_BOOTFILE "uImage" 760 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 761 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 762 #define __USB_PHY_TYPE utmi 763 764 #define CONFIG_EXTRA_ENV_SETTINGS \ 765 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 766 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 767 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 768 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 769 "fdtfile=t1024qds/t1024qds.dtb\0" \ 770 "netdev=eth0\0" \ 771 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 772 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 773 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 774 "tftpflash=tftpboot $loadaddr $uboot && " \ 775 "protect off $ubootaddr +$filesize && " \ 776 "erase $ubootaddr +$filesize && " \ 777 "cp.b $loadaddr $ubootaddr $filesize && " \ 778 "protect on $ubootaddr +$filesize && " \ 779 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 780 "consoledev=ttyS0\0" \ 781 "ramdiskaddr=2000000\0" \ 782 "fdtaddr=d00000\0" \ 783 "bdev=sda3\0" 784 785 #define CONFIG_LINUX \ 786 "setenv bootargs root=/dev/ram rw " \ 787 "console=$consoledev,$baudrate $othbootargs;" \ 788 "setenv ramdiskaddr 0x02000000;" \ 789 "setenv fdtaddr 0x00c00000;" \ 790 "setenv loadaddr 0x1000000;" \ 791 "bootm $loadaddr $ramdiskaddr $fdtaddr" 792 793 #define CONFIG_NFSBOOTCOMMAND \ 794 "setenv bootargs root=/dev/nfs rw " \ 795 "nfsroot=$serverip:$rootpath " \ 796 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr - $fdtaddr" 801 802 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 803 804 #include <asm/fsl_secure_boot.h> 805 806 #endif /* __T1024QDS_H */ 807